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JNTU ONLINE EXAMINATIONS [Mid 2 - mca]

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In a. b. c. d.

1974, Texas instruments introduced the first microcontroller is ____ [01D01] TMS 5000 TMS 1000 TMS 8000 TMS 9000

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ATMEL 89C2051 Is one example of Embedded Controller has - pins [01D02] a. 20 pins b. 80 pins c. 90 pins d. 100 pins Following are the microcontrollers [01M01] a. 8085 b. 8086 c. 80486 d. MCS-96 ASSPs are stand for [01M02] a. Application specific standard products b. Application special suited products c. Application suited for sim power d. Appropriate specific standard products 8085 is a __ bit processor [01M03] a. 2 bit b. 8 bit c. . 16 bit d. 32 bit 8086 is a_____ bit processor [01M04] a. 2 bit b. 8 bit c. 16 bit d. 32 bit Date storage and processing is an integral part of any automatic control systems is called [01S01] a. Microprocessor b. microcontroller c. any chip d. RAM Some of the microcontrollers are not used commonly [01S02] a. Intel MCS-51 b. MCS-96 c. Motorola 68HC12 family d. Microsoft Single- chip microcomputers are called --- [01S03] a. Microprocessor b. microcontroller c. any chip d. RAM PIC stands for _____ [01S04] a. Peripheral interface controller b. Peripheral interface command c. Powerful input cartridge d. Peripheral input controller CISC Stands for [02D01] a. Cover Instruction Set computer b. Complete Instruction Set computers c. Complete Reduced Instruction Set Computers

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d. 12.

Cover illegal set operations.

RISC Stands for [02D02] a. Cover Instruction Set computer b. Reduced Instruction Set Computer c. Complete Reduced Instruction Set Computers d. Cover illegal set operations. MCS - 51 is a ____ bit microcontroller [02M01] a. 2 bit b. 8 bit c. 16 bit d. 32 bit MCS - 96 is a_____ bit microcontroller [02M02] a. 2 bit b. 8 bit c. 16 bit d. 32 bit CHMOS IS STAND FOR [02M03] a. Complementary high speed metal oxide semiconductor technology b. conversion high speed metal oxide semiconductor technology c. Complementary high speed more oxide semiconductor technology d. Complementary high speed metal oxide silico conductor technology 8031 have on-chip data memory bytes [02M04] a. 128 b. 256 c. 62 d. 32 8088 is a _____bit processor [02S01] a. 2 bit b. 8 bit c. 16 bit d. 32 bit In a. b. c. d. Von Neumann architecture, programs and data share the______memory space. [02S02] Different Same Not defined Different,Same and Not defined

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Program and date fetches the memory by using ______ [02S03] a. Time division b. Frequency division c. Space division d. Wavelength division. HMOS IS STAND FOR [02S04] a. high speed metal oxide semiconductor technology b. huge speed metal oxide semiconductor technology c. high speed more oxide semiconductor technology d. high speed metal oxide silicon conductor technology 8032 have on-chip program memory [03D01] a. EPROM b. ROM c. RAM d. NONE 8051 have on-chip program memory [03D02] a. EPROM b. ROM c. 8KROM d. 4K ROM 8752 have on-chip program memory [03D03]

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a. b. c. d. 24.

EPROM 8K EPROM 8KROM 4K ROM

8032 have on-chip data memory bytes [03M01] a. 128 b. 256 c. 62 d. 32 8751 have on-chip data memory bytes [03M02] a. 128 b. 256 c. 62 d. 32 8031 have on-chip program memory [03M03] a. EPROM b. ROM c. RAM d. NONE 8052 have on-chip program memory [03M04] a. EPROM b. ROM c. 8KROM d. 4K ROM 8752 have on-chip data memory bytes [03S01] a. 128 b. 256 c. 62 d. 32 For Atmel 89C4051 microcontroller operating voltage range is_____ [03S02] a. 0-9V b. 0-8V c. 0-6v d. 0-100V 8751 have on-chip program memory [03S03] a. EPROM b. 4K EPROM c. 8KROM d. 4K ROM In a. b. c. d. Stepper Motor, The phase refers to the _______ [04D01] Number of separate winding circuits Number of same winding circuits Phase difference between windings All windings in the stepper motor are 180 degrees out of phase

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The Atmel Microcontrollers have ( AT89C52) have on-chip program memory ( flash) [04D02] a. 4K b. 8K c. 20 K d. 2K PIC 16 XXX and PIC 17CXX is a______ [04D03] a. 8 bit micro controller b. 16 bit micro controller c. 32 bit micro controller d. 64 bit micro controller 16C71 PIC Micro controllers has ADC channels [04D04] a. 8 bit ADC b. 10 bit ADC c. 16 bit ADC

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d. 35.

32 Bit ADC

The Power down modules and IDLE modes can be used to keep the power consumption to a ---------- level; [04M01] a. Maximum b. Minimum c. Peak level d. Not related The Atmel Microcontrollers have ( AT89C55WD) have on-chip program memory ( flash) [04M02] a. 4K b. 8K c. 20 K d. 2K The Atmel Microcontrollers have ( AT89C2051) have on-chip program memory ( flash) [04M03] a. 4K b. 8K c. 20 K d. 2K The Atmel Microcontrollers have ( AT89LV52) have on-chip program memory ( flash) [04S01] a. 4K b. 8K c. 20 K d. 2K The Atmel Microcontrollers have ( AT89C2051) have DIGIAL I/O's [04S02] a. 32 b. 15 c. 16 d. 8 The Atmel Microcontrollers have ( AT89C1051) have DIGIAL I/O's' [04S03] a. 32 b. 15 c. 16 d. 8 ALU of 8051 performs arithmetic and logical operation on ______ [05D01] a. 8 bit operands b. 16 bit operands c. 32 bit operands d. 64 bit operands The following is the not timing and control of MCS - 51 has [05D02] a. PSEN b. RD c. WR, ALE d. CASHE The following is the not timing and control of MCS - 51 has [05D03] a. PSEN b. RD c. WR, ALE d. CASHE ULN-2003 micro controller has 12, 11, 10 pins are used for [05M01] a. VCC b. Ground c. Input d. Output The are ------------ register banks in the on chip RAM, each having 8 bit wide registers RO through R7 [05M02] a. four b. five c. six d. seven

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stack Pointer has a ------------ bit [05M03] a. 16 bit b. 8 bit c. 32 bit d. 64 bit Stack Pointer has a ------------ bit [05M04] a. 16 bit b. 8 bit c. 32 bit d. 64 bit MCS - 51 is a family of 8-bit micro controller operating at ______ frequency. [05S01] a. 12 MHz b. 24 MHz c. 32 MHz d. 64 MHz The whole operation of 8051 microcontroller is ______ with the clock. [05S02] a. synchronous b. not synchronous c. equal d. not equal Access to accumulator is ------------------ than access to main memory. [05S03] a. faster b. slower c. equal d. not equal Stack Pointer of 8051 is a ------------ wide. [05S04] a. 8 bit b. 16 bit c. 3 bit d. 2 bit The following adjustment is automatically done by DAA instruction in 8051 Microcontrollers. [06D01] a. Decimal b. floating point c. binary d. fraction In the following program, DAA instruction is executed after Mov A, #BCD1 Mov B, #BCD2 ADD A, B DAA [06D02] a. ADDC instruction b. Mov A, #BCD1 c. Mov B, #BCD2 d. DAA Pin 8 of the ULN-2003 microcontroller is ________ [06D03] a. VCC b. Ground c. Input d. Output In a. b. c. d. Stepper Motor, The phase refers to the________ [06D04] Number of separate winding circuits Number of same winding circuits Phase difference between windings All windings in the stepper motor are 180 degrees out of phase

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The 128 bytes of on chip additional RAM locations from 80H to OFFH are reserved for the special function and therefore these are called as ---------- [06M01] a. Special function registers

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b. c. d. 57.

special purpose registers automatic shift registers cyclic register.

ULN-2003 micro controller has 5,6, 7 pins are used for [06M02] a. VCC b. Ground c. Input d. Output. 'In Micro controller, User interface certainly not needs basic components like the following_______ [06M03] a. LED's b. Push buttons c. Relays and latches d. Micro processor Use of Serial ADC, SPI and I2 C bus interface can ______-the number of microcontroller pins [06S01] a. save b. not saved c. generate d. accumulate ULN-2003 has_____Darlington drivers with internal diodes, which provide path for current in the coil when the transistor is turned off. [06S02] a. 7 b. 8 c. 9 d. 10 ULN-2003 micro controller has 12, 11, 10 pins are used for [06S03] a. VCC b. Ground c. Input d. Output The advantage of using a real-time replacement kernel such as_______ is that there are no limits on size or complexity of the real-time application code [07M01] a. LynxOS b. VXworks c. RTOS of Keil d. RTX51 A________ is an interrupt generated within a processor by executing an instruction [07M02] a. maskable interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrupt A_________is a class of interrupts where the presence of an unserviced interrupt is indicated by a high level (1), or low level (0), of the interrupt request line [07M03] a. level-triggered interrupt b. Edge triggered interrupt c. Hybrid triggered interrupt d. Message signalled interrupt ULN-2003 micro controller has 5,6, 7 pins are used for [07M04] a. VCC b. Ground c. Input d. Output VxWorks is a real-time operating system made and sold by Wind River Systems of Alameda, ---------------- [07M05] a. California, USA. b. Japan c. Canada

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d. 67.

Australia

An______is a special case of interrupt that is generated by one processor to interrupt another processor in a multiprocessor system. [07S01] a. maskable interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrupt A_________is a hardware interrupt that is unwanted. They are typically generated by system conditions such as electrical interference on an interrupt line or through incorrectly designed hardware. [07S02] a. spurious interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrupt First-In-First-Out pipes (FIFOs) or shared memory can be used to________ between the operating system and the real-time core. [07S03] a. transfer data b. share data c. destroy data d. store data --------------------introduces the concepts and methodologies employed in designing a system -onchip based around a microprocessor core, and in designing the core itself. [07S04] a. ARM System-on-Chip Architecture b. 80196 MICRO CONTROLLER c. Prototype MCU based measuring instruments. d. Non masking interrupt sources ARM has Fixed-length_______bit instructions [08M01] a. 8 bit b. 16 bit c. 32 bit d. 64 bit In a. b. c. d. ARM, ' frq' is used for [08M02] general purpose interrupt handling a protected mode for the operating system supports a high speed data transfer or channel process. implements virtual memory and memory protection

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ARM microcontroller have following registers in this architecture [08M03] a. 58 registers b. 37 registers c. 55 registers d. 10 registers 80196 micro controller have Up to_______ Bytes of program memory [08M04] a. 256K b. 128 K c. 8K d. 1026 K Time-sharing designs switch tasks on a clock interrupt, and on events, called [08M05] a. round robin b. shared robin c. circularly shift d. right shift ARM9TDMI Compatible with________ [08S01] a. ARM 7 b. ARM 14 c. ARM 25 d. ARM 45 In ARM, IRQ is used for [08S02] a. general purpose interrupt handling

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b. c. d. 78. In a. b. c. d.

a protected mode for the operating system supports a high speed data transfer or channel process. implements virtual memory and memory protection ARM, 'ab' is used for [08S03] Virtual memory and /or channel process. a protected mode for the operating system supports a high speed data transfer or channel process. implements virtual memory and memory protection

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Real-time non-intrusive emulation for the 80C196 microcontrollers used up to_________ [08S04] a. 25 MHz b. 80 MHz c. 108 MHz d. 800 MHz. More recent CPUs take far less time to switch from one task to another, the extreme case is ________ that switch from one task to the next in zero cycles [08S05] a. barrel processor b. PIV processor c. dual core processor d. micro processor Memory allocation is even more________ in an RTOS than in other operating systems [09D01] a. easy b. critical c. not related d. speed The simple_______algorithm works astonishingly well for simple embedded systems [09D02] a. fixed-size-blocks b. variable size blocks c. zero size blocks d. random size blocks A__________(IRQ) is a hardware interrupt that may be ignored by setting a bit in an interrupt mask register's (IMR) bit-mask. [09D03] a. maskable interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrupt Systems must manage sharing data and hardware resources among multiple tasks. [09M01] a. Multi tasking b. single tasking c. schedule tasking d. restore tasking Problems with semaphore based designs are well known: [09M02] a. priority inversion b. deadlocks. c. both priority inversion and deadlocks. d. multi tasking In a ________, two or more tasks lock a number of binary semaphores and then wait forever (no timeout) for other binary semaphores, creating a cyclic dependency graph. [09M03] a. priority inversion b. dead lock c. multi tasking d. scheduling Since an interrupt handler blocks the ________task from running, and since real time operating systems are designed to keep thread latency to a minimum, interrupt handlers are typically kept as short as possible [09M04] a. highest priority b. lowest priority c. none of the priority

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d. 88.

zero priority

____behave very much like edge-triggered interrupts, in that the interrupt is a momentary signal rather than a continuous condition [09S01] a. level-triggered interrupt b. Edge triggered interrupt c. Hybrid triggered interrupt d. Software interrupt. In a. b. c. d. _______, a high priority task waits because a low priority task has a semaphore [09S02] priority inversion dead lock multi tasking scheduling

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Protocol deadlocks occur when ________tasks wait for each other to send response messages. [09S03] a. 0.5 b. two or more c. 1 d. no tasks Likewise, a________ (NMI) is a hardware interrupt that does not have a bit-mask associated with it - meaning that it can never be ignored [10D01] a. maskable interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrupt An______is a special case of interrupt that is generated by one processor to interrupt another processor in a multiprocessor system. [10D02] a. maskable interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrupt A________ is an interrupt generated within a processor by executing an instruction [10M01] a. maskable interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrupt A ________is a hardware interrupt that is unwanted. They are typically generated by system conditions such as electrical interference on an interrupt line or through incorrectly designed hardware. [10M02] a. spurious interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrup ________behave very much like edge-triggered interrupts, in that the interrupt is a momentary signal rather than a continuous condition [10M03] a. level-triggered interrupt b. Edge triggered interrupt c. Hybrid triggered interrupt d. Software interrupt A ________is a class of interrupts where the presence of an unserviced interrupt is indicated by a high level (1), or low level (0), of the interrupt request line [10S01] a. level-triggered interrupt b. Edge triggered interrupt c. Hybrid triggered interrupt d. Message signalled interrupt An ------------------is a class of interrupts that are signalled by a level transition on the interrupt line, either a falling edge (1 to 0) or a rising edge (0 to 1). [10S02] a. level-triggered interrupt b. Edge triggered interrupt

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c. d. 98.

Hybrid triggered interrupt Message signalled interrupt

The hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time [10S03] a. level-triggered interrupt b. Edge triggered interrupt c. Hybrid triggered interrupt d. Message signalled interrupt A device signals its request for service by sending a short message over some communications medium, typically a computer bus. [10S04] a. . level-triggered interrupt b. Edge triggered interrupt c. Hybrid triggered interrupt d. Message signalled interrupt Is a set of techniques for the exchange of data among two or more threads in one or more processes. Processes may be running on one or more computers connected by a network [11D01] a. Inter-Process Communication (IPC) b. Intra Process communication c. asymmetric multi processing d. computer clustered multiprocessing ___________ is defined as the temporal difference between the deadline, the ready time and the run time [11D02] a. Slack time b. least slack time c. stability d. suitability Whereas a counts upwards from zero for measuring elapsed time, a timer counts down from a specified time interval, like a sand clock. [11D03] a. Timer b. Scheduler c. Stopwatch d. Counter SCADA is the abbreviation for _________ [11M01] a. Supervisory Control And Data Acquisition b. Supervisory chemical and dental aquarium c. Supervisory Control And Data attention d. Silicon Control And Data Acquisition Microcontrollers were originally programmed only in assembly language, but various high-level programming languages are now also in common use to target microcontrollers. These languages are either designed specially for the purpose, or versions of general purpose languages such as the________ programming language [11M02] a. Java language b. C language c. core java d. VC++ MIPS STANDS FOR _________ [11M03] a. Microprocessor without Interlocked Pipeline Stages b. Microprocessor with Interlocked Pipeline Stages c. MicroCONTROLLER without Interlocked Pipeline Stages d. Microprocessor without Inter Pipeline Stages In computing,__________involves a multiprocessor computer-architecture where two or more identical processors can connect to a single shared main memory [11S01] a. symmetric multiprocessing or SMP b. unsystamatic multiprocessing c. multitasking d. scheduling (such as Beowulf), in which not all memory is available to all processors [11S02] a. computer clustered multiprocessing

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b. c. d. 108.

unsystamatic cultiprocessing asymmetric multiprocessing single processor

The vast majority of robots use electric motors, including brushed and brushless ________ motors [11S03] a. DC motor b. AC Motor c. ultra sonic motor d. piezo motor HP-IB is stands for [12D01] a. Hewlett-Packard Instrument Bus b. General Purpose Interface Bus c. Hewlett-packard isolation bus d. General Purpose isolation Bus IEEE-488 allows up to__________devices to share a single 8-bit parallel electrical bus by daisy chaining connections [12D02] a. 25 b. 15 c. 39 d. 89 Digital timers can achieve higher precision than mechanical timers because they are ____with special electronics [12M01] a. quartz clocks b. analog clock c. digital clock d. quartz clocks and analog clock ucLinux is probably the best choice if your device has plenty of____________ [12M02] a. flash and RAM memory b. internal and external memory c. cache and external memory d. EPROM and ROM Memory Following is the operating system for ''Open Systems and their interfaces for the Electronics in Motor vehicles'' is [12M03] a. VXworks b. ucLinux c. RTX51 d. OSEK/VDX ARM7TDMI Features_________bit Thumb instruction set for increased code density [12M04] a. 16 bit b. 32 bit c. 64 bit d. 8 bit GPIB stands for _________ [12M05] a. Hewlett-Packard Instrument Bus b. General Purpose Interface Bus c. Hewlett-packard isolation bus d. General Purpose isolation Bus Most computer systems have ____________ electronic timers [12S01] a. one to sixteen b. 5 to 8000 c. 10-90 d. 500-700 The ARM7TDMI core is a -----------------bit embedded RISC processor delivered as a hard macro cell optimized to provide the best combination of performance, power and area characteristics [12S02] a. 16 bit b. 32 bit c. 64 bit

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d. 118.

8 bit

ARM and Thumb instructions sets can be mixed with__________overhead to support application requirements for speed and code density [12S03] a. maximum b. minimum c. nill d. complex IEEE 488 bus stands for [13D01] a. Standard Digital Interface for Programmable Instrumentation b. Standard analog Interface for Programmable Instrumentation c. Standard Digital Interface for power Instrumentation d. Standard Digital illumination for Programmable Instrumentation IN IEEE 488 BUS, The three handshake lines (NRFD, NDAC, DAV)_________ the transfer of message bytes among the devices and form the method for acknowledging the transfer of data. [13D02] a. amplify b. control c. centralize d. nullify IEEE 488 Bus, following are used for Interface Management Lines. ( ATN, EOI, IFC,REN & SRQ). SRQ Stands for_______ [13D03] a. line is like an interrupt: it may be asserted by any device to request the Controller to take some action b. line is like an interrupt: it may be asserted by any device to request the Controller to not to take some action c. line is like an acknowledgement: it may be asserted by any device to generate signals d. line is like an status bus for allowing the input signals go through it The IEEE-488 connector has ______ pins. [13M01] a. 96 b. 14 c. 24 d. 100 IFC_________ all device interfaces and returns control to the System Controlle [13M02] a. clears b. stores c. change d. ampligy The 16 signal lines of IEEE 488 Bus are divided into 3 groups. Which is not in that group [13M03] a. 8 data lines b. 3 handshake lines c. 5 interface management lines. d. 8 interrupt lines The NRFD (Not Ready for Data) handshake line is asserted by a Listener to indicate it is____ for the next data or control byte [13M04] a. not yet ready b. ready c. not yet accepted d. Data Valid In a. b. c. d. IEEE 488 Bus, following are not the Interface Management Lines [13M05] ATN EOI IFC RCN

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The IEEE-488 interface system consists of 16 signal lines and_________ground lines [13S01] a. 08 b. 24 c. 34 d. 02

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The NDAC (Not Data Accepted) handshake line is asserted by a Listener to indicate it has_______ the data or control byte on the data lines [13S02] a. not yet ready b. ready c. not yet accepted d. data Valid ________ filters do not suffer with temperature and so are extremely stable with respect both to time and temperature [14D01] a. Analog filter b. digital filter c. neither of the above d. filter is not related to temperature The ARM7TDMI core is a_________bit embedded RISC processor delivered as a hard macro cell optimized to provide the best combination of performance, power and area characteristics [14D02] a. 16 bit b. 32 bit c. 64 bit d. 8 bit Filter can easily be changed without affecting the circuitry (hardware) [14M01] a. Analog filter b. digital filter c. neither of the above d. filter is not related to hardware An_______ filter can only be changed by redesigning the filter circuit [14M02] a. Analog filter b. digital filter c. neither of the above d. filter is not related to hardware ARM and Thumb instructions sets can be mixed with ____________overhead to support application requirements for speed and code density [14M03] a. maximum b. minimum c. nill d. complex Following is the operating system for ''Open Systems and their interfaces for the Electronics in Motor vehicles" is [14M04] a. VXworks b. ucLinux c. RTX51 d. OSEK/VDX An optical shaft encoder system for measuring electrically powered motor shaft_____________ [14S01] a. speed b. velocity c. width d. diameter The characteristics of___________circuits (particularly those containing active components) are subject to drift and are dependent on temperature. [14S02] a. Analog filter b. digital filter c. neither of the above d. filter is not related to temperature ARM7TDMI Features__________bit Thumb instruction set for increased code density [14S03] a. 16 bit b. 32 bit c. 64 bit d. 8 bit

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IEEE 488 Bus, following are used for Interface Management Lines. ( ATN, EOI, IFC,REN & SRQ). IFC stands for ____________ [15D01] a. End or identify b. Remote Enable c. Attention d. Interface Clear Following is the operating system for ''Open Systems and their interfaces for the Electronics in Motor vehicles'' is ________ [15D02] a. VXworks b. ucLinux c. RTX51 d. OSEK/VDX Digital timers can achieve higher precision than mechanical timers because they are_________with special electronics [15D03] a. quartz clocks b. analog clock c. digital clock d. both quartz clocks and analog clock _________ Filters are very much more versatile in their ability to process signals in a variety of ways; this includes the ability of some types of ________ filter to adapt to changes in the characteristics of the signal. [15D04] a. Analog filter b. digital filter c. neither of the above d. filter is not related to characteristics of the signal The ARM7TDMI core is a -----------------bit embedded RISC processor delivered as a hard macro cell optimized to provide the best combination of performance, power and area characteristics [15M01] a. 16 bit b. 32 bit c. 64 bit d. 8 bit Most computer systems have__________electronic timers [15M02] a. one to sixteen b. 5 to 8000 c. 10 - 90 d. 500-700 ucLinux is probably the best choice if your device has plenty of [15M03] a. flash and RAM memory b. internal and external memory c. cache and external memory d. EPROM and ROM Memory ARM7TDMI Features ________bit Thumb instruction set for increased code density [15S01] a. 16 bit b. 32 bit c. 64 bit d. 8 bit IEEE 488 Bus, following are used for Interface Management Lines. ( ATN, EOI, IFC,REN & SRQ). REN stands for __________ [15S02] a. Remote disable b. Remote Enable c. Radar Equipment d. Remote engine not used IEEE 488 Bus, following are used for Interface Management Lines. ( ATN, EOI, IFC,REN & SRQ). EOI stands for _________ [15S03] a. End or identify b. Remote Enable c. Attention d. Interface Clear

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SCADA is the abbreviation for ________ [16D01] a. Supervisory Control And Data Acquisition b. Supervisory chemical and dental aquarium c. Supervisory Control And Data attention d. Silicon Control And Data Acquisition In computing, ___________involves a multiprocessor computer-architecture where two or more identical processors can connect to a single shared main memory [16D02] a. symmetric multiprocessing or SMP b. unsystamatic multiprocessing c. multitasking d. scheduling Microcontrollers were originally programmed only in assembly language, but various high-level programming languages are now also in common use to target microcontrollers. These languages are either designed specially for the purpose, or versions of general purpose languages such as the __________ programming language [16D03] a. Java language b. C language c. core java d. VC++ The vast majority of robots use electric motors, including brushed and brushless __________motors [16D04] a. DC motor b. AC Motor c. ultra sonic motor d. piezo motor ARM and Thumb instructions sets can be mixed with ______overhead to support application requirements for speed and code density [16M01] a. maximum b. minimum c. nill d. complex (Such as Beowulf), in which not all memory is available to all processors [16M02] a. computer clustered multiprocessing b. unsystamatic cultiprocessing c. asymmetric multiprocessing d. single processor Is a set of techniques for the exchange of data among two or more threads in one or more processes. Processes may be running on one or more computers connected by a network [16M03] a. Inter-Process Communication (IPC) b. Intra Process communication c. asymmetric multi processing d. computer clustered multiprocessing. MIPS STANDS FOR _________ [16M04] a. Microprocessor without Interlocked Pipeline Stages b. Microprocessor with Interlocked Pipeline Stages c. MicroCONTROLLER without Interlocked Pipeline Stages d. Microprocessor without Inter Pipeline Stages A recent alternative to DC motors are piezo motors or ultrasonic motors. These work on a fundamentally different principle, whereby tiny piezoceramic elements, vibrating many thousands of times per second, cause_________ motion [16M05] a. linear b. rotary c. circular d. both linear and rotary ______ is defined as the temporal difference between the deadline, the ready time and the run time. [16S01] a. Slack time b. least slack time

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c. d. 158.

stability suitability

A device signals its request for service by sending a short message over some communications medium, typically a computer bus. [17D01] a. level-triggered interrupt b. Edge triggered interrupt c. Hybrid triggered interrupt d. Message signalled interrupt. Whereas a counts upwards from zero for measuring elapsed time, a timer counts down from a specified time interval, like a sand clock. [17M01] a. Timer b. Scheduler c. Stopwatch d. .Counter ARM s are Used especially in portable devices due to its________and reasonable performance [17M02] a. High power consumption b. low power consumption c. power consumption is not at all related. d. worst performance. ARM history is mainly developed to replace_______in BBC computers [17M03] a. 1206 b. 6502 c. 1273 d. 1125 A ________can be used to control the sequence of an event or process. [17S01] a. Timer b. Scheduler c. Stopwatch d. Counter In a. b. c. d. typical designs, a task has three states those are [17S02] running ready blocked. running, ready and blocked.

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ARM stands for_______ [17S03] a. advanced RISC machine b. advanced CISC Machine c. Advanced Resource Machine d. Advanced Reed Machine. ARM history developed by Acorn computers in________ [17S04] a. 1983 b. 1998 c. 1970 d. 1945 The hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time. [17S05] a. level-triggered interrupt b. Edge triggered interrupt c. Hybrid triggered interrupt d. Message signalled interrupt Systems must manage sharing data and hardware resources among multiple tasks [18D01] a. Multi tasking b. single tasking c. schedule tasking d. restore tasking Since an interrupt handler blocks the______task from running, and since real time operating systems are designed to keep thread latency to a minimum, interrupt handlers are typically kept

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as a. b. c. d. 169.

short as possible [18D02] highest priority lowest priority none of the priority zero priority

Memory allocation is even more______in an RTOS than in other operating systems [18D03] a. easy b. critical c. not related d. speed A__________(IRQ) is a hardware interrupt that may be ignored by setting a bit in an interrupt mask register's (IMR) bit-mask. [18D04] a. maskable interrupt b. non maskable interrupt c. interprocessor interrupt d. software interrupt In a. b. c. d. typical designs, a task has three states those are [18M01] running ready blocked. running ,ready and blocked.

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Problems with semaphore based designs are well known: [18M02] a. priority inversion b. deadlocks. c. priority inversion and deadlocks. d. multi tasking Protocol deadlocks occur when __________tasks wait for each other to send response messages [18M03] a. 0.5 b. two or more c. 1 d. no tasks The simple_______algorithm works astonishingly well for simple embedded systems [18M04] a. fixed-size-blocks b. variable size blocks c. zero size blocks d. random size blocks In_______, a high priority task waits because a low priority task has a semaphore [18S01] a. priority inversion b. dead lock c. multi tasking d. scheduling In a____________, two or more tasks lock a number of binary semaphores and then wait forever (no timeout) for other binary semaphores, creating a cyclic dependency graph. [18S02] a. priority inversion b. dead lock c. multi tasking d. scheduling ____________introduces the concepts and methodologies employed in designing a system-onchip based around a microprocessor core, and in designing the core itself. [19D01] a. ARM System-on-Chip Architecture b. 80196 MICRO CONTROLLER c. Prototype MCU based measuring instruments. d. Non masking interrupt sources. ARM history developed by Acorn computers in _________ [19D02] a. 1983 b. 1998 c. 1970

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d. 179.

1945

First-In-First-Out pipes (FIFOs) or shared memory can be used to_________between the operating system and the real-time core. [19M01] a. transfer data b. share data c. destroy data d. store data VxWorks is a real-time operating system made and sold by Wind River Systems of Alameda, _________ [19M02] a. California, USA. b. Japan c. Canada d. Australia PIC I/O and 8051 pin both can drive the following source directly [19S01] a. LASER b. LED c. PHOTO DIODE d. PIN DIODE The advantage of using a real-time replacement kernel such as_______is that there are no limits on size or complexity of the real-time application code [19S02] a. LynxOS b. VXworks c. RTOS of Keil d. RTX51 ARM has Fixed-length________bit instructions [20D01] a. 8 bit b. 16 bit c. 32 bit d. 64 bit ARM stands for_______ [20M01] a. advanced RISC machine b. advanced CISC Machine c. advanced Resource Machine d. advanced Reed Machine ARM9TDMI Compatible with_______ [20S01] a. ARM 7 b. ARM 14 c. ARM 25 d. ARM 45 ARM history is mainly developed to replace _______ in BBC computers [20S02] a. 1206 b. 6502 c. 1273 d. 1125

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