6.

012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-1

Lecture 9 - MOSFET (I)

MOSFET I-V Characteristics

October 6, 2005

Contents:

1. MOSFET: cross-section, layout, symbols

2. Qualitative operation
3. I-V characteristics

Reading assignment:

Howe and Sodini, Ch. 4, §§4.1-4.3

Announcements: Quiz 1: 10/13, 7:30-9:30 PM,

(lectures #1-9); open book; must have calculator.
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-2

Key questions

• How can carrier inversion be exploited to make a tran-

sistor?
• How does a MOSFET work?

• How does one construct a simple first-order model for

the current-voltage characteristics of a MOSFET?

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-3

1. MOSFET: layout, cross-section, symbols

polysilicon gate
body source drain
gate

n+

p+ n+ n+

inversion layer gate oxide

n
channel

gate length

gate width
p+ p n+ n+ n+

n+ STI edge

Key elements:
• inversion layer under gate (depending on gate voltage)

• heavily-doped regions reach underneath gate ⇒ in

-
version layer electrically connects source and drain

• 4-terminal device: body voltage important

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-4

Image removed due to copyright restrictions.

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-5

2 Circuit symbols

Two complementary devices:

• n-channel device (n-MOSFET) on p-Si substrate

(uses electron inversion layer)

• p-channel device (p-MOSFET) on n-Si substrate

(uses hole inversion layer)

D IDn D
IDn S
+ + S
+
VDS > 0 VSG
VSB
G G _ _
B B
+ + G B G B
VGS VBS VSD > 0
_ _

S−
S −IDp D− −IDp D

(a) n-channel MOSFET (b) p-channel MOSFET

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-6

2. Qualitative operation

Water analogy of MOSFET:

• Source: water reservoir
• Drain: water reservoir
• Gate: gate between source and drain reservoirs

VDS

VGS

ID

S n+ D
VGS
n+ n+ water
VDS
inversion
depletion
layer
region

B
source gate drain

Want to understand MOSFET operation as a function of:

• gate-to-source voltage (gate height over source water

level)
• drain-to-source voltage (water level difference between
reservoirs)

Initially consider source tied up to body (substrate or

back).
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-7

Three regimes of operation:

2 Cut-off regime:
regime:

• MOSFET: VGS < VT , VGD < VT with VDS > 0.

• Water analogy: gate closed; no water can flow regardless

of relative height of source and drain reservoirs.

VGS<VT VGD<VT
G

S n+ D

n+ n+
no inversion
layer
anywhere depletion
region
p

no water flow

ID = 0
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-8

2 Linear or Triode regime:

• MOSFET: VGS > VT , VGD > VT , with VDS > 0.

• Water analogy: gate open but small difference in height

between source and drain; water flows.

VGS>VT VGD>VT
G

S n+ D

n+ n+
inversion layer
everywhere
depletion
region
p

Electrons drift from source to drain ⇒ electrical current!

• VGS ↑ → |Qn| ↑ → ID ↑

• VDS ↑ → |Ey | ↑ → ID ↑
ID ID
small VDS small VDS

VGS>VT
VDS

0 0
0 VDS VT VGS
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-9

2 Satura
Saturation regime:

• MOSFET: VGS > VT , VGD < VT (VDS > 0).

• Water analogy: gate open; water flows from source to

drain, but free-drop on drain side ⇒ total flow indepen-
dent of relative reservoir height!

VGS>VT VGD<VT
G

S n+ D

n+ n+

inversion layer
depletion "pinched-off"
region at drain side
p

ID independent of VDS : ID = IDsat

VGDsat=VT
ID

saturation
linear

0
0 VDSsat=VGS-VT VDS
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-10

3. I-V characteristics

Geometry of problem:
y
0 L
VDS

VGS
ID
G
IS

-tox
S n+ D
0

n+ n+
xj inversion
depletion
VBS=0 layer
region

2 General expression of channel current

Current can only flow in y-direction:

Iy = W Qn(y)vy (y)

Drain terminal current is equal to minus channel current:

ID = −W Qn(y)vy (y)
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-11

ID = −W Qn(y)vy (y)

Rewrite in terms of voltage at channel location y, Vc(y):

• If electric field is not too big:

dVc (y)
vy (y)  −µnEy (y) = µn
dy

• For Qn(y ) use charge-control relation at location y:

Qn(y) = −Cox [VGS − Vc(y) − VT ]

for VGS − Vc(y) ≥ VT .

All together:

dVc(y)
ID = W µnCox (VGS − Vc (y) − VT )
dy

Simple linear first-order differential equation with one un-

known, the channel voltage Vc(y).
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-12

Solve by separating variables:

ID dy = W µnCox (VGS − Vc − VT )dVc

Integrate along the channel in the linear regime:

-for y = 0, Vc(0) = 0

-for y = L, Vc(L) = VDS (linear regime)

Then:
� �
L VDS
ID 0 dy = W µnCox 0 (VGS − Vc − VT )dVc

or:

W VDS
ID = µnCox (VGS − − VT )VDS
L 2

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-13

For small VDS :

W
ID  µnCox (VGS − VT )VDS
L

Key dependencies:

• VDS ↑ → ID ↑ (higher lateral electric field)

• VGS ↑→ ID ↑ (higher electron concentration)
• L ↑ → ID ↓ (lower lateral electric field)
• W ↑ → ID ↑ (wider conduction channel)

ID ID
small VDS small VDS

VGS>VT
VDS

0 0
0 VDS VT VGS

This is the linear or triode regime.

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-14

In general,

W VDS
ID = µnCox (VGS − − VT )VDS
L 2

Equation valid if VGS − Vc(y) ≥ VT at every y.

Worst point is y = L, where Vc (y) = VDS , hence, equa-

tion valid if VGS − VDS ≥ VT , or:

VDS ≤ VGS − VT

ID VDS=VGS-VT

VGS

VGS=VT
0
0 VDS

term responsible for bend over of ID : − VDS

2
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-15

To understand why ID bends over, must understand first

channel debiasing
debiasing::
|Qn(y)|
VDS=0
Cox(VGS-VT)

VDS>0
0
0 L y

|Ey(y)|

VDS>0

VDS=0
0
0 L y
Vc(y)

VDS
VDS>0

VDS=0
0
0 L y
VGS-Vc(y)
VDS=0
VGS
VDS
local gate
overdrive VDS>0
VT
0 L y

Along channel from source to drain:

y ↑ → Vc(y) ↑ → |Qn(y)| ↓ → |Ey (y)| ↑

Local ”channel overdrive” reduced closer to drain.

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-16

Impact of VDS :

|Qn(y)|
VDS=0
Cox(VGS-VT)

VDS
0
0 L y
|Ey(y)|

VDS

VDS=0
0
0 L y
Vc(y)

VDS

VDS
VDS=0
0
0 L y
VGS-Vc(y)
VDS VDS=0
VGS
VDS
local gate
overdrive
VT
0 L y

As VDS ↑, channel debiasing more prominent

⇒ ID rises more slowly with VDS
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-17

3µm n-channel MOSFET

Output characteristicss ((VGS = 0 − 4 V, ∆VGS = 0.5 V ):

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-18

Zoom close to origin (VGS = 0 − 2 V, ∆VGS = 0.25 V ):

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-19

Transfer characteristics (VDS = 0 − 100 mV, ∆VDS =

20 mV ):
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 9-20

Key conclusions

• The MOSFET is a field-effect transistor:

– the amount of charge in the inversion layer is con-

trolled by the field-effect action of the gate
– the charge in the inversion layer is mobile ⇒ con-
duction possible between source and drain
• In the linear regime:
– VGS ↑⇒ ID ↑: more electrons in the channel
– VDS ↑⇒ ID ↑: stronger field pulling electrons out
of the source
• Channel debiasing: inversion layer ”thins down” from
source to drain ⇒ current saturation as VDS approaches:

VDSsat = VGS − VT