Digital Implementation of a DC Bus Voltage Controller for

Four-Wire Active Filters

V. Soares* P. Verdelho**
* **
ISEL – Instituto Superior de Engenharia de Lisboa IST – Instituto Superior Técnico
* *,**
DEEA – Departamento de Engenharia CAUTL – Centro de Automática da Universidade
Electrotécnica e Automação; Técnica de Lisboa
* **
CIC – Centro de Instrumentação e Controlo ERSE – Entidade Reguladora dos Serviços Energéticos
Lisboa, PORTUGAL Lisboa, PORTUGAL
Email: vesoares@deea.isel.ipl.pt Email: pcverdelho@alfa.ist.utl.pt

Abstract — This paper presents the digital implementation of

a dc bus voltage controller for three-phase four-wire active II. SYSTEM MODELLING
filters. Active filters can only operate if a control system is used
to regulate the dc side voltages of its power converter. Using a The voltage regulation control system based on a
split dc link capacitor converter topology the control system three-phase four-wire VSC is shown in Fig. 1. The power
purpose enables the total dc voltage regulation and voltage converter is a three-leg VSC with the neutral wire connected
sharing across capacitors. System modelling and controllers to the middle-point of the dc bus, Fig. 2.
syntheses are realized and presented in the paper.
Experimental results are shown enabling to highlight the AC mains
behaviour and robustness of the digital control system
proposed.
ic123 L icN
I. INTRODUCTION
Voltage regulation systems play an important role in all ic123
iload
self-powered systems connected to the ac mains, like active
filters (AF’s), unified power flow controllers (UPFC’s), 3-leg edc
VSC
advanced static VAr compensators (ASVC’s), PWM ic123
C edc1 +
edc2 +
rectifiers, uninterruptible power supplies (UPS’s) and C
+
neutral current compensators (NCC’s). In some of these - εedc
applications the voltage regulation is not the primary goal. g123

However, voltage regulation is absolutely necessary to the

δic123
operation of the voltage source converters (VSC’s) in order 123
-
to sink or feed current into mains. θ + ic123 r
When neutral current control is desirable, especially in
θ 123
active filtering with zero sequence current component dq0
compensation, three-phase four-wire converters are needed.
They can be realized either with a three-leg VSC with split icd r icq r ic0 r - DC voltage
dc link capacitor, as in the present study, or with a four-leg +
i0 bal unbalance regulator
VSC. When dealing with neutral current a special care id 1h+ DC voltage δedc
should be taken into account in order to assure an equal +
+ regulator
+
-
voltage sharing between capacitors. Also, the ripple voltage
id iq i0 edc r
must be considered so that the rated capacitor voltages are
not exceeded. These problems are due to neutral current Fig. 1. Voltage regulation control system based on the three-phase four-wire
caused by unbalance or current harmonics. VSC with split dc link capacitor.
Some works have been realized in the design of voltage
controllers for these converters using linear [1]-[4] and The phase inductors placed between the mains supply and
sliding-mode control techniques [5]. The works realized in the VSC are described by the variables R and L. For the
[1]-[3] are based on linear models and analog control, neutral connection is also considered its resistance RN and
however digital implementation issues need to be presented inductance LN. The presence of an additional inductance LN
and discussed. In this paper a digital control system that is useful to decrease the switching frequency and smooth the
performs the voltage regulation on a AF, based upon a neutral current.
three-leg VSC with split dc link capacitor is presented. Voltages on the VSC ac side are described by (1).
Experimental results in a DSP platform are presented to Variables gi, where i = {1,2,3} stands for phase number, are
highlight the system characteristics with respect to dynamic the switching functions. A value gi = 0/1 means that the
and steady-state behaviour. lower/upper IGBT is conducting. Obviously, in any leg, the
IGBT’s conduction is nonsimultaneous.
1-4244-0136-4/06/$20.00 '2006 IEEE 2763
 idc1 iload
⎡ 3 − 1 − 1⎤
1 ⎢
− 1 3 − 1⎥⎥
+ −1
L = (5b)
4L ⎢
T11 T21 T31 123
⎢⎣− 1 − 1 3 ⎥⎦
edc1
L ic1 D11 D21 D31 C1
u1
L ic2 ⎡− R / L 0 0 ⎤
u2
L ic3 edc −L −1
R 123 ⎢
=⎢ 0 − R/L 0 ⎥⎥ (5c)
123
u3
LN icN ⎢⎣ 0 0 − R / L ⎥⎦
uN
e1 e2 e3 C2
T21 T22 T32 edc2 The state equations for the capacitors voltages are,
D12 D22 D32 ⎧ d edc1 1 1
-
⎪⎪e&dc1 = = idc1 − iload
Leg 1 Leg 2 Leg 3 dt C C . (6)
idc2 ⎨ d e
⎪e& = dc 1 1 3
Fig. 2. Three-phase four-wire topology based on the three-leg VSC with
2
= − i − i = e
& − i
⎩⎪ 2
dc dc load dc1 c
split dc link capacitor. dt C 2 C C 0
A detailed system modelling with linear control [4] and
ei = g i edc1 + ( g i − 1) edc 2 , g i = {0, 1} (1) system modelling with sliding-mode control [5] was already
discussed.
In a matrix form these voltages can be expressed by, The global system dynamics of the connection
mains-VSC is established by the state equations in
e123 = g 123 edc1 + (g 123 − 1 (3×1) ) edc 2 . (2) vector-matrix form by (7) or alternatively by (8) where he
variables fdq0 are auxiliary switching functions.
The variable iload is a load current on the dc side of the
VSC. Fig. 3 shows the dc side currents and its relationships ⎡ g 1 − g1 ⎤
⎢ − 1
L ⎥⎥
with the ac side currents. All currents derived are expressed
⎡ ic1 ⎤ ⎢
& L
by (3) and (4). g2 1 − g2
⎢& ⎥ ⎢ −1
− L 123 ⋅ R 123 − ⎥
idc1 iload ⎢ i c2 ⎥ ⎢ L L ⎥
⎢ i&c ⎥ = ⎢ g 1 − g3 ⎥ ⋅
⎢ 3 ⎥ ⎢ − 3
L ⎥⎥
iC1
e&
⎢ dc1 ⎥ ⎢ L
idc1 C edc1
⎢e& ⎥ ⎢ g 1 / C g2 / C g3 / C 0 0 ⎥
icN ⎣ dc 2 ⎦ ⎢ g 1 − 1 g2 −1 g3 − 1
0 0 ⎥ (7)
iC2 ⎣⎢ C C C ⎦⎥
idc2 C edc2 ⎡ i c1 ⎤ ⎡ 0 ⎤
⎢i ⎥ ⎢ ⎡ u1 ⎤
⎢ c2 ⎥ ⎢ L 123
−1
0 ⎥⎥ ⎢
u 2 ⎥⎥
⋅ ⎢ i c3 ⎥ + ⎢ 0 ⎥⋅⎢
idc2 iload ⎢ ⎥ ⎢ ⎥ ⎢ u3 ⎥
⎢ edc1 ⎥ ⎢0 0 0 − 1/ C⎥ ⎢ ⎥
i
⎥ ⎣ load ⎦
Fig. 3. Dc side currents in the three-leg VSC with split dc link capacitor.
⎢edc ⎥ ⎢0 0 0 − 1 / C
⎣ 2⎦ ⎣ ⎦

⎧⎪idc1 = g123
T
i c123
⎨ (3) ⎡ R f ⎤
⎪⎩idc 2 = (1(1×3) − g123 ) i c123 = −ic N − idc1
T
⎢− L θ& 0 − d ⎥
L
⎡ i&cd ⎤ ⎢ R f q ⎥ ⎡ i cd ⎤
⎢ & ⎥ ⎢ − θ& − 0 − ⎥ ⎢ ⎥
⎧iC1 = i dc1 − i load ⎧i c1 + i c2 + ic3 + i c N = 0 ⎢ i cq ⎥ = ⎢ L L ⎥ ⎢ i cq ⎥
⎨ ⎨ (4) ⎢ i&c ⎥ ⎢ R + 3 RN f 0 ⎥ ⋅ ⎢i ⎥ +
⎩iC 2 = −i dc 2 − i load = i C1 + i c N ⎩i dc1 + i dc 2 + ic N = 0 ⎢ 0⎥ ⎢ 0 0 −
L + 3 L
−
L + 3 L
⎥ ⎢ c0 ⎥
⎣⎢edc ⎦⎥
& ⎢ N N ⎥ ⎣edc ⎦
For low/medium power VSC’s it is assumed that neutral ⎢ fd fq f0 ⎥ (8)
⎢ 0 ⎥
wire presents the same parameters as phase wires so R = RN ⎣C / 2 C / 2 C/2 ⎦
and L = LN. The system dynamics of the connection
⎡1 / L 0 0 0 ⎤ ⎡ ud ⎤
mains-VSC is established by the state equations in ⎢ 0 1/ L ⎥ ⎢u ⎥
vector-matrix form (5). 0 0 ⎥⋅⎢ q ⎥
+⎢
⎢ 0 0 1 /( L + 3 L N ) 0 ⎥ ⎢ u0 ⎥
&i −1 −1 −1
⎥ ⎢ ⎥
c123 = ( −L 123 R 123 ) i c123 + L 123 u 123 − L 123 e 123 (5a) ⎢
⎣ 0 0 0 − 1 /(C / 2)⎦ ⎣iload ⎦

2764
 III. SYSTEM CONTROL regulation system closed-loop. Its presence is useful for
reducing the voltage overshoot under non-constant dc
The generic voltage regulation control system was already
voltage operation (e.g. power supplies based on PWM
shown in Fig. 1. Currents ic123r are obtained from icdq0r by a
rectifiers) and to smooth the reference changes preventing
Park’s transformation presented in [6], [7]. They derive
high current seek during transients. Moreover, is necessary
from the input currents idq0 and also from the dc voltage
for a proper startup of the VSC in special if the majority of
regulation systems.
circuits (power and/or control) are not energized.
Current control is accomplished by three two-level
The dc voltage controller is sintetized assuming a unitary
comparators (delta-modulation technique) operating in phase
TF for the current control system (Gc(s) = 1), without
coordinates.
disturbances, inclusively the absence of a load at the
Fig. 4 shows the block diagram of the voltage regulation
capacitors. Considering the variables kP1 and kI1 as the
systems for edc and voltage unbalance εedc. Direct (active),
proportional and integral gains of the PI controller C1(s),
quadrature (reactive) and zero sequence current components
are controlled by the input values idq0, depending on the k I1
currents harmonics of the AF. C1 ( s ) = k P1 + , (9)
s
A proportional-integral (PI) controller C1(s) performs the
voltage regulation in the VSC dc side. Its input is the the voltage regulation closed-loop TF for ∆Iload =0 is
capacitor voltage error δedc = (edcr - edc). Through the derived (10).
regulation of the first harmonic active current of positive
sequence icd 1h+ it is possible to control the active power flow k P1 udo ⎛ k ⎞
⎜ s + I1 ⎟
o ⎜
in the VSC and thus the total capacitor voltage edc. It’s ∆Edc C / 2 edc ⎝ k P1 ⎟⎠
worthwhile to note that the PI controller will feed not only ( s) = F ( s) ⋅ (10)
∆Edcr udo ⎛⎜ icd
o
⎞ k I1 udo
VSC dc load but also handles the power dissipated in the s2 + + k ⎟ s +
o ⎜ o P1
⎟ o
inductances and losses in the switching devices. C / 2 edc ⎝ edc ⎠ C / 2 edc
For voltage unbalance regulation purposes a proportional
(P) or a PI controller C2(s) can be used. This controller A first-order LP filter F(s) with a cutoff frequency
generates a balancing zero sequence current component i0 bal. ωcF = kI1/kP1 is used, therefore,
A positive error εedc = (edc1 - edc2) decreases the reference
k I1 / k P1 ω cF
current ic0r and, by means of neutral current icN, equal F (s) = = . (11)
voltage sharing between the capacitors is accomplished. s + k I1 / k P1 s + ω cF
edc
edc1 Considering a null active power flow in the converter, i.e.,
+
edc2
+
C1(s) icdo = 0, the PI gains are finally obtained (12).
-
+ δedc id 1h+
edc r F(s) o o
C edc C edc
- k P1 = o
ζ ω n1 , k I1 = ω 2n1 (12)
+ εedc
C2(s)
i0 bal u d 2 u do
+
+
id icd r
The parameters considered in the controller synthesis for a
iq
-
icq r prototype second-order TF, as the one formed by (10) and
i0
+
ic0 r (11) are: a damping ratio ζ = √2/2= 0.707 (Butterworth or
Fig. 4. Block diagram of the voltage regulation systems and reference
ITAE criteria for second-order systems), a natural undamped
current generation. frequency ωn1 = ω/5 = 62.83 rad/s (ω = 2πf, f = 50 Hz;
fn1 = 10 Hz), a capacitor C = 4 mF, a dc voltage
The linearized model of the total voltage regulation edco = edcr = 200 V and a mains voltage Urms = 50 V.
system is presented in Fig. 5. Under balanced and sinusoidal voltage conditions the
relation between the voltage space vector and the mains
∆Iload 1 voltage leads to ud = √(3/2) Û123 or ud = √3 Urms with uq = 0
C/2
[4]-[8].
∆Id r ∆Icd -
ud° + 1 The resulting proportional and integral gains are
∆Edc r F(s) C1(s) Gc(s) ud° icd° ∆Edc
+- C/2 edc° s+
C/2 edc° ² kP = 0.4104 and kI = 18.23. A PI controller with anti-windup
VSC is used to limit the integral action. It imposes a phase peak
Fig. 5. Block diagram of the total voltage regulation system.
value of 10 A (îc123 = 10 A; -12.2 A ≤ icdo ≤ 12.2 A). The
filter F(s) has an equivalent cutoff frequency ωcF = kI1/kP1
Transfer functions (TF’s) C1(s) and Gc(s) are related with (fcF = 7.1 Hz). In the VSC and current controller it is
the PI controller and the current control system, respectively. considered: L = LN= 2.15 mH and R = RN = 0.1 Ω.
A first order low-pass (LP) filter F(s) is used to eliminate the For a digital implementation in a DSP platform discrete
influence of the zero introduced by the PI controller in the TF’s should be obtained. The sampled version of the
forward-path TF, and consequently in the dc voltage continuous model presented in Fig. 5 will give the analog

2765
system digitally controlled of Fig. 6. The sample period (or For the voltage unbalance regulation purposes a model
sample time) is expressed by Ts (fs = 1/Ts, ωs = 2πfs). The must be obtained. By (6) the voltage unbalance TF derived
value used in the prototype was Ts = 35 µs which gives a is simply,
sampling frequency fs = 28.6 kHz.
εE dc 3
(s) = . (17)
∆Iload 1 I c0 Cs
C/2
∆Icd r
δ∆edc(nT s) ∆id(nTs) ∆Id* ∆Icd h ∆Icd
∆Edc r
+
- 1 Fig. 7 shows the block diagram of the voltage unbalance
∆Edc
ud°
Ts
C1(z)
Ts
Gh(s) Gc(s)
C/2 edc ° s+ regulation
ud° icd° system where C2(s) and Gc(s) are the TF’s of a
+- ∆id(t) C/2 edc° ²
A/D D/A VSC linear controller and the current control system, respectively.
t = nTs

The regulation of the dc voltage unbalance may be

Fig. 6. Block diagram of the sampled voltage regulation system.
With values of sampling frequency at least 20 times
greater that the system bandwidth, as in the present case
(BW = fn1 = 10 Hz), the difference between an analog and
digital control system is neglectable. So, the analog system
digitally controlled behaves like it was controlled by a linear
controller [9], [10]. The discrete version of the TF C1(s) (13)
is obtained using the Bilinear transformation. A very good
approximation between continuous and discrete data systems
accomplished using P or PI controllers. A detailed study is
shown in [4].
For a P controller the closed-loop TF (18) has a LP filter
behaviour (with Gc(s) ≈ 1). Open-loop TF presents a zero in
the forward-path (type 1 system) therefore a P controller
enables to obtain a null voltage error in εEdc under
steady-state conditions. Also, a null error is obtained as
system is regulated to zero, εEdcr = 0.
I0

is achieved with this transformation technique. +

+
Ic0 r Ic0
C2(s) Gc(s) 3
εEdc r = 0 εEdc
−1 Cs
T z + 1 a 0 + a1 z +
I0 bal
C1 ( z ) = k P1 + k I1 s ⋅ =
-
(13a)
2 z − 1 1 + b1 z −1
Fig. 7. Block diagram of the voltage unbalance regulation system.

a 0 = (k P1 + k I1 Ts / 2) , a1 = (k I1 Ts / 2 − k P1 ) , b1 = −1 (13b)
εE dc ω cε ω cε C
Similar procedures are taken with respect to the filter F(s). (s) = , k P2 = (18)
Considering the normalized filter cutoff frequency, εE dc r s + ω cε 3

ω cF = ω cF / ω s , (14) The advisable value for the cutoff frequency ωcε is related
n
with the sensibility of the voltage unbalance εEdc with
then, respect to I0. It should be as small as possible for the
frequency operating range. A good zero sequence current
a 0 + a1 z −1
F ( z) = , (15a) control is desirable, which is good as close to unit is the ratio
1 + b1 z −1 | Ic0 / I0 | regarding also its phase characteristic. As frequency
increase more close to unit is the ratio | Ic0 / I0 |. Zero
ω cF π ω cF π − 1 sequence current control exhibits high errors in the low
a0 = n
, a1 = a0 , b1 = n
. (15b) frequency range. By the point of view of current control
ω cF π + 1 ω cF π + 1 under normal operation, the worst situation is verified when
n n
a first harmonic zero sequence current is desired. Therefore,
Digital implementations of the PI controller and the a cutoff frequency is imposed to ωcε = ω/10 (fcε = 5 Hz;
reference filter are based on the coefficients (13b) and (15b),
magnitude response, 0.995 ≈ 0 dB; phase response, 5.711°)
respectively. They are applied to the difference equation
and a proportional gain is obtained, kP2 = 0.07255.
(16) derived from either (13a) or (15a).
y (n Ts ) = a0 x(n Ts ) + a1 x[(n − 1)Ts ] − b1 y[(n − 1)Ts ] (16) IV. EXPERIMENTAL PROTOTYPE

With respect to voltage sharing some issues must be
pointed out [4], [5]. Neutral current control in the VSC is
responsible for voltage unbalance in special for low
frequency components. Voltage unbalance may also be due
to current imbalance, which produce dc components, or even
to unequal capacitor values. Even small differences in these
parameters will produce unequal voltage sharing along time
because capacitors act as integrators.
An experimental prototype was built with a 2 kVA
three-leg IGBT VSC, Fig. 8(a). Hall-effect current and
voltage sensors and simple digital and analog interface
circuits were used, Fig 8(b). The ac current control and dc
voltage regulation were performed by a DSP system
(ADwin-Gold). This stand-alone and compact model is well
suited for prototyping and it is equipped with the IEEE
32 bit floating point 40 MHz Super Harvard Architecture
(SHARC) DSP ADSP 21062 from Analog Devices, Fig. 9.
It presents a single-cycle instruction execution with 25 ns
instruction rate. The performance values are 40 Millions of

2766
Instructions per Second (MIPS), 120 Millions of Floating
Point Operations per Second (MFLOPS) of peak
performance and 80 MFLOPS of sustained performance.
(a)
(b)
Fig. 8. (a) The 2 kVA three-leg IGBT VSC prototype. (b) Analog-digital
interface circuits between DSP system and the VSC.
Fig. 9. DSP internal structure used in the experimental prototype.
The DSP as an internal Static Random Access Memory
(SRAM) of 256 kB (25 ns). The external Dynamic Random
Access Memory (DRAM) is 4 MB (125 ns). Both memories
can be used for program and data. In the experimental
prototype it is required the fastest possible program
execution so the SRAM is the mainly used memory. This
processing system it is programmable by a dedicated
interface and runs in real-time independent of the computer
and its workload.
There is a selectable group of 2 Analog-to-Digital
converters (ADC’s) with 16 bipolar multiplexed analog
inputs (12 bit resolution with 0.8 µs conversion time plus
1 µs multiplexer settling time, or 16 bit resolution and 10 µs
conversion time plus 4 µs multiplexer settling time). For
2767
faster operation 12 bit ADC were used. With respect to
digital data there are 16 bit TTL inputs/outputs.
The analog inputs in the prototype were: currents ic123,
(iload); voltages u12, u23, edc1 and edc2. Digital outputs was
used for switching signals and IGBT enabling signals g123
and E123, respectively, in order to control the three-leg VSC.
As stated before, the global DSP execution time, which
corresponds to the sampling time related to all analog inputs
and digital outputs was 35 µs (sampling frequency of
28.6 kHz).
V. EXPERIMENTAL RESULTS
With the digital control system the experimental VSC
transient and steady-state responses are presented in
Figs. 10-13.
All the results were taken applying a -10 A to +10 A
reactive input current step change iq, a first harmonic current
of zero sequence i0 with a current peak value of 10/√3 A,
and a 2.5 A load current step iload. The load current was
created by a resistive load (Rload = 80 Ω) applied on the dc
side of the VSC. A voltage reference step change edcr of
20 V was also created in and experimental results. Balanced
sinusoidal voltage conditions were considered.
Mains voltage, phase currents (and neutral current) and dc
bus voltages are presented in all figures.
Fig. 10. Reactive input current step change iq from -10 A to +10 A.
(1) Mains voltage u1 (100 V/div). (2) Converter current ic1 (10 A/div).
(3) Converter current ic2 (10 A/div). (4) Dc bus
voltage edc = edc1 + edc2 (160 V/div).
Fig. 11. First harmonic zero sequence current i0 with a peak value of
10/√3 A. (1) Mains voltage u1 (100 V/div). (2) Converter
current ic1 (10 A/div). (3) Converter current icN (10 A/div).
(4) Dc bus voltage edc = edc1 + edc2 (160 V/div).
 As expected dc bus voltages are insensible to reactive and
zero sequence current components since there is no active
power associated with it, Figs. 10 and 11.
Load current is transformed into an active current by
means of the voltage regulation system, Fig. 12. The absence
of a voltage error relatively to a large disturbance (iload) is
due to the introduction of a pole in the system forward-path
TF by the PI controller C1(s). Observing Fig. 13 it is clear
that the steady-state error obtained is also null.
Fig. 12. Load current step iload of 2.5 A. (1) Mains voltage u1 (100 V/div).
(2) Converter current ic1 (10 A/div). (3) Converter current ic2 (10 A/div).
(4) Dc bus voltage error δedc = edcr - edc (40 V/div).
Fig. 13. Voltage reference step change edcr of 20 V. (1) Mains
voltage u1 (100 V/div). (2) Converter current ic1 (10 A/div).
(3) Converter current ic2 (10 A/div). (4) Dc bus voltage
change edc = edc - edc initial (40 V/div).
All the experimental results presented shows that a
constant dc voltage operation and system robustness is
verified with the digital controller operating over the
three-leg VSC with split dc link capacitor.
VI. CONCLUSIONS
In this paper a digital implementation of a dc bus voltage
controller for a four-wire AF was presented. The AF was
implemented with a three-leg VSC with split dc link
capacitor.
The complete VSC dc side model presented enables to
obtain the total voltage and unbalanced regulation systems.
The voltage unbalance is accomplished controlling the zero
sequence current components and thus enabling to share the
voltage across the capacitors in an efficient way. Also, with
2768
the models presented, it is possible to predict voltage
oscillations in the VSC dc side.
With respect to voltage regulation, experimental results
proved that digital implementations of the linear controllers
were successful and a stable and steady-state error free
system was obtained in the operation of the VSC connected
to the ac mains.
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