Numerical Optimization of an Active Voltage

Controller for Series IGBTs

A.T. Bryant and Y. Wang S.J. Finney and T.C. Lim P.R. Palmer
Department of Engineering School of Engineering and Physical Department of Electrical and Computer
Cambridge University Sciences Engineering
Trumpington Street Heriot-Watt University University of British Columbia
Cambridge, UK CB2 1PZ Edinburgh, UK EH14 4AS 2356 Main Mall
a.t.bryant.97@cantab.net S.J.Finney@hw.ac.uk Vancouver, BC, Canada V6T 1Z4
yw220@cam.ac.uk prp@ece.ubc.ca

Abstract—Feedback control of IGBTs in the active region can FWD

IL
be used to regulate the device switching trajectory. This
facilitates series connection of devices without the use of external CS L0 VAK
snubber networks. Control must be achieved across the full
active region of the IGBT and must balance a number of RS R0 LD
conflicting system goals including diode recovery. To date, the
choice of control parameters has been a largely empirical VDC
process. This paper uses accurate device models and formalised
optimization procedures to evaluate IGBT active voltage AFB LS
controllers. A detailed optimization for the control of IGBT turn- 1+s/ωFB
on is presented in this paper.
IC
I. INTRODUCTION + AOP
LG RG

A
CTIVE voltage control (AVC) has been shown to
provide an effective solution to the series connection of
IGBTs. A high speed feedback loop is used to force the
collector-emitter voltage to follow a pre-defined reference. By
this means voltage sharing and dv/dt control are achieved
without the need for bulky snubber networks [1-3].
Investigations have shown that a complex series of trade-
offs are implicit in the design of the IGBT controller [4].
Increased feedback loop gain and reduced gate resistance
improve reference tracking but can result in oscillations and
loss of voltage sharing. Diode power loss and over-voltage
associated with IGBT turn-on can be reduced by slowing the
switching reference, at the cost of increased IGBT switching
losses. This last issue is particularly important for bridge leg
applications where complementary IGBT voltage sharing must
be maintained [5].
Design of AVC by means of small signal models and
control theory is limited by the fact that linearised IGBT
parameters are strongly operating point dependent. In this
paper these issues are addressed through the use of an
optimization approach that uses full non-linear models and
balances the conflicting system requirements.
II. CIRCUIT AND CONTROLLER MODELLING
A chopper cell was modelled in order to evaluate the AVC
performance, shown in fig. 1. The IGBT and diode models
are based on those developed using a Fourier-series-based
solution of the ambipolar diffusion equation (ADE) [6,7].
These compact, physics-based models offer an accurate
solution of the device physics. They have been developed for
use in both PSpice and MATLAB/Simulink.
- VCE
VREF/AFB 1+s/ωOP
IGBT
LE
Fig. 1. Chopper cell circuit used in simulation, showing the AVC control
model.
A. Device Models
In this work the optimization algorithm runs within
MATLAB, hence the Simulink models were used [7]. A
simplified block diagram of the IGBT model is shown in fig.
2.
The carrier storage region (CSR) is the heart of the non-
linear model. Its carrier dynamics are governed by the
ambipolar diffusion equation (ADE) describing the behaviour
of the excess carrier density p(x,t):
∂ 2 p ( x, t ) p ( x, t ) ∂p ( x, t )
D = + (1)
∂x 2 τ ∂t
In the Fourier-based solution the excess carrier density is
expressed as a Fourier series in space, which transforms the
ADE into a set of ODEs [6]. The boundary conditions of the
CSR – necessary to solve the ADE – are defined by other
aspects of the device behaviour, for example the collector
current IC, the depletion layer width, the MOSFET current and
the P+ emitter recombination current. In turn, these depend on
the boundary values solved using the Fourier series, which are
also used to determine the collector-emitter voltage VCE.
The device models used in this paper were based on a
1700V/400A NPT IGBT/diode pair, previously parameterized
using methods described in [8,9].

0-7803-9033-4/05/$20.00 ©2005 IEEE. 2060

 2
Ic III. OPTIMIZATION OF AVC PERFORMANCE
Saturation Vpn

f(u) f(u) The AVC gate drive is optimized using a formal numerical
PN jnc e- injection
pv ect optimization algorithm [7,9]. This finds the optimum design
Currents
px1
Saturation1 Ic W
Ic

W
Vbase 1
Vce by varying system parameters (e.g. component values,
pv ect
X2
px2 -K- Vd2 Wd2 Drift region resistance controller gains or reference waveform characteristics) and
Carrier storage region
Feedback
gain
Depletion
layer width evaluating the system performance. In addition to the
optimization algorithm, a suitable function must be found to
Vds
quantify the performance of the system to allow the evaluation
Id
Vgs to proceed automatically. Since the evaluation relies on
simulation of the system, this function must process the
MOSFET

f(u) s
1e-9s+1
simulation results to obtain the performance metric.
Displacement current
Miller cap
dVde/dt
Vmos

Vge
Cdg Cdg
Vge
Vge
2
A. Optimization Algorithm
dVde/dt
Optimization techniques rely on finding the minimum of an
Igc
4
Ig
Ig

Gate: Miller cap

objective function. This is specific to a particular problem,
and Cge Kelvin emitter
inductance and must be a function of the system parameters. The
3
dIg/dt
Le
optimum set of parameter values will give the minimum
1
dIc/dt
objective function (e.g. finding the minimum power
dissipation by varying circuit parameters).
Fig. 2. Simulink IGBT model, with labels showing the functions of the
various blocks.
Locating a minimum relies on the method of steepest
descent. For analytic objective functions, the gradient can be
B. AVC Model calculated at any point, so methods for such problems usually
The active voltage controller works by comparing the rely on evaluating a Hessian matrix. Here, the objective
collector voltage VCE with a reference voltage VREF to control function is not an analytic function of the parameters, as is the
it during switching. VREF is generated within the AVC gate case here, and direct search algorithms must be used [10,11].
drive, and has specific characteristics tailored for switching Therefore the objective function must be evaluated at points
IGBTs in series [1-5]. The form of VREF is shown in fig. 3. surrounding the current position in the parameter space. In
The turn-off phase is characterised by an initial pre- optimization of the AVC gate drive, the possible objectives
conditioning step, necessary to allow the inevitably include minimum device power dissipation and the error
mismatched series-connected devices sufficient time to reach between the reference and collector voltage waveforms.
the active region where their voltages may be controlled These cannot be expressed as analytic functions of the
easily. The main ramp then follows, during which the voltage parameters (gate resistance, feedback gain, etc.).
is controlled until it reaches the supply voltage VDC and the According to the Hooke and Jeeves Search [11], shown in
freewheel diode can turn on. fig. 4, after evaluating the objective function at points
The turn-on phase is characterised by an initial slowly- surrounding the current (base) point, a move in a particular
decreasing ramp, which allows the series-connected devices to direction is made. The search algorithm then tests to see if
commence turn-on together. A steeper ramp then follows to further movement in the same direction would give another
ensure the voltage decreases quickly, allowing rapid reduction in the objective function. This is known as a pattern
completion of switching to avoid excessive turn-on energy move. The search is terminated when there is no further
losses. improvement in objective function by moving in any
The controller is also shown in fig. 1. The feedback circuit, direction.
effectively a potential divider which reduces the large
B. Performance Evaluation
collector voltage to a suitable level for use in the control
circuit, has a cutoff frequency of ωFB and a gain of AFB. The An evaluation function was created to return key
op-amp buffer – realized in the gate drive with a wide- performance indicators, such as diode and IGBT power
dissipation, switching times and switching energy losses, peak
bandwidth op-amp – has a cutoff frequency of ωOP and a gain
of AOP. This drives the gate circuit with stray inductance LG diode reverse recovery voltage overshoot and the error
between the reference and collector voltages. Any of these
and resistance RG.
may be combined and weighted as required to form the
VREF
objective function. Ideally multiple objectives would be
VOFF
handled using a more advanced optimization algorithm [12]
capable of generating trade-off curves from which designers
VFALL
can draw conclusions regarding the compromises in
VRISE performance.
time The diode and IGBT power dissipations are the average
VON tRISE tOFF
power dissipations over one complete switching cycle,
tFALL tON
calculated using the total energy dissipation during this period.
Fig. 3. Reference waveform VREF used to control the collector voltage VCE. The diode peak recovery voltage overshoot is simply found by
searching for the most negative diode voltage during the IGBT
turn-on/diode turn-off switching event.

2061
 x2 Accepted increment A. Optimization of Power Dissipation and Diode Voltage
Rejected increment The profile P1 and the gate resistance RG were then optimized
Accepted pattern move
(optimization (1)) to minimise the power dissipation over the
Rejected pattern move
Base point
whole switching cycle, giving profile P2. Fig. 7 shows the
Pattern move point waveforms for profiles P1 and P2. The optimization has
effectively caused the devices to operate under hard switching.
The power dissipation values PDISS before and after
optimization are given in table II.
500

400 3 × IC

VCE (V), VREF (V), VAK (V), 3 × IC (A)

Minimum 300

200

100
x1 V CE
Start point
0
Fig. 4. Example of the Hook & Jeeves direct search with two variables.
V REF
-100
C. Gate Drive Turn-On Optimization
-200
The gate drive optimization concentrated on optimizing the VAK
reference voltage (VREF) turn-on profile and gate resistance -300
(RG), both to reduce the total (IGBT+diode) power losses and -400
to minimise the peak snubberless diode recovery voltage -4 -3 -2 -1 0 1 2
Time (µs)
overshoot (VRM). The need to maintain low losses is important
Fig. 5. Experimental (dotted) and simulated (solid black) waveforms for turn-
since the turn-on of the IGBT may incur large losses. The on with the original profile (P1) at 290V and 113A.
requirement to reduce the diode peak recovery voltage is
necessary to reduce the tendency for the freewheel diode to 500
‘snap’ during turn-off; indeed it has been found 400 3 × IC
experimentally [5] that forcing slower VREF ramps during
VCE (V), VREF (V), VAK (V), 3 × IC (A)

IGBT turn-on significantly reduces the diode peak recovery 300

voltage. These are generally conflicting requirements. 200

These objectives may be combined into one using a
100
weighted sum. The power dissipation is close to 1kW, and the VCE
peak recovery voltage is 1-2 times the supply voltage. Hence 0
it was decided to make the objective for some optimizations -100
VREF
equal to a simple sum of the power dissipation in kW and the
relative peak recovery voltage |VRM/VDC|: -200
VAK

f OBJ = PDISS + VRM VDC (2) -300

-400
16 17 18 19 20 21 22
D. Implementation Time (µs)
MATLAB is an ideal environment in which to implement Fig. 6. Experimental (dotted) and simulated (solid black) waveforms for turn-
this algorithm. Objective function evaluation consists of off with the original profile (P1) at 290V and 113A.
running the simulation in Simulink (using a MATLAB
600
function call) and analysing the data within MATLAB. This
500
must occur each time the objective function is required, i.e.
VCE (V), VREF (V), VAK (V), 3 × IC (A)

400 VREF
once for every point in the search space. Errors in simulation 3 × IC
are ignored; these generally involve lack of convergence or 300
VCE
excessive simulation times (indicating that the particular 200
simulation is unlikely to produce a result). This is achieved by 100
setting their objective function evaluations to infinity. 0
IV. RESULTS -100
Figs. 5 and 6 show experimental waveforms from the AVC -200
gate drive and corresponding simulation waveforms. These -300
VAK
demonstrate the action of the controller during turn-on and -400
turn-off respectively. The feedback gain AFB was set to 1/30.
-500
The supply voltage was 290V and the load current was 113A. -1 0 1 2 3 4 5
Time (µs)
The controller uses the original profile P1 as given in table I.
Fig. 7. Optimization (1): simulation waveforms for optimized and original
profiles (P2, solid, and P1, dotted, respectively).

2062
 TABLE I
PROFILE PARAMETERS 600
Profile tFALL tON VFALL RG 500
P1 3.5µs 1.1µs 185V 3.9Ω

VCE (V), VREF (V), VAK (V), 6 × IC (A)

400 VREF
P2 1.75µs 0.6µs 240V 10.9Ω 6 × IC
P3 2.25µs 0.3µs 180V 10.9Ω 300
VCE
P4 1.75µs 0.2µs 180V 10.9Ω 200
P5 2.6µs 0.7µs 204V 11Ω
P6 1.76µs 0.6µs 180V 11Ω 100
0
TABLE II
OPTIMIZATION RESULTS -100

Index Start End IL (A) PDISS* |VRM/VDC|* -200

Profile Profile start end start end
-300
1 P1 P2 113 2.04 1.20 1.00 1.65 VAK
2 P2 P3 113 1.20 1.38 1.65 1.00 -400
3 P3 P4 50 0.60 0.52 1.01 1.00
-500
*: Objective function consists of values shown in bold. -1 0 1 2 3 4 5
Time (µs)
Profile P2 was then optimized further (optimization (2)) by Fig. 9. Simulation waveforms for reduced current operation (50A), with the
original profile P1 (dotted) and the profile optimized for 113A (P3, solid).
minimising the weighted sum of the power dissipation PDISS
and the diode peak reverse recovery voltage VRM. The 600
simulation waveforms for the resulting profile, P3, are shown 500
in fig. 8, compared with those for P2. Values for PDISS and VREF
VCE (V), VREF (V), VAK (V), 6 × IC (A)
400
|VRM/VDC| are given in table I. 6 × IC
300
B. Effects of Optimization at Reduced Load Current VCE
200
The effect of reducing the load current to 50A is shown in 100
fig. 9. The original profile, P1, and P3, that optimized for 0
minimum power dissipation and diode voltage at the higher
-100
load current, are shown. Profile P3 is then optimized further
-200
(optimization (3)) for power dissipation and diode voltage at
the reduced load current, giving profile P4. Fig. 10 shows the -300 V AK
simulation waveforms for profiles P3 and P4. -400
-500
C. Practical Validation of Optimization Trends -1 0 1 2 3 4 5
The reference voltage generator used in these experiments Time (µs)
Fig. 10. Optimization (3): simulation waveforms at reduced current (50A),
did not allow arbitrary profiles to be generated. However,
with the profile optimised for 50A (P4, solid) and that for 113A (P3, dotted).
some adjustment of the profile was possible. Therefore, the
optimum profiles for 113A and 50A, P3 and P4 respectively,
were modified to allow practical implementation, resulting in 350

the creation of profiles P5 and P6 for 113A and 50A 300

respectively, given in table I. A comparison of the original 250
Original profile (P1)
profile P1 with P3–P6 is shown in fig. 11.
Reference voltage VREF (V)

200

150
600
100
500
V REF 50
VCE (V), VREF (V), V AK (V), 3 × IC (A)

400 3 × IC Optimum profile 113A (P3)

0
300 Practical profile 113A (P5)
VCE -50
200 Optimum profile 50A (P4)
100 -100
Practical profile 50A (P6)
0 -150
-1 0 1 2 3 4 5
-100 Time (µs)

-200 Fig. 11. Comparison of profiles used in validation of optimization trends.

-300
VAK
-400 Figs. 12 and 13 show the experimental and simulation
-500
waveforms for turn-on and turn-off respectively for profile P5.
-1 0 1 2 3 4 5 The supply voltage VDC is 283V and the load current is 100A.
Time (µs)
Similar waveforms are shown for the reduced load current of
Fig. 8. Optimization 2: simulation waveforms for the further optimized
profile P3 (including diode voltage, solid), compared with those for profile P2 50A, with a supply voltage of 290V and profile P6, in figs. 14
(dashed). and 15 for turn-on and turn-off respectively.

2063
 500 500
VREF
400 400

VCE (V), VREF (V), VAK (V), 6 × IC (A)

6 × IC
VCE (V), VREF (V), VAK (V), 3 × IC (A)

3 × IC
300 300
VCE
200 200

100 100 VREF

0 0
VCE
-100 -100

-200 -200 VAK

-300 VAK -300

-400 -400
-4 -3 -2 -1 0 1 2 18 19 20 21 22 23 24
Time (µs) Time (µs)
Fig. 12. Experimental (dotted) and simulated (solid black) waveforms for Fig. 15. Experimental (dotted) and simulated (solid black) waveforms for
turn-on with the practical profile (P5) at 283V and 100A. turn-off with the practical profile (P6) at 290V and 50A.

V. DISCUSSION
The results shown in section IV show that the simulation
500 captures the behaviour of the AVC gate drive correctly. The
turn-on waveforms in fig. 5 and the corresponding turn-off
400
3 × IC waveforms in fig. 6 exhibit the expected characteristics of the
VCE (V), VREF (V), VAK (V), 3 × IC (A)

300 AVC gate drive, including the preconditioning step and good
voltage following during switching. The two stage turn-on
200
profile results in the diode switching off significantly before
100 VREF the IGBT collector voltage has reached its on-state value.
0 A. Optimization of Power Dissipation and Diode Voltage
VCE
-100 Optimization (1) varies the reference voltage turn-on profile
to obtain the minimum overall power dissipation (diode and
-200 V AK
IGBT combined throughout one switching cycle). As
-300 expected this effectively removes active control of the gate,
-400 forcing the IGBT into hard switching. The peak diode reverse
17 18 19 20 21 22 23
recovery voltage thus becomes large in magnitude, as is
Time (µs)
Fig. 13. Experimental (dotted) and simulated (solid black) waveforms for
evident from fig. 7. This shows that the optimization correctly
turn-off with the practical profile (P5) at 283V and 100A. determines that hard switching produces the minimum losses.
However, the loss of control over the IGBT is not attractive
when switching series-connected devices, because they may
switch at different times and cause a severe voltage imbalance.
The reintroduction of a large diode peak reverse recovery
500 voltage is also unattractive.
400 V REF Optimization (2) improves on this by reducing the diode
VCE (V), VREF (V), VAK (V), 6 × IC (A)

6 × IC peak reverse recovery voltage, shown in fig. 8. This is

300
V CE achieved by delaying the second, steeper slope until the diode
200 peak reverse recovery current has just been reached. The
100
development of the diode reverse voltage is then tracked by
the reduction in IGBT collector voltage, thus eliminating
0 diode reverse recovery overshoot voltage. This second slope
-100 also acts to turn on the IGBT quickly to reduce the power
losses.
-200
The power dissipation is still included in the objective
-300 function in optimization (2) so that the gains made in
VAK
optimization (1) are not lost. Although the values in table II
-400
-4 -3 -2 -1 0 1 2 show that the power dissipation increases from 1.20kW to
Time (µs)
1.38kW, the total objective function value decreases from
Fig. 14. Experimental (dotted) and simulated (solid black) waveforms for
turn-on with the practical profile (P6) at 290V and 50A.
2.85 to 2.38. Clearly a limited sacrifice in power dissipation is
beneficial in improving the apparent overall system

2064
performance. However, it should be stressed that the choice
of weighting between power dissipation and diode peak
reverse recovery voltage depends ultimately on the
application. Different weightings would give rise to
correspondingly different optimum profiles.
It should be noted from table I that the gate resistance RG
also increases from 3.9Ω to 10.9Ω in the optimizations. The
principal effect of this is to delay the onset of turn-off during
the pre-conditioning step, shown in figs. 6, 13 and 15. During
this period the collector voltage is in the range of at least tens
of volts, with the full load current flowing through the device,
contributing significantly to the power dissipation. Delaying
the increase in VCE with larger values of RG therefore reduces
PDISS. An increased value of RG also improves stability.
These waveforms may be considered ideal.
B. Effects of Optimization at Reduced Load Current
Unfortunately the operation of the controller optimized for
113A varies noticeably at the reduced load current of 50A; the
smaller current allows switching to occur more quickly.
Therefore the diode has recovered before the IGBT collector
voltage reaches its on-state value, as is shown in fig. 9.
Nevertheless, it is still an improvement on the original profile,
also shown in fig. 9.
Optimization (3), shown in fig. 10, further improves the
combined objective of power dissipation and diode peak
reverse recovery voltage at 50A by making the profile steeper.
In addition to the profile becoming steeper, the duration of the
first slope (tFALL) is also reduced, so that, as with optimization
(2), the diode recovers just as the reference voltage is falling.
Undoubtedly the synchronisation is very attractive.
C. Practical Validation of Optimization Trends
The validation of the simulations is proven by the
comparisons with corresponding experimental results in figs.
12-15. The matching is close, although there is a small error
in the diode recovery voltage. While the practical profiles are
not identical to the optimized profiles, they do show that the
model is sufficiently accurate for prediction of controller
performance at several conditions. These waveforms suggest
that it is highly likely that the matching would also be good
for the optimized profiles. In any case, since the optimized
profiles (P3, P4) depend on the weighting applied, they are not
uniquely optimal; therefore exact matching of the practical
profile to the optimized profile when validating the
simulations is not of critical importance.
D. Further work
The AVC optimization would benefit greatly from the use
of a multiple-objective optimization algorithm, e.g. [12]. This
would avoid the need for a weighting, and allow the designer
to judge quickly the optimum trade-off. Optimization across
multiple conditions [13], particularly the load current and
temperature, would also be useful in ensuring a robust
controller design.
As observed experimentally and in simulation, there is a
strong tendency for the controller to oscillate at high feedback
gains (with AFB greater than approximately 1/30), which are
required for low-voltage operation. Increasing the damping
2065
factor has the disadvantage of increasing the tracking error
between VCE and VREF during switching. In such cases, the
optimization algorithm could be used to improve the tracking
(by reducing the mean error) and to decrease the chance of
oscillation (by reducing the variance of the error). Using the
mean squared error as the objective function in this case
would be suitable.
In practical systems, there is a string of series-connected
IGBTs. Since there will always be an inherent variation in
IGBT parameters, such as leakage current and threshold
voltage, the ability of a gate drive to maintain control of the
device may vary across the string. Simulation of a whole
series string and the subsequent application of robust
optimization methods would be a valuable asset in
determining the reliability of the system performance.
VI. CONCLUSIONS
The numerical optimization method outlined in this paper
has been shown to be an effective method of improving the
performance of the AVC gate drive. The gate resistance and
voltage reference profile during turn-on were varied to
improve the performance of the controller during IGBT turn-
on.
REFERENCES
[1] P.R. Palmer, H.S. Rajamani, ”Active Voltage control of IGBTs for high
power applications,” IEEE Transactions on Power Electronics, Volume:
19 , Issue: 4 , July 2004, pages:894 – 901.
[2] Y. Wang, M.S. Abu Khaizaran, P.R. Palmer, “Controlled switching of
high voltage IGBTs in series,” 2003 IEEE Conference on Electron
Devices and Solid-State Circuits, 16-18 Dec. 2003, Pages:297 – 300.
[3] P.R. Palmer, A.N. Githiari, “The series connection of IGBTs with
optimized voltage sharing in the switching transient,” Power Electronics
Specialists Conference, 1995. PESC ' 95 Record., 26th Annual IEEE,
Volume: 1, 18-22 June 1995 Pages:44 - 49 vol.1.
[4] P.R. Palmer, Y. Wang, M. Abu-Khaizaran, S. Finney, “Design of the
active voltage controller for series IGBTs,” in PESC Conf. Rec.,
Aachen, June 2004.
[5] Lim, T.C; Finney, S. J.; Williams, B. W; Palmer, P.R. “Active clamping
of series connected freewheel diode through active voltage control,”
PESC 04. 2004 IEEE 35th Annual, Vol. 3, 20-25 June 2004 pp. 1112 -
1117
[6] P.R. Palmer, E. Santi, J.L Hudgins, X. Kang, J.C. Joyce and X. Kang,
“Circuit simulator models for the diode and IGBT with full temperature
dependent features,” IEEE Trans. Power Electronics, vol. 18, no. 5,
pp.1220—1229, September 2003.
[7] P. Palmer, A. Bryant, J. Hudgins, and E. Santi, “Simulation and
optimization of diode and IGBT interaction in a chopper cell using
MATLAB and Simulink,” in IAS Conf. Rec., Pittsburgh, October 2002.
[8] X. Kang, A. Caiafa, E. Santi, J. Hudgins, and P. Palmer, “Parameter
extraction for a physics-based circuit simulator IGBT model,” in APEC
Conf. Rec., Miami, February 2003, pp. 946–952.
[9] A. Bryant, P. Palmer, J. Hudgins, E. Santi, and X. Kang, “The Use of a
Formal Optimization Procedure in Automatic Parameter Extraction of
Power Semiconductor Devices,” in PESC Conf. Rec., Acapulco, June
2003.
[10] W. Murray, Numerical Methods for Unconstrained Optimization.
London, 1972.
[11] R. Hooke and T.A. Jeeves, “Direct search solution of numerical and
statistical problems,” Journal for the Association for Computing
Machinery, Vol. 8, No.2, pp. 212-229, April 1961.
[12] D.M. Jaeggi, C.S. Asselin-Miller, G.T. Parks, T. Kipouros, T. Bell and
P.J. Clarkson, “Multi-objective Parallel Tabu Search,” submitted to 8th
Int. Conf. Parallel Problem Solving from Nature (2004).
[13] A.T. Bryant, D.M. Jaeggi, G.T. Parks, P.R. Palmer, “The Influence of
Operating Conditions on Multi-Objective Optimization of Power
Electronic Devices and Circuits,” to be published in IAS Conf. Rec.,
Hong Kong, October 2005.