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Registration Form

1. Participant name

:

2. Name of the organization

:

3. Designation

:

4. Address

:

5. Cell No

:

6. E mail id :

:

7. Preferable Slot (Ref: Course Calendar)

:

8. DD no

:

9. DD date

:

10. Bank Name

:

11. Accommodation Required

:

YES

: 10. Bank Name : 11. Accommodation Required : YES No (Accommodation will be arranged in

No

: 10. Bank Name : 11. Accommodation Required : YES No (Accommodation will be arranged in

(Accommodation will be arranged in students Hostel at cost of Rs.300/- per (includes food)

Participants Signature

:

CONVENER:

Dr. Zachariah C. Alex

Director, School of Electronics Engineering VIT University

 

Pay by Demand Draft Drawn in favour of “VIT University” Send the DD along with the Registration form to

CO ORDINATORS

WIND RIVER

The Coordinator [Vx Works Training] Embedded System Division

Dr.Krishna Navuluri Krishna.srivatsa@windriver.com

School of Electronics

Engineering

VIT University Vellore 632 014, Tamilnadu.

EMBEDDED SYSTEM DIVISION School of Electronics Engineering VIT University

 

PROF.R.PRAKASH PROF.B.KARTHIKEYAN PROF.T.N.PADMINI PROF .S.SUNDAR

- 9486265296

- rprakash@vit.ac.in - bkarthikeyan@vit.ac.in -tnpadmini@vit.ac.in - sundar.s@vit.ac.in

- 9865521366

- 9786026007

- 9629434950

PROF.M.SHANMUGASUNDARAM - 9444241211

- mshanmugasundaram@vit.ac.in

PROF.P.CHITRA

- 9952456249

- chitra.p@vit.ac.in

PROF.P.CHITRA - 9952456249 - chitra.p@vit.ac.in VIT UNIVERSITY, Vellore & WIND RIVER Announces 4 days
PROF.P.CHITRA - 9952456249 - chitra.p@vit.ac.in VIT UNIVERSITY, Vellore & WIND RIVER Announces 4 days

VIT UNIVERSITY, Vellore

&

WIND RIVER

Announces 4 days certificate course

VIT

U N I V E R S I T Y

(Estd. u/s 3 of UGC Act 1956)

on

REAL TIME OPERATING SYSTEMS (RTOS)

for

EMBEDDED SYSTEMS & WORKBENCH FOR VX WORKS 6.X

Resources: Certified Vx Works Trainers from WIND RIVER WIND RIVER Certified International Syllabus

VENUE: TT603 Embedded System Laboratory School Of Electronics Engineering, VIT University

International Syllabus VENUE: TT603 – Embedded System Laboratory School Of Electronics Engineering, VIT University

COURSE AGENDA LEVEL- I

COURSE AGENDA LEVEL- II

Day 1

 

Day 4

Real-Time Architectures Review of Real-Time Operating Systems Requirements Analysis State Machines Partitioning Software into Tasks

Day 2

Queue modeling Intertask synchronization Device i/o driver models Encapsulation techniques Miscellaneous topics Real-time scheduling is not intuitive Basics of rate monotonic analysis More complex rate monotonic analysis Blocking Problems and Their Solutions

Source Analysis Source Analysis Views Navigating Workspace Resources Editor Features Source Analysis Lab

Wind River System Viewer System Viewer System Viewer Configuration and Log Explanation Triggering User Events System Viewer Lab Data Monitor Performance Profiler Memory Analyzer Coverage Analyzer

 

Day 3

 

Function Tracer Analysis Tools Lab

 

Workbench Overview and Managing Targets Workbench Perspectives Help Resources Cross-Development Setup

   
 

Registration Details

Course calendar

   

Target Manager Configuration Getting Started Lab

 

Project Management Introduction to VxWorks Projects Project Explorer Overview Application Projects Build Specifications Project Management Lab

Debugging

Slot

 

Date

Course

Amount

 

No

   

level

Industry

Faculty/

Students

1

   

January 7 th

11 th ,2011

Level I

40,000/-

20,000/-

Debugger Feature Overview Configuration GUI and Usage Overview (setting breakpoints, etc.) Kernel-Space and Application-Space Debugging Debugging Lab

2

 

January 17 th

Level II

40,000/-

20,000/-

 

20 th ,2011

3

 

February 20 th

Level I

40,000/-

20,000/-

 

- 24 th ,2011

4

   

March 20 th -

Level I

40,000/-

20,000/-

24 th -,2011

Using VxWorks Shells Introduction to VxWorks Shells Host Shell and Shell Interpreters Kernel Shell VxWorks Shell Lab

           
   
   
                Day1 Getting Started Product Overview Workbench 3.2

Day1

Getting Started Product Overview Workbench 3.2 Features Product Delivery, Installation and Licensing Host Support VxWorks 6.8 Features Using the VxWorks Simulator Introduction to VxSim Remote Systems Target Server Connections VxWorks Simulator Configuration Connecting to VxSim Wind Debug Agent (WDB) VxWorks Simulator VxSim Lab Managing Projects in Workbench Introduction to VxWorks Projects Project Explorer Overview Application Projects Build Specifications Project Management Lab VxWorks Source Builds Introduction and Purpose of VSBs Workbench Projects Command-Line Usage VSB Options, Projects and VxWorks Builds VSB Lab

Day4

Real-Time Processes (RTPs) RTP Overview RTP File Generation Starting an Application Shared Data Usage and Library Usage Real-Time Processes Lab Exceptions, Interrupts, and Timers Exceptions Using Signals to Recover from Hardware Exceptions/Fatal Errors Interrupts Interrupt Flow Example ISR Stack, ISR Restrictions Timers Watchdog Interface and Polling Auxiliary Clock for Polling at Higher Speed Exceptions, Interrupts, and Timers Lab Error Detection and Reporting Error Reporting Framework Persistent Memory Error Records Error Detection and Reporting Configuration Error Detection and Reporting Lab System Viewer System Viewer System Viewer Configuration and Log Explanation Triggering User Events System Viewer Lab

 

Day2

Using VxWorks Shells Introduction to VxWorks Shells Host Shell and Shell Interpreters Kernel Shell Host Shell Lab

Debugging

Debugger Feature Overview Configuration GUI and Usage Overview (Setting Breakpoints, etc.) Kernel-Space and Application-Space Debugging Debugger Lab Real-Time Multitasking Multitasking Environment Overview Task Creation and Deletion Other Task APIs (task DeLay(), Task Variables, Task Hooks, etc.) System Tasks Real-Time Multitasking Lab VxWorks Events Event Register Task Synchronization Events Lab

Day 3

 

TECHNOLOGY SUMMARY

 

Host OS

Windows

Arch/Target(s) probes

Power PC /wind River SBC power QUICCI II for 8548/Wind River Probe

WR Standard products used in course ,incl. Product version

General Purpose Platform ,Vx works Edition 3.8

WR background

Technology

Workbench 3.2,Vx Works ,Wind River Probe

 
 

Semaphores

 

Semaphores and Synchronization Mutual Exclusion Semaphores Semaphores Lab Intertask Communication Shared Memory Message Queues Pipes Intertask Communications Lab Memory Memory Maps Memory Allocation Memory Management Routines Partition Management