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Ring oscillator Primer


J P Silver E-mail: john@rfic.co.uk

1 ABSTRACT
This tutorial describes the operation of a basic ring oscillator as used in RFIC circuits etc. The pertinent design parameters are given together with their relevant equations to allow basic hand calculations before simulation is attempted. Finally a worked example is given to highlight the design steps required and CAD simulations are also described.

Inverting Amplifier resonator

Output load

X Vout

2 INTRODUCTION
Ring oscillators are probably the simplest type of oscillator used in RFIC design. They can be designed for a fixed frequency and variable frequency operation. They are usually included on the die as a way of checking the process used in manufacturing the die to see it meets the relevant spice predictions thus verifying other circuits on the chip.

+
Zin Rload Z = Zin

Figure 1 Closed loop (a) and open loop (b) oscillator models. Figure 16a shows the closed

3 RING OSCILLATOR DESIGN


3.1 OSCILLATOR THEORY An amplifier provides an output that is a replica of the input. An oscillator provides an output at a specific frequency with no input signal required. Figure 1 shows the three fundamental parts of a feedback oscillator ie the amplifier (capable of amplifying at the frequency of interest) a resonator (the frequency selective component) and an output load. The resonator may contain transformers or other impedance transforming components such as coupling capacitors. There will be no output when power is initially applied, but even if the amplifier were noise free, noise would still be generated in the resonator at the resonant frequency. This noise will be applied to the input of the amplifier where it will be amplified and fed back in phase at the resonant frequency and further amplified, building up each time. Eventually the signal will cause the amplifier to limit, ensuring that the oscillator output power eventually peaks, usually at the saturated output power of the amplifier.

loop model with the three main parts of the oscillator the resonator, active INVERTINGdevice and output load. To aid analysis the loop is often broken at point X to form the open loop model shown in figure 16b. The open loop model can be analysed, for insertion magnitude and phase difference. At the required oscillator frequency the phase difference through the loop must be 180 (or multiples of 180 degrees) and that the corresponding loop gain magnitude is maximum and greater than unity. NOTE the resonator can be low-pass, highpass or band-pass filter The oscillator loop gain is given by:-

Af =

A 1 A

Af = gain after feedback A = open loop gain = feedback factor

The gain A will be infinite when the loop gain is unity and the phase shift is 360. This is known as the

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Barkhausen criterion for oscillation in a POSTIVE FEEDBACK circuit. For a NEGATIVE FEEDBACK circuit we require a phase shift of 180 and these type of circuits are used in CMOS oscillator designs. 3.2 SMALL SIGNAL ANALYSIS The most common CMOS oscillator is known as the Ring oscillator which, consist of a cascade of inverting amplifiers. Capacitors are connected to the load resistors, forming a low-pass filter and therefore, create the frequency dependence for the amplifier. The following pages follow the evolution of a ringoscillator example using standard NMOS data, a bias current of 100uA for each stage and a single-stage 3dB breakpoint of 10MHz. Figure 2 shows a simple amplifier stage suitable for the ring oscillator.

Gain(dB) = 20 log.(gm.R LOAD ) 2.K N.W.ID L 2.110E - 6 .10.100E - 6 = 4.69E - 4 1

gm =

Gain(dB) = 20 log.( 4.69E - 4 .10E3 ) = 13dB Then the pole at Fpole1 = 1 = 10MHz 2 .10E 3 .1.59E -12

For 100uA bias current

Vgs = VT +

2.L.IREF W.K N 2.1.100E- 6 10.110E- 6

0.7 +

= 1.13V

RLOAD

frequency response shown in figure 6. We have now introduced an additional phase shift of 90 degrees giving 180 in total. We note we can obtain the correct phase of 360 degrees for oscillation, but this occurs after the gain has dropped below the 0dB gain line (shown by the red dotted line). Therefore oscillation will not occur.

VIN CLOAD

VOUT

Gain(dB) = 20 log.(Av ) = 20log(gm.R LOAD ) 2


2

Figure 2 Basic inverting amplifier cell with capacitor load used in the ring oscillator If were to analyse the amplifier shown in Figure 2 (assuming W/L = 10) we would obtain the gain/phase vs frequency response shown in figure 4, using the ADS simulation shown in figure 3.

However, in most applications there is always plenty of gain!

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AC
AC AC1 Start=1.0 kHz Stop=50 MHz Step=

I_Probe I_Probe1 R R3 R=10 kOhm

V_DC SRC1 Vdc=5 V

LEVEL1_Model MOSFETM1 Vto=0.7 Kp=110e-6 Gamma=0.6 Phi=0.8 Lambda=LAMBDA Pb=0.95 Cgso=220e-12 Cgdo=220e-12 Cgbo=700e-12 Cj=770e-6 Mj=0.5 Cjsw=5e-10 Mjsw=0.38 Tox=140e-10 Ld=0.016 um

DC
DC DC1
Var Eqn

Vout C C1 C=1.59 pF

V_AC SRC2 Vac=polar(1,0) V Freq=freq

VAR VAR1 LAMBDA=0.01/L L=1 W=10

MOSFET_NMOS MOSFET1 Model=MOSFETM1 Length=L um Width=W um

Figure 3 ADS simulation setup for a single-stage inverting amplifier with output low-pass filter with a 3dB breakpoint of 10MHz.

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m1 freq=10.16MHz dB(AC.Vout)=13.752
20

DC.I_Probe1.i 210.5uA

15

m1

10

0 1E3 1E4 1E5 1E6 1E7 5E7

dB(AC.Vout)
180

freq, Hz

135

90

45

-45

-90

-135

-180 1E3 1E4 1E5 1E6 1E7 5E7

phase(AC.Vout), deg

freq, Hz

Figure 4 ADS simulation result for a single-stage inverting amplifier with output low-pass filter as shown in figure 3. The 3-dB breakpoint is at 10MHz as predicted.

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Var Eqn

VAR VAR1 LAMBDA=0.01/L L=1 W=10 I_Probe I_Probe1

V_DC SRC1 Vdc=5 V

AC
AC AC1 Start=100 kHz Stop=50 MHz Step= R R4 R=10 kOhm

LEVEL1_Model MOSFETM1 Vto=0.7 Kp=110e-6 Gamma=0.6 Phi=0.8 Lambda=LAMBDA Pb=0.95 Cgso=220e-12 Cgdo=220e-12 Cgbo=700e-12 Cj=770e-6 Mj=0.5 Cjsw=5e-10 Mjsw=0.38 Tox=140e-10 Ld=0.016 um

R R3 R=10 kOhm

DC_Block DC_Block1

DC
DC DC1

C C1 C=1.59 pF

Vout C C2 C=1.59 pF MOSFET_NMOS MOSFET2 Model=MOSFETM1 Length=L um Width=W um

V_AC SRC2 Vdc=1.3 V Vac=polar(1,0) V Freq=freq

MOSFET_NMOS MOSFET1 Model=MOSFETM1 Length=L um Width=W um

DC_Feed DC_Feed1 V_DC SRC3 Vdc=1.3 V

Figure 5 ADS simulation setup for a two-stage inverting amplifier with output low-pass filter with a 3dB breakpoint of 10MHz.

If we add a third inverting stage we obtain the gain/phase frequency response shown in figure 8, with the ADS simulation shown in figure 7. In this case we can see that at the 0 degree phase crossover point there is positive gain (~30dB) and when the output is fed back to the input (ie negative feedback) the circuit should oscillate at ~ 17MHz. In this case the phase contribution of the RC networks is 180 degrees 60 = 120 degrees per stage. Broadband noise will be amplified in phase at the oscillation frequency until the gate voltage rises to VT+VSAT. This will cause the stage to switch on, but as the output contains a R-C filter there will be a delay before the input to the next stage rises to VSAT+VT and switches that stage on. Figure 9 shows the waveforms through the oscillator shown in figure 7. The oscillation will therefore be:-

The minimum gain required for oscillation to occur at the 0 (or 360) degree phase frequency is:
fosc = 3.fo Where fo = frequency of the RC network on each stage, and Avo = Voltage gain at 0Hz Avo3
2 fosc 1+ fo 3

=1

Avo3
2 1 + 3.fo fo 3

Avo3 1+

( 3)
2

[ 1 + (3)] [ 4]
3

Avo3

Avo = 4 = 2 = 6dB

Fosc =

3 2 .R LOAD .C LOAD

[ 4]

Avo3
3

= 1 Avo3 =

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It must be stressed that the simulations given so far are SMALL SIGNAL only! We have added a convenient fixed bias to each stage in order to perform the AC analysis. In reality each stage will be switching from the supply of 5V to zero with a time delay equivalent to 360/number of stages. Although there is fixed 10K resistor on each load no account has been taken of the large signal effect of the internal drain-source resistance that is in parallel with the load resistor. Any increase in this internal resistance will lower the overall load resistance and increase the frequency of operation. On startup the oscillation frequency will be that determined by small signal analysis ie

The next evolution to a more practical circuit is to use active loads instead of the resistors. The problem with using current sources is that they will reduce the voltage swing of the VCO and for this reason the push-pull inverting amplifier (as shown in Figure 6) can be used as this can switch to the supply rails.
Vcc P-Type CMOS TR1

Fsmall signal = 3.f singlecell


However, as the amplitude builds up and switching of the cells occur then the large-signal oscillating frequency will take over as described in the next section. 3.3 LARGE SIGNAL ANALYSIS Therefore, when designing the ring oscillator it is better to calculate the new value of load resistance and any other capacitive parasitics that may effect the frequency of operation (capacitors will lower the frequency and resistances in parallel with the load resistance will increase the frequency). The oscillation this circuit can also be described in terms of the delay ie

CL Vin Vout

N-Type CMOS TR2

Figure 6 CMOS Inverting amplifier cell. As the input voltage rises from zero to Vcc the TR1 will be hard on and TR2 off and as the voltage rises to VCC/2 both devices will be on and as the voltage rises still further TR1 will turn off and TR2 will be hard on. The load capacitor CL will charge and discharge as vout changes depending on the resistance looking into the tied drains of TR1 and TR2. If an odd number of inverters are connected in series then the capacitor in conjunction with Rload will cause a delay in the voltage reaching the next stage. This delay equates to a phase shift. Using the calculated Rload and Cload we can calculate the oscillation frequency as:
N= the number of stages Rn = equivalent resistance of N device Rp = equivalent resistance of P device 1 1 = f= N.(Rn + Rp)Cload T

N= the number of stages td = time delay of each stage (s) = n + p f= 1 1 = T 2.N.(td)

To ensure that the rise and fall time are equal to td we must make the N & P type devices equal to each other ie

P .C OX .

W WP = N .C OX . N LN LP

To calculate the load resistances we can use the following equation:

As up and un are not the same the ratios of W/L have to be altered so that the above condition is met.

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Rn =

VDD KPn W (VDD VTHN)2 . 2 L VDD KPn 2 .(VDD VTHN ) 2

L W

Also Rn can be described in terms of BSIM parameters:

Rn =

MUZ.Cox.W (VDD VTHN )

2L.VDD

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DC.I_Probe1.i 210.5uA
35 30 25 20 15 10 5 1E5 1E6 1E7 5E7

m1

dB(AC.Vout)
180

freq, Hz

135

90

45

m1 freq=6.494MHz dB(AC.Vout)=30.469

-45

-90

-135

-180 1E5 1E6 1E7 5E7

phase(AC.Vout), deg

freq, Hz

Figure 7 ADS simulation result for a two-stage inverting amplifier with output low-pass filters as shown in figure 5. The 3-dB breakpoint is at 10MHz as predicted.

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V_DC SRC1 Vdc=5 V

Var Eqn

AC
AC AC1 Start=100 kHz Stop=50 MHz Step= I_Probe I_Probe1 R R3 R=10 kOhm DC_Block DC_Block1 R R4 R=10 kOhm

VAR VAR1 LAMBDA=0.01/L L=1 W=10

LEVEL1_Model MOSFETM1 Vto=0.7 Kp=110e-6 Gamma=0.6 Phi=0.8 Lambda=LAMBDA Pb=0.95 Cgso=220e-12 Cgdo=220e-12 Cgbo=700e-12 Cj=770e-6 Mj=0.5 Cjsw=5e-10 Mjsw=0.38 Tox=140e-10 Ld=0.016 um

R R5 R=10 kOhm DC_Block DC_Block2

DC
DC DC1

V2 V1
C C1 C=1.59 pF DC_Feed DC_Feed1 V_DC SRC3 Vdc=1.3 V MOSFET_NMOS MOSFET2 Model=MOSFETM1 Length=L um Width=W um

V3

C C3 C=1.59 pF

Vout

V_AC SRC2 Vdc=1.3 V Vac=polar(1,0) V Freq=freq MOSFET_NMOS MOSFET1 Model=MOSFETM1 Length=L um Width=W um

C C2 C=1.59 pF

DC_Feed DC_Feed2

MOSFET_NMOS MOSFET3 Model=MOSFETM1 Length=L um Width=W um

V_DC SRC4 Vdc=1.3 V

Figure 8 ADS simulation setup for a three-stage inverting amplifier with output low-pass filters, with a 3dB breakpoint of root 3 x 10MHz ~ 17MHz.

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m1 freq=4.995MHz dB(AC.Vout)=47.340
60 50 40 30 20 10 0 1E5 1E6

DC.I_Probe1.i 210.5uA

Oscillation frequency

m1

1E7

5E7

dB(AC.Vout)
180

freq, Hz

135

90

45

m2
0

-45

-90

-135

m2 freq=17.43MHz phase(AC.Vout)=519.5mdeg
1E5 1E6 1E7 5E7

-180

phase(AC.Vout), deg

freq, Hz

Figure 9 ADS simulation result for a three-stage inverting amplifier with output lowpass filters as shown in figure 7. The 3-dB breakpoint is at root 3 times 10MHz ~ 17.3MHz as predicted. In this case we have positive gain at the 0 degree phase point and when the loop is closed the circuit should oscillate.

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V1 Delay td

V2

V3

Time Period = 6td

Figure 10 Time domain diagram of the signals through the 3-stage ring oscillator. Each stage is delayed by the time constant Rload.Cload = td.
Cin = 3 Cox ' (WnLn + WpLp ) 2

In terms of time delays we have from high to low-

(high low ) = RP.Cload


and for low to high

Where Cox ' = Cox.W.L Cox = Eox TOX Eox = Er + Eo

(low high ) = RN.Cload


Where Cload = added load capacitor + parasitic output capacitor. Parasitic capacitances are present as the gate forms a plate capacitor with the oxide insulator. The input and output device capacitances are given by the following:

Where Er = Dielectric constant of silicon ~ 3.46 Eo = Dielectric of free - space = 8.85E -12 Cout = Cox ' ( WnLn + WpLp )

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4 CONCLUSION
This tutorial describes the small signal operation of a ring oscillator, which is useful in gaining insight as to why the oscillator works at a particular frequency. For accurate design the effects of the parasitic capacitors have to be considered as well as the load capacitance. With this information the rise and fall time delays can be calculated and knowing the number of cells being used the operating frequency can be predicted. Additional tutorials will give examples of a fixed frequency ring oscillator and a variable frequency ring oscillator (VCO). Using ADS is it possible to simulate using harmonic balance to predict, output frequency (and harmonics), output power and phase noise performance.