MiddleEastTechnicalUniversity ElectricalandElectronicsEngineeringDepartment

EE413IntroductiontoVLSIDesign

Tutorials

METUMEMSVLSIResearchGroup

Lastupdatedon20091028

TABLEOFCONTENTS
1. UsingPCLaboratory...................................................................................................................................3 1.1. Introduction..........................................................................................................................................3 1.2. RunningCadence..................................................................................................................................3
1.2.1. 1.2.2. 1.2.3. InitializingCadenceEnvironment.....................................................................................................................3 RunningCadence..............................................................................................................................................4 HowtoLogout?................................................................................................................................................4

2. SchematicEntryofaCMOSInverter.......................................................................................................5 2.1. CreateaNewLibrary...........................................................................................................................5 2.2. SchematicsofaCMOSInverter...........................................................................................................6 3. TransientSimulationofSchematics...........................................................................................................9 4. BasicsofLayoutDrawing.........................................................................................................................12 4.1. WhatisLAYOUT?.............................................................................................................................12 4.2. CMOSProcessandLayoutDrawingStepbyStep............................................................................12
4.2.1. 4.2.2. 4.2.3. 4.2.4. 4.2.5. 4.2.6. Step1ActiveRegionsandWells.................................................................................................................12 Step2Polysilicon.........................................................................................................................................13 Step3N+andP+Diffusion..........................................................................................................................13 Step4Contacts..............................................................................................................................................13 Step5MetalDeposition................................................................................................................................14 FinalView........................................................................................................................................................14

5. LayoutDrawingUsingCadence...............................................................................................................15 5.1. DesignRules.......................................................................................................................................15

5.1.1. 5.1.2. Layers...............................................................................................................................................................15 DesignRulesOverview...................................................................................................................................15

5.2. LayoutoftheInverter.........................................................................................................................17 6. LayoutversusSchematicCheck(LVS)....................................................................................................24 7. SimulationoftheInverterLayout............................................................................................................28 8. ASampleDesignFlow...............................................................................................................................29

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1. USINGPCLABORATORY
1.1. Introduction
Thereare9personalcomputersinthislaboratory.InsteadofMicrosoftWindowsOS,Ubuntuisinstalledon computers.SoyouwillbefamiliarwithLinuxenvironment.ThereasonforusingaLinuxOSisitsimplifies theprocedureforrunningtheCadence.Differentfrompreviousyears,Cadencewillrunonthesecomputers insteadofaterminal.

1.2. RunningCadence
Cadence is one of the most widely used IC design software all over the world. It contains many subprogramseachofwhichisresponsiblefromonestepinICdesignflow.Inthecontentofthiscourse,you willlearnlowlevel(transistorlevel)designtoolsofthecadence. Alltheusershaveausernameandapassword.Dochangeyourpasswordassoonaspossible,andprefer complexpasswordscontainingbothletters(withdifferentcaps)andnumbers,andalsopunctuations.To changeyourpasswordopenaterminalviaApplicationsAccessoriesTerminal.Interminalusepasswd command.Enteryouroldpasswordandthenenteryournewpasswordtwice. InordertorunCadenceonUNIXmachines,followthefollowingguidelines: 1.2.1. InitializingCadenceEnvironment Withthestepsinthepreviouspart,youareconnectedtotheserverandreadytorunCadence.Inordertorun Cadenceforthefirsttime,youneedtoinitializeyourworkingdirectory.Forthispurposefollowthenext steps: 0. Turnonthecomputerifitisnot,andlogintoUbuntubyusingyourusernameandpassword. 1. Openaterminal:ApplicationsAccessoriesTerminal 2. mkdirCadence ThiswillmakeadirectorynamedCadence. 3. cdCadence EnternewlycreatedCadencedirectory. 4. lns/Cadence/DesignKits/XFAB_XC06/cadence/env/bin/tkit. ThiscommandgeneratesalinktothescriptfilerequiredtorunCadence. 5. ./tkitmfbtechxc06 Runcadenceforthefirsttime,choosexc06asthetechnology,whichisXFab0.6utechnologywith2 metaland1polylayers. So,youhavearunningcadenceatthemoment.Rememberthat,thepreviousstepsareforinitializingthe cadenceforthefirsttime,andtheyshouldbedoneonceonly.NowclosecadencebyFile>Exit. 1.2.2. RunningCadence Youhaveinitializedcadenceinthepreviouspart.Afterthefirstrun,youneedtodothefollowingthingsto runcadence: 0. Openaterminal
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1. cdCadence 2. ./tkitmfb& Thatisall.Cadenceshouldberunning. 1.2.3. HowtoLogout? Whenyoulogout,makesurethatnoprogramsarerunning. Ifcadenceisrunningforexample,closeit. ThenclickonyournameatupperrightofthescreenandclickLogout.... Afterthis,theloginscreen shouldcomeback. SoyouloggedoutfromUbuntu,anditwaitsforyoutologinagain. Nowyoucan leave.

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2. SCHEMATICENTRYOFACMOSINVERTER
Inthistutorial,youwillstartusingCadenceanddesignyourfirstCMOSgate:aninverter.Believeornot, workingonthefirstinverteristhemostimportantpartoftheoveralllaboratorywork.Youwilllearnmuch. Donotpassthestepsunlessyouhaveunderstoodwhatyouaredoing. Ifyougetsomeproblem,donot hesitatetoasktoyourassistant.Donotforgetthat,youhavetolearneverystepinthistutorial.

2.1. CreateaNewLibrary
Beforestartingtoyourfirstdesign,youneedtocreatealibrary,whichwillcontainallthecircuits thatyouwillimplementduringthislaboratory. 1. Startcadence. 2. Open library manager window by Tools>Library Manager... on icfbwindow. 3. Onlibrarymanagerwindow,chooseFile>New>Library. 4. Write down "EE413" to the name of the library as seen on the figure. 5. In save destination, delete /mnt/maxell so that destination begins with/homes/ee413.ThenpressOK. 6. Each library should be attached to a technology library (or technology file). A technology library contains required information about the technology you are using, like DRC ExtractionLVSrules,contactdimensions,etc(youwillunderstand theselater:).Onthenewlyappearedwindow,clickon"Attachto anexistingtechfile"radiobuttonandclickOK. 7. Again,anewwindowwillappeartochoosethetechnologylibrary. Choose"TECH_XC06"fromthepulldownmenu.ThisisthetechnologylibraryforXFab0.6u process.

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2.2. SchematicsofaCMOSInverter
Wegotanewlibrary.Now,wewillgoonbymakinganewcell. 1. Clickonlibrary"EE413"youhaveaddedpreviously.Onthelibrarymanager,thereare3columnsas yousee.Leftmostonecontainsthelibraries,themiddleonecontainsthecellviewsintheselected library, and the column on the right contains the views of the selected cellview. Libraries are composedofcellviews(whicharecircuitsthatyouwillimplement,likeinverter,nand,etc.).Each cellview should have different name in a library. Each cellview contains views like schematic, symbol,andlayout.Thesearepredefinednamesandyouwilllearnwhattheyarebyfollowingthe tutorials. 2. At the moment, there is no cellview in the "EE413" libraryyet.ClickonFile>New>CellViewinorderto createone.Write"inverter"totheCellName.Although theyaredefault,besurethatViewNameis"schematic", andToolis"ComposerSchematic".Thismeansthatyou willuseComposertocreateyourschematicview.Click OK. 3. VirtuosoSchematicEditingwindowshouldbeopened.As you see, you will work with a black background. You shouldknowthat,thisschematictoolisoneofthebest thatyouwilluseinthefuture. There is a tool box on the left and a pulldown menu on the top of the window. Most of the commandsinthemenushaveshortkeysandyouareexpectedtolearntherequiredshortkeysat leasttheonesmentionedinthetutorials. 4. Nowwewilladdatransistor.Clickon Add>Instance fromthemenu.Theshortcutkeyforthis commandis"i".Inotherwords,simplypressing"i"keyissameasclickingAdd>Instance. 5. "AddInstance"windowwillbeopenedlikefigurebelow.Write"PRIMLIB"toLibraryand"nmos4" toCell.Viewwillbe"Symbol"bydefault,checkit.YoumaybrowsethelibrariesusingBrowse buttonalso.Width,lengthandotherpropertiesofthetransistorcanbechangedinthiswindow,or youcanchangethemlater. FocustotheschematiceditorandinsertoneNMOStransistor.Dothesamethingfor"pmos4"cell and insert one PMOS transistor. Do not forget that you are making an inverter, so put PMOS transistortotopforbetterunderstanding. 2

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6. Now,youwilladdpinsofthecircuit,whichareconnectionstotheouterworld,liketheinputandthe outputconnections ofthecircuit.Clickon Add>Pin orsimplypress"p"toaddthepinsofthe circuit.Youwilladd2pins,AandQ,whichwillbetheinputandtheoutputrespectively.Donot forgettochoosedirectionofAasinputanddirectionofBasoutput. 7. Now,youwilladdvddandgndofthecircuit.Similartostep5,add"vdd"and"gnd"cellsfrom "PRIMLIB"library. 8. Onepointshouldbenotedhere.Youcanzoominoroutbyusingthebuttonsonthetoolbaronthe left,orusingWindow>Zoom."f"autozoomsthecurrentdesign.Oryoumayclickanddragusing 3rdbutton(rightbutton)ofthemouse,whichzoomsthedrawnbox.Tryandsee. Wheneveryou havezoomedtoawrongplace,pressfinordertofitthecircuit. 9. Now,youwilldrawtheconnections,orsimplywiresofthecircuit.ClickonAdd>Wire(narrow)or press"w".Clickatthestartandendpointsofthewires.Donotforgettoconnectbulkconnectionsof transistorasseeninthefigure. 10. Yourcircuitisalmostcompleted.Clickon Design>Check and Save in order to check and savewhetherthereisanyunconnectedpinornot. If you get some warning messages, check the yellowmarkers. Ifthereisnoproblem,youwill notgetanywarningorerror. GeneratingSymbolfromSchematics... 11. Everycellshouldhaveasymbolviewinordertobe usedinothercircuits.Clickon Design>Create Cell View>From CellView. Be sure that "To View Name" is "symbol" and "Tool/DataType"is"ComposerSymbol"assimilar tothefollowingfigure.ClickOK.

12. Youwillget"SymbolGenerationOptions"window.ClickOKwithdefaultsettings. 13. Anewwindowwillappearshowingyournewboxshapedsymbolview.Inputsareontheleftand outputsareontheright.Althoughcadencedoesnotcare,itisnotverypropertousethisboxshaped symbolasinvertersymbol.Onecandrawhis/herownsymbolbyusing"Add>Symbol>Line"and "Circle"andothertools.Althoughitisnotdifficultforinverter,itwillnotbeeasytodrawproper symbolsforthecircuitsyouwilldesigninthefuture,andyoudon'twanttoloosetimewithdrawing boxes,etc. 14. ThereisaD_CELLSlibrary.Clicktorightmousebuttonon"INX1"cell's"symbol"viewand choose"Copy".Anewdialogwindowwillappearinordertochoosethesourceanddestinationof copyingprocess.Fill"To"partasEE413,inverterandsymbolaslibrary,cell,andview.Click onOK.Ifanewdialogboxappearsthatthereisalreadyasymbolviewatthedestination,clickon OverwriteallandthenOKbuttons.
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15. ChecktheinvertersymbolinEE413librarywhetherthecopyisdonecorrectlyornot.Thesymbol shouldbeatraditionalinverter. 16. That'sall.Youdesignedtheschematicsandcopiedthesymboloftheinverter.Youarereadytogoon withthesimulationsofthisschematics.Beforethis,letmeaddafewnoteshere. NOTES 1. Youcanseethepropertiesoftransistorsoranyothercomponentsbypressing"q"orclickingon Edit>Properties>Objects,afterchoosingtheobject(byclickingonit).Whenanobjectisselected, itsbordersbecomevisible.Forthetransistors,itispossiblechangetheaspectratiosbychanging "Width"and"Length",whichare"0.8u"and"0.6u"bydefault."u"isusedformicroand"m"isused for"mili"here. 2. Youcanmoveobjectsby"m"or"Edit>Move".Copyanddeletingobjectsaresimilaralso.Seethe menusandshortcuts. 3. Itispossibletochangethelocationorshapeofthewiresby"move(m)"also.

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3. TRANSIENTSIMULATIONOFSCHEMATICS
Intheprevioustutorials,youhavedesignedtheschematicsofaCMOSinverteranditssymbolview.Inthis one,youwillsimulatetheschematicsandobserveitscharacteristics. Inordertosimulateacircuit,youneedtodefinetheinputoutput,andthevddgnd.Forthispurpose,wewill generateanothercell. 1. Makeanewcell"invsim"in"EE413"librarywith"schematic"view,usingFile>New>CellViewon thelibrarymanagerwindow. 2. Addthefollowingcomponentsand drawthecircuitinthefigure. Library EE413 PRIMLIB PRIMLIB analogLib analogLib analogLib CellName inverter vdd gnd vdc vpulse cap

3. You have added your design into thisschematicwithafewcomponents.Here,"vdc"willbeusedtoapplyVDDvoltage."vpulse"will beusedforapplyingasquarewavetotheinputoftheinverterand"cap"iscapacitiveload. 4. Nowclickon"vdc"andpress"q".Rememberthat"q"isforreviewingandchangingtheproperties ofthecomponents.Write"5"to"DCVoltage". 5. Change these properties of "vpulse". Remember that "n" stands for "nano", and "u" stands for "micro". Property Voltage1 Voltage2 DelayTime RiseTime FallTime PulseWidth PulsePeriod NewValue 0 5 0 1n 1n 10u 20u
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Vpulseisusedtogeneratepulsedsignalswith2voltagelevels,Voltage1andVoltage2.Thedelay timeatthebeginningofthesimulationisdeterminedbyDelayTime.Alsorisetime,falltime,pulse widthandpulseperiodaredeterminedbytheseproperties. 6. Changethecapacitanceof"cap"to"0.1pF". 7. Thisisthelastviewofthecircuit.Now,presscheckandsavewhichisthefirstmenu(acheck symbolonit)inthetoolboxontheleftofthewindow.

8. Now, click on "Tools>Analog Environment" in order to run analog simulator. 9. Click on Analyses>Choose. "tran" is chosenasthedefaultanalysistime.Write 50u to the "Stop Time". You have programmedthesimulatortosimulatethe transient responseofthe circuit for50u seconds.ClickOK. 10. Now, it is time to determine the nodes thatwillbeobserved.Clickon Outputs>ToBePlotted>SelectonSchematics.Thiswillletyouchoosethenodestobeobserved. Focustheschematicseditorandclickonthewiresattheinputandoutputoftheinverter. Thereare2typesofsignalstobeobservedafterthesimulation:voltageandcurrent.Ifyouclickon wire,youselectthatwire'svoltageastheobservedsignal.Ifyouclickonthenodeliketheinputof theinverter,youselectthecurrentofthatnodeastheobservedsignal.Youseeacircleonthatnode. Youwillworkonvoltagehere. 11. CheckandSavetheschematics. 12. Thereare2waveformviewers,WaveScanandAWD. WaveScanismoreadvancedanddefault waveformviewerforthecurrentCadenceversion. However,wewillpreferAWDsincetheuser interface is simpler and more clear. On the Analog Design Environment dialog, click on Session>Optionsand chooseAWDastheWaveformTool.andclickon"Simulation>Run"to
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startthesimulation.Afterthesimulationiscompleted,awaveformwindowwillbeopened.Donot forgetto"CheckandSave"theschematicsbeforerunningthesimulation. 13. Youshouldseeawaveformsimilartothefigureontheleft.Twodifferentcolorsrepresenttheinput andoutputoftheinverter.Asseen,theinputsignalisinverted,sotheoperationofthecircuitis correct.Inordertoseethesesignalsseparately,clickon"Axes>ToStrip"atwaveformwindow.You shouldseeasimilarwaveformtothefigureontheright.

14. Whichoneisinputandwhichoneisoutput?Well,ifyouclickonthewiresontheschematicsand press"q",youwillseethepropertiesofthem.Youcanseethenamesofthewiresthere. 15. Now,changetheseparametersandsimulateagain. PulseWidthofvpulse PulsePeriodofvpulse Capacitanceofcap Simulationtime 100n 200n 1p 1u

16. Youshouldfindawaveformlikethis. So, we applied a higher frequency input signal and increased the load. This results in larger rise and fall timesattheoutputoftheinverter. 17. Thereare2markersonthewaveform window.Presson"a"or"b"inorder to locate them. You can measure whatever you want using these markers. You are done with the simulation of the inverterschematics.

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4. BASICSOFLAYOUTDRAWING
Tillnow,youdesignedyourcircuitandsimulateditinthevirtualenvironment.Inordertoconvertyour designtorealworld,youneedtodrawthelayoutofit.Layoutdrawingisnotaseasyasdrawingwiresinthe schematics becauseyouneedconsideringthereal(physical)structureofthecircuit.Donotforgetthat, layoutdrawingisquiteimportantanditisajobtitleintheVLSIdesigncenters. This tutorial is quite important. Although all the steps here will be lectured by your assistant, try to understandbyyourselffirstinordertogaintime.

4.1. WhatisLAYOUT?
LayoutisthedrawingsofmasksusedduringthefabricationoftheCMOSchips.Masksarekindsoffilters usedtoshapevariouslayers.EachlayerinCMOSfabrication,likePolysiliconlayerormetallayer,are shapedwithadifferentmask.Consideringourpurposeasthedesigner,wehavetheabilitytochangevery restrictednumberofvariablesduringdesign.Forinstancewecannotchangethethicknessoftheoxidelayer inthegate,butwecanchangethewidthofthegate.Duringlayoutdrawing,wewillconsideronlythewidth andlengthofametallayer,notthethickness.

4.2. CMOSProcessandLayoutDrawingStepbyStep
In this part, we will consider the steps of layout drawingofaCMOSinverterseeninthefigureon the right. Do not forget that, the CMOS process stepsaremuchmorecomplexthantheoneswewill considerinthispart.Weareskippingmanysteps since we do not care much about them as the designer. Ateachstep,thephysicalstructureand thelayoutcorrespondingtothisphysicalstructure aregiven,andthentheprocessisexplained. 4.2.1. Step1ActiveRegionsandWells
Active regions NWELL

Let'sstarttheCMOSprocessflow.Wehaveaptypesubstratewithsinglewelltechnology,whichmeans thatNMOStransistorsareimplementedonptypesubstrate,andPMOStransistors areimplemented on NWELLs. Nwellsarethentypedopedregionsasseeninthefigureabove.Normally,frontsidesofthe wafersareinitiallycoveredwithverythickSiO2layer(orSi3N4layer)excepttheregionswheresomeactive elements,likethetransistors,willbeimplemented. Amaskisusedtoshapetheseopenings,whichare calledasActiveRegions.AndonemaskisusedtoshapetheNwellregion.Sotwolayersaredrawninthe layout.
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4.2.2. Step2Polysilicon
Polysilicon

Nextstepistogrowandshapepolysiliconlayer,whichwillformthegateofthetransistor.Forthispurpose, weneedtodrawonemaskonly,whichiscoloredasred. 4.2.3. Step3N+andP+Diffusion

N+ doping

P+ doping

N+ doping

Inthisstep,n+andp+regionswillbedoped.Dopingisdoneonentirewafersurface.SinceSiO2and PolySilicondonotpassdopands(orimpurities)tothesubstrate,theseregionsarenotdoped.First,amaskis usedtodeterminetheregionstobedopedwithp+impurities.Afterp+doping,therestofthesurfaceis dopedbyn+dopands.Soonlyonemaskisused. Oneimportantpointshouldbestatedhere.Nwellregionsshouldbebiasedtohighpotentialandpsubstrate shouldbebiasedtolowestpotentialinordertominimizetheleakagecurrentonthediodeformedbyNwell andpsubstrate.Forthispurpose,astructurelikethefigureaboveisused,wheretheNwellisbiasedwiththe samepotentialtothep+regionontheleft.Notethat,contacttotheNwellshouldben+inordertodecrease schottkyeffect.Seethep+dopingregionmaskontheright. 4.2.4. Step4Contacts
Contacts

Asthenextstep,theentirewafersurfaceisagaincoveredbyathickoxidelayerinordertopreventthe shortsbetweenthesubstrateandmetallayerdepositedinthenextsteps.Inordertotakeconnectiontothe substrate,oneshouldusecontacts,whichareopeningsintheoxidelayer.Thereare3differentcontactsand wewilllearnthoselateron.Thiscontactisthefirstoneanditconnectsthesubstratetothemetallayer (metallayerisnotshownhere,itwillbegrowninthenextstep).

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Oxidelayerisgrowntothewholewafersurfaceandthenthecontactsareetchedaway.Soonlycontact openingsshouldbemaskedasseenontheright. 4.2.5. Step5MetalDeposition

METAL

Wearealmostdonewiththeprocess.Themetallayerisgrownandshapedinthisstep.Notethat,themetals whereacontactexiststouchestothesubstrate. 4.2.6. FinalView

Thisisit.Theprocessiscompletedandourlayoutisready.Asyousee,layoutissomehowsimilartothe topviewofachip.Makesurethatyouunderstoodeverystephere.Donothesitatetoaskquestions,this tutorialisquiteimportant. Rememberthedefinitionofthelayoutstatedatthebeginningofthetutorial. Itiscombinationofmasks usedduringtheprocessofthechip.Soasthedesigner,yougivetheshapesofthelayersthatyouwant,and theprocessengineerproducesthecorrespondingchipforyou.Asthedesignerpointofview,youdonot reallycareaboutthethicknessofthelayers,butyoucareonlytheshapeofthelayers.Soyouareina2D world.

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5. LAYOUTDRAWINGUSINGCADENCE
In the previous part, layout drawing basics are given. In this tutorial, the layout will be drawn using Cadence.Attheendofthetutorialthedesignwillbecheckedinordertoverifythephysicalstructureofthe drawnlayout.

5.1. DesignRules
Inthislaboratory,XFab0.6m,2Metal2PolyNWELLprocesswillbeused(xc06).Eachtechnologyhas itsownlayoutdrawingdesignrules,andtheyshouldbesatisfiedforsuccessfulproduction. DesignRule Check(DRC)toolsareusedtodeterminewhetherthedesignrulesaresatisfiedornot. Thefollowingpartssummarizestheshortdescriptionsofthelayersfirstly,andthengivesthemostimportant designrules.Thedetailscanbeobtainedfrom\\battal\413\dr_xc06.pdf. 5.1.1. Layers Thereareanumberoflayerstobeusedinthelayoutview.Mostoftheselayersandabbreviatednamesare summarizedbelow:

NWELLrepresentsnwell DIFFrepresents"active"layer,activelayersareregionsonwhichtransistorscanbegrown POLY1representsthegatepolylayer,whichisusedforconstructinggatesoftransistors,itisalso usedasaconductor PIMPrepresentsp+dopingregion NIMPrepresentsn+dopingregion CONT representsopeningsinoxide,whichareusedtogetcontactsbetweendifferentlayerslike activemetal,polymetal MET1representsthefirstmetallayerwhichisthemainconductingpathforrouting MET2representsthesecondmetallayerwhichisthealternativeconductingpathforrouting.Since therearetwometallayers,andtheyareisolatedwithoxide,twodifferentconductionpathsrouted withdifferentmetalscancrossovereachother. VIA represents an opening in oxide between metal1 and metal2, hence connecting metal1 and metal2.

5.1.2. DesignRulesOverview Thetablebelowshowsthedesignrulesforvariouslayers.Minimumwidthshowstheminimumproducible widthofthelayers.Spacingandnotchsimilarlyshowtheminimumspacingandnotchspacesofthelayers.

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Layer NWELL DIFF POLY1 CONT MET1 MET2 VIA

Min.Width(m) 4 0.6 (1.4inthe transistor) 0.6 0.6(fixed) 0.9 0.9 0.7(fixed)

Spacing(m) 4.8 1.2 0.8 0.6 0.8 0.8 0.6

Notch(m) 4.8 1.2 0.8

Minimum Spacing Minimum Width

0.8 0.8

Notch

Furtherdesignrulesarestatedbelowwhicharerequiredfordrawingatransistor.Atthemoment,youmay notunderstandalloftheruleshere.Youwillgetalloftheseruleswhiledrawingthelayoutoftheinverter. 1. MinimumGATElength0.6u 2. MinimumPOLY1extensionofGATE0.6u 3. MinimumACTIVEPOLY1spacing(sametransistor)0.3u 4. MinimumGATEwidth1.4u 5. MinimumPPLUSextensionofACTIVE0.4u 6. MinimumNTUBextensionofACTIVE1.8u 7. MinimumDIFFUSIONCONTACTtoGATEspacing0.5u 8. MinimumACTIVEextensionofDIFFUSIONCONTACT0.4u 9. MinimumBULKCONTACTtoPPLUSspacing0.8u 10. MinimumMET1extensionofCONTACT0.3u 11. CONTACTcrossingVIA isnotallowed 12. VIA crossing POLY1 edgeisnotallowed Thefigureontherightillustrates thedesignrules.Thenumberin the parenthesis refers to the designruleabove. You may not understand the meaning of this figure at the moment.Donotworry,youwill understand while going through thestepsinthenextpart. Come back to this figure after you have completed the whole tutorial.
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0.3 (3) 1.5 1.4 (4) 0.3 (10) 1.2 0.5 (7) 0.6

PIMP

2.2

1.8 (6) 0.4 (8)

0.6 (2)
CONT

0.6 (1)

MET1 DIFF

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5.2. LayoutoftheInverter
Nowwecanstartdrawingthelayoutoftheinverter.OpenLibraryManagerbyTools>LibraryManageron icfbwindow. 1. Firstcreateanewcellviewfortheinverter.SelectFile>New>CellView,andselect"Virtuoso"as thetool,alsomakesurethatlibrarynameis"EE413"andcellnameis"inverter".ClickOK. 2. Twonewwindowswillappear.Oneisnamedas"LSW"andtheotheroneisthelayoutwindow. Firstofall,focusonlayouteditorandclickonOptions>Display.MakesurethatXSnapSpacing andYSnapSpacingareboth0.05.ThenOptions>LayoutEditor,anduncheckGravityon. 3. LSWisapalettefromwhichyoucanselectthemasklayeryouwanttodrawwith.Atthemomentit liststhelayersdefinedinTECH_XC06process.Althoughtherearelotsoflayerslisted,onlysome of them will be used. Some of the layers have two different versions like POLY1 drw and POLY1pin.drwstandsfordrawingandpinstandsforpin.Whiledrawingthelayout,only drwlayersshouldbeused.Thosepinlayersandotherthingsaregeneratedautomaticallybythe extractiontools. 4. Asthefirsttask,wewilldrawasimpletransistor.ClickCreate>Rectangle(r). 5. Nowyoushouldselectthelayeryouwanttodrawwith.Select"DIFFdrw"fromLSW. 6. Drawarectangle3.6mwideand1.4mtall,forthedimensionsuse"dX,dY"displaysatthetopof thewindow.Inordertodrawtherectangleyoushouldfirstclicktothetopleftcornerandthenclick tothebottomrightcorner(justtwoclicks,nodrag). 7. Inordertomakesurethatyouhavedrawnintherightsize,usethe"ruler".ClickMisc>Ruler(k), andinordertofocusonthecircuityouhavedrawnpress"f"(Fitcommand).Clickonthetopleft cornerandmeasurethewidthandthenlengthoftheactive.Youshouldread3.6mhorizontallyand 1.4 m vertically. If the rectangle is not at the correct size, you should "Stretch" it. Click Edit>Stretch(s).Movethemouseontheobjectsothatthesideyouwanttostretchishighlighted, thenyoucanclickandmovethemouseforthenewsize,clickagaintofixthemovingslide. Youmaygetdifficultyifyouareusingskeyinsteadofthemenu.Dosometrials. 8. Nowselectthelayer"POLY1dg"fromLSW. 9. Similarlydrawarectangleof0.6mwideand2.6mtallrightatthecenteroftheactiveregion.Use Edit>Move("m")orEdit>Stretch("s")tofixthepositionandsizeofthepolyrectangle.Thecorrect figuremustlooklikethefollowing:

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10. Inordertoobtainelectricalconnectionwewillplacetwocontactstothediffusionarea:onefordrain andoneforthesource.Toformsuchacontact,youmustdrawarectangleof"MET1drw"anda smallerrectangleof"CONTdrw"insidethemetal.Howevertheselayerscannotbearbitrarilyplaced asexplainedinthedesignrulessectionbefore.Draw2MET1rectangleswith1.2mwidth,and2 CONTrectangles0.6mwidth.Thefollowingfigureshowstheresultingdrawing.

11. Nowwehavebuiltasimpletransistor,howeverdidnotspecifywhetheritisnMOSorpMOS.Foran nMOStransistoractiveareamustbedopedwithn+,whileforapMOStransistoractiveareamustbe dopedwithp+.Donotforgetthatthisisannwellprocess,sopMOStransistorsareplacedinnwell, whilenMOStransistorsaredirectlybuiltonthepsubstrate.PIMPandNIMPlayerswillbeusedfor p+andn+doping. 12. Another pointis thebulkconnections. Asyouknow,transistors are4terminal devices. The4 th terminalofannMOStransistoristhepsubstrate,whilethatofpMOStransistoristhenwell.Since allthewaferis(henceallthetransistorsare)builtonthesamesubstrate,allnMOStransistorsmust havethesamebulkterminal,whichisthemostnegativevoltagelevelinthecircuit:ground,soyou
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should consider threshold variation effects for transistors whose most negative terminals are connectedtovoltagesotherthanground.Similarlyallthetransistorsinthesamenwellhaveone common bulk terminal (usually VDD). However, one can place isolated nwells and can have different bulk voltages for isolated pMOS transistors. Although this is possible, it is usually impracticaltoplaceisolatedwells,sincetheyshouldbeplacedapartfromeachother. 13. Wewillalsoplaceoneothercontactforthebulk.InordertobypassSchottkydiodeeffects(metalto silicondirectconnection),oneshoulddopethesilicontoguaranteearesistivecontact(alsoconsider latchup).ForannMOStransistor,bulkconnectionismadetothepsubstrate,soweshoulddopethe activelayerwithp+foraresistivecontact;similarlyforapMOStransistor,bulkconnectionismade tothenwell,soweshoulddopetheactivelayerbelowthecontactwithn+. ThefigurebelowdisplaysannMOStransistorwithbulkconnectionontheleft:

PIMP

NIMP

ThefigurebelowdisplaysapMOStransistorwithbulkconnectionontheleft,andalsohasannwell around:

NIMP

PIMP

NWELL

14. Nowwehavetwotransistors,whatisleftisconnectingthemtogether.Weneedtoroutepowerlines "VDD"and"ground",thenconnecttheinput"A"andoutput"Q".Theoveralllayoutshouldlooklike thefollowing:

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15. Thisprocessisspecifiedasdoublemetal,doublepoly,hencetherearetwodifferentmetalsandone polylayerthatcanbeusedasconductingpaths(thesecondpolyisusedforbuildingcapacitors).The conventionfortwometalprocessesareroutingpowerlines(VDD,gnd)withthefirstmetal,and routingsignalpaths(likeinput"A",andoutput"Q")withsecondmetal.Hence,wewillmakemetal2 contactsfor"A"and"Q".Inordertoconnectmetal1tometal2,oneshoulduse"via"layer;inorderto connectpoly1tometal2firstmakeacontactfrompoly1tometal1andthenmakea"via"connection frommetal1tometal2. ConnectionsbetweenMET1andMET2,andbetweenPOLY1andMET1arefrequentlyused,soa simplymethodisusedincadence.SelectCreate>Contact(o). Thereareanumberofcontacttypes: VIA_C:ConnectionbetweenMET1andMET2. P1_C :ConnectionbetweenPOLY1andMET1. ND_C :Connectionbetweenn+dopedactiveregionandMET1. PD_C :Connectionbetweenp+dopedactiveregionandMET1. SoyoumayuseVIA_Cfortheoutputterminal,andP1_CandVIA_Cfortheinputterminal.Still, youmaydrawtheseconnectionbyyourselvesasseeninthefollowingfigures.VIA_Cisseenonthe left,andP1_Cisseenontheright.Notethat,youmayneedtopressShiftFforshowingtheinternal structureofthecontacts(CtrlFisforhiding).

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Usingtheinformationabove,takecontacttometal2forboththeinputandtheoutput.Thefinal layoutwilllooklikethefollowing.

16. Asyoumayconsider,wehavenotassignednamesforthepowerandsignallines(rememberportsin the schematic) yet. In this step we will create pins for "vdd!, gnd!, A, Q" (the "!" signs are necessary).ClickCreate>Pin.Thefollowingwindowpopsup:

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CheckDisplaypinnamecheckboxonthewindow.Write"vdd!"in"TerminalName"field,select "metal1_T"from"PinType",checkonly"left,right"in"AccessDirection"list.MakesurethatI/O Typeisinput/output. Whenyoumovethemouseoverthelayout,youwillnoticearectangle movingwithyou.Placethispinontothemetallineatthetopofthelayout(zoominwiththeright mousebutton,inordertoplacethatexactly).Similarlyplacea"gnd!"pinonthemetallineatthe bottom.Nowchangethe"PinType"to"metal2_T"andcreatepinsfor"A"and"Q".Donotforgetto changeI/OTypetoinputandoutputwhenplacingAandQrespectively.Whenyouaredone"Hide" thepopupwindow. 17. Nowwehavetocheckwhetherwehaveviolatedanydesignrulesornot.Thisstepiscalledasthe DRCandisveryimportant.DRCerrorsmustbecorrectedbeforethelayoutiscompleted.Inorderto makeDRCclickVerify>DRC.Anewwindowpopsup.Click"OK".Icfbwindowwilldisplaythe DRCsteps,andfinallyreporttheerrorsfound.IfthelayoutgetsalongwithallDRCrules,you shouldseethemessage"Totalerrorsfound:0". 18. SelectVerify>Markers>Deleteall,andclick"OK",thiswillclearallthemarkersthatmayresult fromerrorsyouhavemade.Nowwewillintroduceanerrorandthenlearnhowtodetectit.Stretch ("s")thegatepolyrightabovethepMOStransistor,sothatthedistancebetweentheactiveareaand theendofthepolyareonly0.4u.(DRCstatesthatthisdistancemustbeatleast0.6u,andstatesthis ruleas"MinimumPOLY1extensionofGATE=0.6um".NowclickVerify>DRCandclick"OK". IcfbwilldisplaythatyouhaveviolatedthisrulebydisplayingMinimumPOLY1extensionbeyond GATE=0.6. 19. Inthisexamplethereisonlyoneerror,andweknowwheretheerroris.Usuallythereareanumber oferrorsandtheyarehardtolocate.Nowwewilllearnhowtolocateerrors.ClickVerify>Markers >Find.Anewwindowpopsup,checkintheboxfor"ZoomtoMarkers",thenclick"Next".Correct thedistancebetweenactiveandtopofthepolyextension(0.6).NowclickVerify>Markers>Delete all.CarryoutanewDRCandmakesurethattherearenoerrorsinthelayout. 20. Iftherearenoerrors,clickDesign>Save. Youhavecompletedyourfirstlayout...Afewmorestepsarestillremaining. Inordertousethis layoutinthesimulations,wehaveto"extract"itandforman"extracted"view. 21. ClickVerify>Extract. 22. ClickOK.CIWmustreportthat"Totalerrorsfound:0".
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23. Nowclosethelayoutview,andopen"extracted"viewoftheinverter.Press"Shift"and"f"together ifthetransistorsarenotseen.Theviewwilllookliketheoneontheright.

Thisistheendofthetutorial. So,youhavedrawnyourfirstinverterlayout,carriedouttheDRC,and generatedextractedview.

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6. LAYOUTVERSUSSCHEMATICCHECK(LVS)
Tillnow,youdesignedtheschematicsandlayoutofaCMOSinverter.However,youdidnotcheck yetwhetherthedrawnlayoutissameastheschematics.Inordertocheckwhethertheschematicsandthe layoutaresame,aspecialcheckmechanismisusedcalledasLVS.Whatitdoesistocomparethenetlistsof theschematicviewandtheextractedview. 1. Open the extracted view of the inverter. 2. ClickVerify>LVS.Thewindow ontherightwillpopup: 3. Make sure that schematic and extractedarecheckedforCreate Netlist part. Fill in the schematic and extracted Library,CellandViewas inthefigure. 4. ClickRun. 5. Afterashortwhile,youwillhave a message box stating that the LVS check is completed. Click OKinthemessagebox. 6. In order to display the results, click on Output in the LVS window. 7. Nowletsconsiderourcase.The transistorsyoudrewinthelayout have1.4mwidth,however,the ones in the schematics have probably different widths. So thiswillbefoundbyLVScheck andgivenasawarning.ThefollowingpartisthepossibleLVSoutputthatyouwillhave. Some explanationsareaddedwithboldcharacters.
@(#)$CDS: LVS version 4.4.5 04/20/2000 16:37 (cds11182) $ Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Net-list summary for /home/vlsi/tepegoz/EE413/LVS/layout/netlist count 4 nets 4 terminals 1 nmos4 1 pmos4

This part is the summary of the extracted view. There are 4 nets, 4 terminals (A,Q,vdd,gnd), and 2 transistors.
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1 1

nmos4 pmos4

Thispartisthesummaryoftheschematicssimilartotheextractedviewcase.
Terminal correspondence points 1 A 2 Q 3 gnd! 4 vdd! The net-lists match logically but have mismatched parameters.

ThislinesummarizestheresultsoftheLVScheck.Itstatesthatschematicandextractedviewsaresame circuits,howeverthereareasomecomponentswithmismatchedparameters.
layout schematic instances 0 0 0 0 2 2 0 0 2 2 2 2 0 0 0 4 4 nets 0 0 0 4 4

un-matched rewired size errors pruned active total un-matched merged pruned active total un-matched matched but different type total

terminals 0 0 0 4 0 4

ThispartisthedetailedinformationabouttheLVScheck. Thefirstpartisabouttheinstances ofthe componentslikethetransistors,capacitors,orresistors.Thereportsaysthatthereare2sizeerrors.Ifthe schematicandthelayoutweredifferent,therewouldbesomeunmatchedcomponentsalso.

Probe files from /home/vlsi/tepegoz/EE413/LVS/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: I /I1 ? Bad width : 2e-06 in layout, 1e-05 in schematic I /I0 ? Bad width : 2e-06 in layout, 1e-05 in schematic -

ThispartisthefurtherinformationabouttheLVScheck.Last2linesstatethatinstanceI1has2mwidth inthelayout,but10mwidthintheschematics.SameforI0also.Now,goandcheckwhatisI0andI1in theschematicview.

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prunedev.out: audit.out: I /+1 ? Bad width : 2e-06 in layout, 1e-05 in schematic I /+0 ? Bad width : 2e-06 in layout, 1e-05 in schematic -

Asthelast,thispartisthefurtherinformationaboutlayoutview. 8. Inthepreviousreport,thereare2layoutand2schematicwarnings,whichareduetomismatchinthe transistordimensions(ifyougetmorethanthis,youshouldgobacktoyourdesign,andcorrectthe problems).Inordertocorrectthismismatches,youshouldgobacktotheschematics,andmakethe widthofthetransistor1.4u.Afterthis,checkandsavethedesign,andstarttheLVSagain.Ifthere isnofurtherwarningorerror,youshouldgetareportverysimilartothis:

@(#)$CDS: LVS version 5.0.0 05/30/2003 19:44 (cds11939) $ Like matching is enabled. Using terminal names as correspondence points. Net-list summary for /home_new/vlsi/tepegoz/CADENCE/XFab/ee413_xc06m3/LVS/layout/netlist count 4 nets 4 terminals 1 nmos4 1 pmos4 Net-list summary /home_new/vlsi/tepegoz/CADENCE/XFab/ee413_xc06m3/LVS/schematic/netlist count 4 nets 4 terminals 1 nmos4 1 pmos4 Terminal correspondence points 1 A 2 Q 3 gnd! 4 vdd! The net-lists match. layout schematic instances 0 0 0 0 0 0 0 0 2 2 2 2 0 0 0 4 4 nets 0 0 0 4 4 for

un-matched rewired size errors pruned active total un-matched merged pruned active total un-matched matched but different type total

terminals 0 0 0 4 0 4

Probe files from /home_new/vlsi/tepegoz/CADENCE/XFab/ee413_xc06m3/LVS/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: Lastupdatedon20091028

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audit.out: Probe files from /home_new/vlsi/tepegoz/CADENCE/XFab/ee413_xc06m3/LVS/layout devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out:

9. Now, you will generate another view, called analog_extracted view, which contains additional informationtoextractedviewforsimulations. Forthispurpose,clickon BuildAnalog onLVS window.MakesurethatIncludeAllisselectedforExtractedParasiticsoption,andthenclickOK. Thiswillgenerateanalog_extractedviewtotheinvertercell.Youmaygoandcheckthisview.

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7. SIMULATIONOFTHEINVERTERLAYOUT
Inthistutorial,wewillsimulatethelayoutoftheinverter,andseethedifferences.Intheprevioustutorials, youhadsimulatedtheschematicsoftheinverter.Whatyouwilldohereisverysimilartothatexceptthat youwillsimulatenottheschematics,butthelayoutofthecircuit.Alsointheprevioustutorials,youhad generatedtheanalog_extractedview.Extractionactuallymeansgeneratingnetlistfromthelayout.During theextraction,manyparasiticsandmorerealisticparameterscanbeused.Forinstance,thecapacitanceof themetallinescrossingoveranothercanbeextracted,andaddedtotheextractedview.So,extractedview simulationsaremorerealisticthanschematicsimulations. Wewilluseinvsimgeneratedfortheschematicsimulations. 1. Opentheschematicofinvsim. 2. Arrancevpulsesuchthatitgivesasquarewavebetween0and5V,andwithfrequencyof5Mhz. Usealoadof1pF. 3. ClickTools>AnalogEnvironment. 4. ClickSetup>Environment. 5. ThereisalistnamedSwitchViewList,thislistdeterminestheorderofviewsAnalogEnvironment willsearchfor.Priorityisfromlefttoright,sotypeanalog_extractedatthefirstplace.Thenclick OK. 6. ClickAnalyses>Choose,andselect"tran",enter"0.5u"forthesimulationtime. 7. ClickOutput>TobePlotted>SelectonSchematic. 8. Clickontheinputandoutputwiresoftheinverter. 9. Istheresultwhatyouexpect? 10. Whydoyouthinkthatlayoutsimulationisimportant?

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8. ASAMPLEDESIGNFLOW
Inthepreviousparts,youcompletedasimpletransistorleveldesign.Checkthefollowingdesignflow,and trytounderstandwhichpartsyouhavecompletedinthepreviouschapters.
START

Design of the circuit on paper

Draw Schematics

Simulate schematics

Good? Y

Draw Layout Find the errors and correct them

Do Design Rule Check (DRC)

Good? Y

Do Extraction and LVS

Good? Y

Simulate layout

Good? Y END

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