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APPLIED PHYSICS LETTERS 86, 193504 2005

Leakage currents of SiO2 lms grown on CoSi2 lines and disks

S. B. Herner and C. J. Petti
Matrix Semiconductor, Santa Clara, California 95054

Received 23 July 2004; accepted 17 March 2005; published online 4 May 2005 Silicon dioxide lms were grown by low-temperature anneal in O2 on substrates of CoSi2 lines or disks. The leakage current through SiO2 lms grown on CoSi2 lines have a strong dependence on the O2 anneal temperature, while those grown on CoSi2 disks have a weak dependence on anneal temperature. This difference is due to the shape of the oxide grown on the CoSi2. Oxide lms were found to grow in a convex shape on CoSi2 disks, being much thicker in the middle of the disk than on the edge. Oxide lms grown on CoSi2 lines had relatively uniform thickness across the width of the line. 2005 American Institute of Physics. DOI: 10.1063/1.1923751 pillar-shaped with a circular cross section, with CoSi2 as an ohmic contact on top Fig. 1 b . A high-voltage pulse breaks down the antifuse on top of the CoSi2 and connects the diode to the electrode. p-i-n diodes have lower reverse currents compared to Schottky diodes, and are thus more attractive for large memory arrays.4 p-i-n diode-based cell fabrication is now discussed. The cells are fabricated on 200 mm silicon wafers. After thick oxide deposition, the bottom cell electrode is formed by etching 170 nm thick tungsten lines with a 20 nm thick TiN adhesion layer underneath . The tungsten lines are patterned using standard lithographic techniques, resulting in 150 nm-wide lines with 170 nm spaces in between. Oxide is deposited between and on top of the etched tungsten lines to serve as an insulator. Chemomechanical polishing removes the oxide from the top of the tungsten lines and planarizes the wafer surface. A 20 nm thick TiN diffusion barrier is then deposited on top of the exposed tungsten lines, followed by 430 nm thick low pressure chemical vapor deposition CVD silicon doped in situ. The silicon is doped with boron during initial deposition. The boron source gas is then discontinued, depositing undoped silicon on top of the doped silicon, forming a p+/undoped stack. The Si/ TiN is etched into individual pillars. The gaps in between the Si/ TiN pillars are lled with HDP CVD oxide and chemomechanically polished until the tops of the pillars are exposed, and the wafer surface is again planarized. An n+-doped ohmic contact to the undoped region at the top of the Si/ TiN pillar is formed by phosphorus ion implantation, completing diode formation. Cobalt silicide CoSi2 is formed on top of the pillar, contacting the n+ Si, using a selective process. The nal CoSi2 lm is 30 nm

One-time programmable OTP memory has recently attracted interest as a replacement for mask-based read only memory MROM . OTP memory has an inherent advantage to MROM due to its ability to be programmed in the eld instead of during fabrication, giving the user exibility in determining content. Dielectric antifuse lms, in which a high voltage pulse deliberately breaks down the lm, have attracted interest for their application in OTP memory cells.14 The mechanism of memory storage in these cells is the break down of the antifuse lm. After breakdown programmed , a higher current ows through the cell compared to before breakdown unprogrammed . For OTP memory cells, it is desirable for the antifuse lm to have both a long lifetime at a relative low read voltage, and for it to break down uniformly for a given higher programming voltage. Silicon dioxide can satisfy both requirements. Large arrays of OTP cells can be made by coupling the oxide antifuse with a diode. In large arrays, a few cells are programmed in forward bias while the rest are held at a reverse bias, and so a low leakage in reverse bias is crucial to minimize power loss. The forward current for an unprogrammed OTP cell based on an oxide antifuse is largely determined by the thickness of the oxide antifuse lm. Thicker oxide lms have lower leakage currents compared to thin lms, but require a higher programming voltage to rupture. Determining the relationships between oxide thickness, leakage current, and programming voltage is an important part of OTP memory cell implementation. Recently, an OTP memory cell based on a SiO2 antifuse and Schottky diode has been described. This memory cell and its fabrication are described in detail in Ref. 3, and are briey summarized here. The cell consists of a rst polysilicon/ CoSi2 line with a thin SiO2 antifuse lm grown directly on the CoSi2 line, and a second line of n-type polysilicon in contact with the antifuse. Cobalt silicide is grown on top of the second line. The second line is deposited on top of the rst line, and is patterned orthogonal to the rst Fig. 1 a . The cell is programmed when biasing voltage is pulsed through the rst line to break down the SiO2 antifuse, connecting n Si to CoSi2, forming a Schottky diode. The Schottky diode described has a relatively high leakage in reverse bias, which results in high-power consumption when programming many cells simultaneously. A second OTP memory cell based on SiO2 antifuse grown on CoSi2 has been developed. This cell is a vertical polysilicon p-i-n diode with an antifuse. The p-i-n diode is

FIG. 1. Schematic of the memory cells a Schottky diode-based with SiO2 antifuse grown on a CoSi2 line; and b p-i-n diode-based with SiO2 antifuse grown on a CoSi2 disk.

0003-6951/2005/86 19 /193504/3/$22.50 86, 193504-1 2005 American Institute of Physics Downloaded 04 May 2005 to 65.215.209.79. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp

193504-2

S. B. Herner and C. J. Petti

Appl. Phys. Lett. 86, 193504 2005

FIG. 2. Leakage current at +2 V through either cell before SiO2 antifuse is broken down. Antifuses were grown by rapid thermal oxidation in 5 L of O2 for 20 s at the temperatures indicated.

thick. Antifuse lm is grown on top of the CoSi2 by annealing in 5 L of O2 99.99999% purity at a temperature between 550 and 750 C for 20 s. A second layer of tungsten is fabricated on top of the antifuses. These tungsten lines are the top cell electrodes and are orthogonal to the bottom cell electrodes. Insulating SiO2 lm is deposited on top of and between the tungsten lines, completing fabrication of the memory cell and electrodes. Vias formed by oxide etch and metal ll connect the memory cell to an aluminum top metal layer, allowing connection to a Agilent 4156C semiconductor parameter analyzer. The forward leakage current at +2 V before rupture of the SiO2 antifuse is measured by applying voltage to the bottom cell electrode while the topmost electrode is held at ground for both the Schottky diode-based and p-i-n diodebased cells. The measured leakage current density for various oxide antifuse growth temperatures anneal time is held constant at 20 s for both devices is shown in Fig. 2. While an offset between the two curves is expected based on device differences, the slopes of the two curves are expected to be similar since they are dependent on the thickness of the oxide. However, the slopes are much different. Morphology of the oxide lms on both substrate was investigated by cross-sectional transmission electron microscopy TEM . Multiple cells were imaged, and representative images are shown in Fig. 3. The oxide lm grows with a relatively uniform thickness across the width of the CoSi2 wire Fig. 3 a . The oxide grown on the CoSi2 disk has a surprising shape: It is much thicker in the center of the disk than on the edges Fig. 3 b . By proling the CoSi2 disk before and after oxide growth, the shape of the oxide lm observed in TEM cross section is conrmed in three dimen-

FIG. 4. Atomic force microscope micrographs of three pillar surfaces a after CoSi2 formation but before oxide growth; and b after oxide growth on top of the CoSi2. The oxide has been grown by anneal in at 750 C / 120 s in O2. The upper image in each set is the two-dimensional map of the surface, and the lower image is the topography of the indicator line in the upper image. The arrow markers are coincident locations on the wafer in both images.

FIG. 3. Cross-sectional TEM micrograph detail bright eld , of the SiO2 antifuse lm on a CoSi2 line cross section from Schottky diode-based cell, and b CoSi2 disk from p-i-n diode-based cell. Downloaded 04 May 2005 to 65.215.209.79. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp

sions. The oxide lm shape on CoSi2 disks was further characterized by atomic force microscopy AFM on wafers during fabrication. Figure 4 a is an AFM image of the surface topography of the pillar after CoSi2 formation, but before oxide growth. The upper image is the two-dimensional map of the surface with gray scale for topography, while the lower image is the one dimensional topography of the line in the upper image. The arrow markers show coincident locations in both images. The CoSi2 disks have a diameter ranging from 78 to 120 nm. The disks are concave and slightly recessed below the plane of the surrounding deposited oxide as shown by the line trace. The center of the concave disks is 1.5 to 2.5 nm below the rim. Figure 4 b is a second AFM image from a different wafer, showing the surface of the disks after oxidation at 750 C / 120 s in O2. The centers of the disks protrude above the edge of the disks. The AFM images conrm the shape of the oxide observed in TEM. This shape explains the different leakage current slopes shown in Fig. 2. The oxide is growing more slowly at the edge of the CoSi2 disk, belying a weak dependence of the leakage current on oxide growth temperature. The oxide grown on CoSi2 lines is uniformly thicker, and the leakage current therefore has a stronger dependence on growth temperature. Marker experiments on the oxidation of CoSi2 have shown that the silicide dissociates and liberated Si reacts

193504-3

S. B. Herner and C. J. Petti

Appl. Phys. Lett. 86, 193504 2005

with O2 to form SiO2. Cobalt atoms then diffuse from the SiO2 / CoSi2 interface to the CoSi2 / Si interface.5 The slower oxidation rate at the edges of the CoSi2 disk may have contributed to the bowed prole of the silicide shown in Fig. 3 b , with more Co being transported to the middle of the disk compared to the edge. The slower oxide growth at the edge of the CoSi2 disks is consistent with stress retarded oxidation. A similar phenomenon has been observed at trench corners in single-crystal silicon that has been thermally oxidized.6,7 We have characterized the morphology and leakage currents of SiO2 lms grown on CoSi2 lines and disks. The leakage currents of oxide lms grown on CoSi2 lines have a stronger dependence on anneal temperature compared to lms grown on CoSi2 disks. Oxide lms grown on CoSi2 disks have a convex shape, with the lms being thinner at the edges of the disk. Oxide lms grown on CoSi2 lines have a more uniform thickness across the width of the line. These

different oxide morphologies are the cause of the different leakage current dependencies on anneal temperature.
1

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