Beruflich Dokumente
Kultur Dokumente
w w w . a r m . c o m
Features
High-efficiency Java bytecode execution, >1000 Caffeine Marks @ 200MHz Ultra-low Java system cost Low power consumption for battery operated wireless embedded devices Single chip MCU, DSP and Java solution No duplication of on-chip memory, bussing, debug or trace resources ARM support code causes no increase in VM size Java JIT compiler performance without the disadvantages Integrated into a number of ARM CPU cores Complete development kit including documentation and reference Run existing OS and middleware Supported by leading OS Supports leading Java run-times Rapid ASIC or ASSP integration with reduced time-to-market
ARM has integrated Jazelle technology into three cores: the ARM1026EJ-S core, the ARM926EJ-S core and the ARM7EJ core, to provide a fully compatible roadmap for Jazelle technologyenabled products.
The ARM1026EJ-S macrocell is a fully synthesizable processor featuring extensive 64-bit internal bussing combined with configurable instruction and data caches, configurable tightly coupled memories (TCM), support for parity protection on SRAM arrays, memory management and protection units (MMU and MPU). It also includes a vector interrupt controller interface, advanced vector floating point support and dual 64/32-bit configurable AMBA AHB system interfaces. The ARM1026EJ-S core implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. The ARM926EJ-S soft macrocell is a fully
synthesizable, high-performance 32-bit RISC processor comprising a Jazelle technologyenhanced processor core, instruction and data caches, tightly coupled memory (TCM) interfaces, memory management unit (MMU), and separate instruction and data AMBA AHB bus interfaces. The size of the instruction and data cache, and instruction and data TCMs can all be independently selected, providing complete flexibility and enabling the ARM926EJ-S solution to be tailored to specific application needs. The ARM7EJ solution is a compact CPU without cache memory, specifically designed for applications demanding the lowest power consumption and where absolute performance is less critical. It has a memory interface identical to that of the ARM7TDMI-S, and features an enhanced multiplier design for improved DSP performance. Ideal for Java-enabled voice handsets, intelligent appliances and home automation applications.
Real-Time Performance
Applications like home gateway and phone solutions demand excellent real-time performance from a processor to run the network protocol software and middleware. The Jazelle architecture extensions enable the processor to maintain fast interrupt response and provide real-time performance.
www.arm.com info@arm.com
Product Roadmap
The Jazelle Support Code provides a simple, progressive method for integrating Jazelle technology into any system. The VTK support code achieves excellent levels of Java performance with non-Jazelle cores by using software Java acceleration. When a Jazelle enabled core with hardware Java acceleration is targeted, then the JTEK version of the support code is used to enable maximum Java performance. This permits a phased approach where by existing designs can be transferred to the full benefits of Jazelle technology.
Java Application
Remote Native Network Graphics Methods Methods
Native Application
processor, together with a new Java state. When presented with Java bytecode, the Jazelle Support Code switches the processor into Java state using a dedicated branch instruction. In Java state, the processor reassigns several ARM registers to accommodate Jazelle machine state and Java operands ensuring compatibility with existing
Native OS
ETM10C Interface
ARM1026EJ-S core
ARM1026EJ-S
The Jazelle Support Code, which will only be available to Sun licensees, permits the virtual machine to access the full benefits of Jazelle technology by replacing the interpreter and invoker methods within the VM. The support code is highly optimized for both speed and size and greatly simplifies the task of porting a virtual machine to the Jazelle platform. The Jazelle Technology Enabling Kit (JTEK) comprises all the necessary support code source, documentation and tools that are required to integrate Jazelle technology into a virtual machine and operating system. JTEK is available for CLDC and CDC, and can be ported to all popular OS. ARM processors traditionally support two instruction sets; ARM state, with 32-bit instructions and Thumb state which compresses the most commonly used instructions into 16-bit format. The Jazelle technology extends this concept by adding a third instruction set, Java
operating systems, interrupt handlers and exception code. Up to four stack elements are maintained in ARM registers to reduce memory access to a minimum; this is an important contributor to the excellent performance of the processor when executing a Java application. Stack spill and underflow is handled automatically by the hardware. Minimum interrupt latency is maintained across both ARM state and Java state. An interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. Since bytecode execution can be restarted, no special provision has to be made for handling interrupts while executing bytecode whether in hardware or software.
VFP10 Interface
VIC Interface
ETM9 Interface
ARM9EJ-S core
ARM926EJ-S
Coprocessor Interface
ETM Interface
Coprocessor Interface
ARM7EJ-S
Bus Interface Unit
The ADK provides a generic, stand-alone environment to enable the rapid creation of AMBAbased components and System-on-Chip (SoC) designs. Containing a rich set of basic components for the interconnect, peripherals and verification of an SoC, and several example system designs, the ADK reduces time-to-market by providing the common foundations for product design based upon the AMBA interface. RealView Developer Suite The ARM RealView Developer Suite provides a fully integrated software solution with leading edge tools for creating efficient software to run on any
ARM, ARM Powered, StrongARM, Thumb, Multi-ICE, PrimeCell, ARMulator, RealView, Move, Jazelle and ARM7TDMI are registered trademarks of ARM Limited. ARM7TDMI-S, ARM7EJ, ARM720T, ARM740T, ARM9TDMI, ARM920T, ARM922T, ARM940T, ARM9E, ARM926EJ-S, ARM946E-S, ARM966E-S, ARM1020E, ARM1022EJ-S, EmbeddedICE, EmbeddedICE-RT, AMBA, MultiTrace, ModelGen, ARM Developer Suite, ETM, ETM7, ETM9, ETM10, Embedded Trace Macrocell, PrimeXsys and JTEK are trademarks of ARM Limited. All other brand names or product names are the property of their respective holders. "ARM" is used to represent ARM holdings plc (LSE: ARM and NASDAQ: ARMHY); its operating company ARM Limited and the regional subsidiaries ARM, INC.; ARM KK; ARM Korea Ltd. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. All warranties implied or expressed, including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded. This document is intended only to provide information to the reader about the product. To the extent permitted by local laws ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information.
www.arm.com
info@arm.com
Jazelle Technology | ARM DOI 0114-5/03.04(1)