CS1251 AIM

COMPUTER ARCHITECTURE

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To discuss the basic structure of a digital computer and to study in detail the organization of the Control unit, the Arithmetic and Logical unit, the Memory unit and the I/O unit. OBJECTIVES To have a thorough understanding of the basic structure and operation of a digital computer. To discuss in detail the operation of the arithmetic unit including the algorithms & implementation of fixedpoint and floating-point addition, subtraction, multiplication & division. To study in detail the different types of control and the concept of pipelining. To study the hierarchical memory system including cache memories and virtual memory. To study the different ways of communicating with I/O devices and standard I/O interfaces. UNIT I BASIC STRUCTURE OF COMPUTERS 10

Functional units- Basic Operational Concepts, Bus Structures, Software Performance Memory locations & addresses Memory operations Instruction and instruction sequencing addressing modes assembly language Basic I/O operations stacks and queues. UNIT II ARITHMETIC 8

Addition and subtraction of signed numbers Design of fast adders multiplication of positive numbers- signed operand multiplication and fast multiplication Integer division floating point numbers and operations. UNIT III BASIC PROCESSING UNIT 9

Fundamental concepts Execution of a complete Instruction Multiple bus organization Hardwired control microprogrammed control. Pipelining Basic concepts data hazards instruction hazards influence on Instruction sets Data path and control consideration Superscalar operation. UNIT IV MEMORY SYSTEM 9

Basic concepts semiconductor RAMs, ROMs Speed, size and cost cache memories - Performance consideration Virtual memory- Memory Management requirements Secondary storage. UNIT-V I/O ORGANIZATION 9

Accessing I/O devices Interrupts Direct Memory Access Buses Interface Circuits Standard I/O Interfaces (PCI, SCSI, USB). TOTAL : 45 TEXT BOOKS 1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Computer Organization 5th Ed, McGraw Hill, 2002. REFERENCES

1. 2. 3.

William Stallings, Computer Organization & Architecture Designing for Performance, 6 th Ed., Pearson Education, 2003 reprint. David A.Patterson and John L.Hennessy, Computer Organization & Design, the hardware / software interface, 2nd Ed, Morgan Kaufmann, 2002 reprint. John P.Hayes, Computer Architecture & Organization, 3rd Ed, McGraw-Hill, 1998.

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ARULMIGU KALASALINGAM COLLEGE OF ENGINEERING ANAND NAGAR, KRISHNANKOIL. DEPARTMENT OF ELECTRONICS & COMMUNICATION COURSE PLAN Name of the Subject: COMPUTER ARCHITECTURE Name of the Staff : Mr.P.SivaKumar
AIM To discuss the basic structure of a digital computer and to study in detail the organization of the Control unit, the Arithmetic and Logical unit, the Memory unit and the I/O unit. OBJECTIVES To have a thorough understanding of the basic structure and operation of a digital computer. To discuss in detail the operation of the arithmetic unit including the algorithms & implementation of fixedpoint and floating-point addition, subtraction, multiplication & division. To study in detail the different types of control and the concept of pipelining. To study the hierarchical memory system including cache memories and virtual memory. To study the different ways of communicating with I/O devices and standard I/O interfaces. TEXT BOOKS 1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Computer Organization 5th Ed, McGraw Hill, 2002. REFERENCES

Code : CS1251 Sem/Branch/Sec: VI /ECE /A & B

1. 2. 3.

William Stallings, Computer Organization & Architecture Designing for Performance, 6th Ed., Pearson Education, 2003 reprint. David A.Patterson and John L.Hennessy, Computer Organization & Design, the hardware / software interface, 2nd Ed, Morgan Kaufmann, 2002 reprint. John P.Hayes, Computer Architecture & Organization, 3rd Ed, McGraw-Hill, 1998.

Web Resources http://www.math.metu.edu.tr/csnm/basic_comp_oper.ppt. Basic Computer Operation http://www.ece.uah.edu/~milenka/cpe631-06s/lectures/ Computer System Architechture http://www.cse.nd.edu/courses/cse60321/www/lectures/ Memory Operation http://faculty.augie.edu/~sweets/Classes/236/lectures Computer Arithmetic http://comp.uark.edu/~hshen/ceng2213/chapter%207.ppt Basic Processing Unit Lesson Plan S.No 1 2 Topic Name Text Book Page No No.of Periods 3 3 Cumulative No. of Periods 3 6

UNIT I BASIC STRUCTURE OF COMPUTERS Functional units- Basic Operational Concepts, Bus T1 1-33 Structures Software Performance Memory locations & T1 34-36 addresses Memory operations

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Instruction and instruction sequencing addressing T1 37-56 modes Assembly language Basic I/O operations stacks T1 58-102 and queues. UNIT II ARITHMETIC Addition and subtraction of signed numbers T1 367-369 Design of fast adders multiplication of positive T1 370-385 numbers signed operand multiplication and fast T1 380-390 multiplication Integer division floating point numbers and T1 390-410 operations UNIT III BASIC PROCESSING UNIT Fundamental concepts Execution of a complete T1 411-424 Instruction Multiple bus organization Hardwired control T1 425-440 micro programmed control. Pipelining Basic concepts data hazards T1 440-452 instruction hazards influence on Instruction sets T1 453-476 Data path and control consideration Superscalar T1 476-570 operation UNIT IV MEMORY SYSTEM Basic concepts semiconductor RAMs, ROMs T1 291-309 Speed, size and cost cache memories T1 310-325 Performance consideration Virtual memory T1 326-337 Memory Management requirements Secondary T1 338-366 storage UNIT V I/O ORGANIZATION Accessing I/O devices Interrupts T1 203-233 Direct Memory Access Buses T1 234-247 Interface Circuits Standard I/O Interfaces (PCI, T1 248-290 SCSI, USB).

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9 12 14 16 18 21 23 25 28 31 35 38 41 44 48 51 53 56

Portion for Internal Test S.No. 1 2 3 Internal Test I II III Portion Topics 1-6 Topics 7-13 Topics 14-20

Related books 1. D.Sima, T.Fontain and P.Kacsuk, Advanced Computer Architectures: A Design Space Approach, Addison Wesley, 2000. 2. Kai Hwang and Zhi.Wei Xu, Scalable parallel Computing, Tata McGra-Hill, New Delhi,2003. Prepared by Mr.P.SivaKumar Verified by HOD/ECE