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Synchronization Design

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1. Overview Synchronization is a fundamental component of an optimally performing network. Synchronization networks provide timing signals to all synchronization network elements at each node in a digital network. These timing signals are traceable to a highly accurate PRS (Primary Reference Source) clock of Stratum 1 quality with frequency accuracy of 10-11 or better. The aim is to ensure that all outgoing transmissions from a digital network node have the same average frequency. Buffer elements are used at important transmission interfaces to absorb differences between the average local frequency and the actual short-term frequency of incoming signals, which may be affected by phase wander and jitter accumulated along the transmission paths. The very nature of digital communications is based on clocking signals. All digital signals require some form of clocking. Sampling, multiplexing, accessing and transportation of digital data are all dependent on changes based on prescribed time intervals. Digital switches, digital cross-connect, multiplexers and digital transport systems are all linked for the sole purpose of reliable communications. All of these pieces must mesh with respect to time in order to get the right information sampled, switched, transported and received. Network synchronization is a method of achieving: A common clock rate for the elements making up the network and; Ensuring that transmission impairments impacting synchronization between nodes be kept to a minimum.

In addition to synchronizing the clock rates at the transmit and receive ends, the links connecting both ends must be designed to minimize timing impairments such as jitter and frequency wander. The quality of the transmission facilities for transporting traffic or synchronization data is dependent on the degree of alignment between the transmit and receive clocks. The higher the degree of alignment the better the error performance. As the degree of alignment degrades, the rates of operation at the transmit and receive nodes start to differ. The end result of this difference in rates is a loss or repetition of bits or bytes of information. This event is defined a slip. Digital communications relies on the use of data buffers to account for differences in clock rates between the transmitted and received data. As the difference increases, the amount of buffer capacity consumed grows. If the difference is too great for the buffers, then an overflow occurs resulting in a slip condition. The impact of slip degradation on different services are shown in the following table:
Service Voice Voice band data Fax Encrypted voice Compressed video Packet data Observed effect Occasional audible clicks Serious degradation, with some modems needing up to 6 seconds to recover from a slip Each slip causes compression or blank lines Serious degradation requiring retransmission of the encryption key Serious degradation resulting in freeze frames or missing lines Loss of packets, resulting in degraded throughput and retransmission delays

Table 1: Impact of slips

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In the PDH environment, the classical mechanism for passing synchronization through a telecom network is to use the TS0 (Time Slot 0). In order to overcome slip problems in the PDH networks, SDH employs a container structure to move the traffic through the network. This considerably reduces the impact of poor synchronization on the efficiency of the transmission network and correspondingly improving the throughput of applications. As the containers realign themselves within the transmission layer, they inject phase hits onto the synchronization layer. The result is that TS0 in an E1 delivered over an SDH network would be susceptible to phase hits if the network is to become badly behaved and experience pointer adjustments. Any applications dependent on a clean, stable wander-free TS0 is potentially at risk. A synchronization problem exists in two distinct forms:

Non-systematic, i.e. spontaneous and unpredictable: As the virtual container is moved around to accommodate anomalies in transmission, TS0 experiences either VC-4 or VC-12 phase hits. VC4 pointers occur if the virtual container is in the higher level and VC-12 pointers occur if the virtual container is in the lower level. VC-4 pointer adjustments have less of an impact than VC-12, being 160 nanoseconds rather than 3.57 microseconds. Systematic (i.e. regular and continuous) phase transients are created within the various equipment elements in a telecom network by either the phase locked loop behaviour of the clock recovery circuit or the effects of buffer correction activity.

Both types of noise will be a problem where the connected application is expecting to see good quality synchronization on the E1. What is causing switching phenomenon? In legacy PDH networks, long term frequency drift or very long wander build up within a network must be compensated for at the access point. If not, it will cause problems by filling up the buffer and creating a slip. Packetization delay is the delay caused by the necessity to fill a packet before it is transmitted and is particularly evident with compressed voice calls associated with GSM traffic. Buffering delay results from the need to maintain a real time delivery of voice traffic across the network. The traffic must be broken down into packets in order to be transmitted. These packets must then be reassembled in order to reproduce (emulate) the original voice call. This delay can often be considerable and if it is not carefully controlled can cause problems with CBR traffic such as voice over ATM. However the control mechanism, i.e. the buffer imposes its own effect on the E1, experienced as the frequency switching. 2. Synchronization Elements and Standards The digital switch is made up of timed elements which may consists of cross connects, multiplexers and gateways. The deployment of these devices is based on the need to transport and route traffic amongst a network of telecommunications nodes. The network design for these elements is a function of access, traffic patterns, carrier boundaries and circuit performance criteria. The circuit performance criteria is predicated on a maximum allowable level of jitter and wander. The amount of network jitter and wander present is dependent on the type of clocks used and the criteria for network design. Choosing the right type of clock is the first step in providing a solid infrastructure for the timed network elements. Master-slave synchronization uses a hierarchy of clocks in which each level of the hierarchy is synchronized with reference to a higher level, the highest level being the PRC.

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The hierarchical levels are shown below:

The PRC (G.811) may be realized as an autonomous clock operating independently of any other sources, or as a non-autonomous clock disciplined by a UTC derived precision signal received from a radio or a satellite system. Currently these requirements can be met with either a cesium beam system or a GPS receiver system. Cesium standards are a standalone, highly reliable stratum 1 PRC and provide signal accuracy exceeding the stratum 1 minimum requirement. Cesium is easy to install and turn up when rapid deployment is critical. Minimum training is required because it is self contained and simple to operate and maintain. GPS is a reliable PRC but is dependent on satellite visibility to provide stratum 1 accuracy. The GPS technology does provide the service provider time of day using the Network Time Protocol (NTP) since the GPS system is traceable to UTC. The SSU (G.812) serves as the slave clock in timing nodes that are referenced to an upstream master clock. The main purposes of the SSU are: o Reference selection: typically more than one source feed is made available to the SSU. The SSU must be able to select a reference based on priority, validation, SSM or combinations thereof; o Source validation: performance monitoring of the reference signals in order to determine the quality of the best available reference; o Holdover: in the event the reference inputs fail, the SSU must maintain an output of a specified accuracy over a defined timeframe. This feature is a function of the internal clocks within the SSU. o Filtering: the output from the SSU must be impervious to any input signal variations. The typical parameters which the SSU will filter are jitter and wander accumulation. The SSU has tree main components: inputs, clocks and outputs. Usually the SSU is configured with at least 2 input cards for redundancy. This provides the SSU system with multiple reference input sources and can be of great benefit for performance monitoring and maintenance. The SSU can distribute multiple outputs, different signal types, and provide output redundancy. Most manufactures of SSU equipment can provide hundreds of outputs from the system, where the most common output type are E1 and 2048 MHz.

SDH network element clock (SEC) G.813

About Network Time Protocol (NTP): NTP is a protocol that devices can use to obtain accurate time of day (TOD). Accuracy is typically within nanoseconds of UTC. NTP is transmitted on top of TCP/IP Two operational modes: Client/Server and Broadcast Most time servers are GPS

If synchronization is not guaranteed, considerable degradation in network function, and even total failure of the network can be the result. To avoid this worst case scenario, all network elements need to be synchronized to a central clock. This central clock is generated by a high precision Primary Reference Clock (PRC) unit conforming to ITU-T G.811 (accuracy of 10-11). This clock signal must be

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distributed throughout the entire network. A hierarchical structure is used for this; the signal is passed on by the subordinate Synchronization Supply Units (SSU) and Synchronous Equipment Clock (SEC).
PRC G.811

SSU G.812

SSU G.812

SEC G.813

SEC G.813

SEC G.813

SEC G.813

Figure 1: Synchronization hierarchy The clock signal is regenerated in the SSU and SEC with the aid of phase-locked loops. If the clock supply fails, the affected network element switches over to a clock source with the same or lower quality, or if this is not possible, it switches to hold-over mode. 3. Rules The SDH frame synchronization method uses a technique called pointer adjustments. The pointer is an address field that tells the multiplexer where the VC is located within the overall frame. Adjusting the pointer address to inform the multiplexer that the VC position has moved can rectify any real delays that occur over the network. The pointer addresses are moved in blocks of 3 bytes, so each pointer movement adds 3 unit intervals of jitter onto the system. A maximum of 15 NE from the PRC can be daisy-chained until it needs to be filtered to the stability set in G.812. After 60 NE, the clock source must be regenerated to achieve a G.811 standard. External synchronization equipment, often GPS or Cesium based, is used to achieve this in a network. ADM/DXC systems must meet the objectives laid down by G.813. However, in practical synchronization network design, the number of network elements in tandem should be minimized for reliability reasons. It is recommended that all node clocks and network element clocks are able to recover timing from at least two synchronization distribution trails. The slave clock must reconfigure to recover timing from an alternative trail if the original trail fails.

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In the event of a failure of synchronization distribution, all network elements need to recover timing from the highest hierarchical level clock source available. To effect this, both G.812 and G.813 clocks may have to reconfigure and recover timing from one of their alternate synchronization distribution trails. This will ensure that a SDH network element clock-timed network element rarely enters holdover or free-run mode. However, it may have to recover timing from a G.812 clock which is itself in holdover if this is the highest hierarchical level source available to it. To provide an example of a reconfiguration, if the first network element from the PRC loses its synchronization trail from the PRC, it must reconfigure and accept timing from the G.812 slave clock. This is shown in the following figure:
G.811 clock G.811 clock

1st NE

1st NE

Timing propagation

2nd NE

Timing recovery

2nd NE

Nth NE

Nth NE

G.812 clock Before recovery

G.812 clock After recovery

Figure 2: Synchronization reconfiguration example 4. PDH and SDH interworking In many scenarios, there is a need to carry a PDH payload across multiple SDH islands. There is no absolute guarantee that every PDH multiplex chain will accept the output jitter appearing at the SDH/PDH boundary. This is because there is no specified lower limit to the corner frequency of the PDH demultiplex transfer characteristic. 5. Mobile Base Stations synchronization requirements A GSM BTS requires 5 x 10-8. A 3G NodeB requires 2 x 10-8.
GPS or Line Sync

Transmission BTS Retimer

Transmission BSC

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6. Benefits of a synchronized network The overall performance of a digital network is directly related to the degree of synchronization amongst the network elements and nodes. Among the many benefits of a properly planned synchronization network, the following are the most prominent: Minimizes the number of frame slips on TDM (Time Division Multiplexed) telecom networks Minimizes jitter, suppresses short term instabilities and wander resulting in: o o Clean external reference to network elements Clean synchronization feeds to downstream networks

Improves operation between PDH and SDH networks Fewer customer outages and complaints

7. Synchronization planning approach and consideration In order to design and construct a network that will provide a sound synchronization infrastructure, the following attributes will be accounted for: Satisfactory QoS (quality of service) levels for critical services. For example, controlling slip rates and limiting pointer adjustments; Maximized reliability and redundancy with protection schemes; Minimize network maintenance; Observe hierarchical top down approach; Minimize potential timing loops; Design a robust network where redundant and seamless protection is available; Minimize human interaction; Develop a network management scheme for remote central office management.

With these goals in mind, there are five basic planning considerations for synchronization which is emphasized: Maintain hierarchy Use the SSU concept Avoid timing loops with careful engineering and planning Diversity: PRS and cabling diversity Minimize cascading effect of distributed timing

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Designing a synchronization network is a combination of choosing the right clocks and placing them at logical points in the network to provide maximum performance and reliability. 7.1 Maintaining hierarchy Since synchronization is the result of achieving a common network clock rate, it is important to understand the various ways this can be achieved. The objective of the synchronization network is to distribute timing references that are traceable to a primary reference source (PRS) in order to achieve the common network clock rate. It is this concept of traceable timing that requires a logical method of networking timing nodes to ensure all nodes are timed by the proper reference points. Hierarchical Master Slave In a hierarchical arrangement of clocks, the level, or quality of clocks placed in the network is such that the higher level clock always provides distribution of the reference signal to lower level clocks. Further, it is sufficient for a site to receive timing from an upstream site of equal type and subsequently pass it on to another of equal type or level. Historically, this has been the most commonly used network synchronization technique. In this configuration, a reference or master clock is distributed to all nodes through a tree like topology. The master-slave synchronization network can be characterized by the following attributes: The network consists of hierarchical levels; The highest level contains the master clock of the network; The master clock provides distribution of the synchronization reference signal to downstream slave clocks; The slave clocks supply timing to yet lower level clocks in the hierarchy; The slave clocks in level 2 will serve as a reference to the level 3 clocks if all reference signals coming from the master are lost; Synchronization is always transferred from a higher level to a lower level to avoid timing loops; All slave clocks should receive reference signals from multiple sources via different paths.

Even with the advent of distributed PRS sites, care must be taken in the inter-site distribution of the synchronization signal. The synchronization signal of the PRS is distributed to the SSUs directly via a ring or chain of SECs. These transport signals must be suitable for the transport of synchronization such that, at the end of the trail, it must be possible to recover the timing signal which meets the jitter and wander limits (specified in ITU-G.823 and G.825). 7.2 Use the SSU concept The SSU is the key component for deploying proper synchronization in a network. With the ability to validate accuracy of an input signal and distribution to all the NE, an SSU will be the mechanism by which each and every NE in a single central site should be timed from. The SSU can be a standalone PRC, an integrated PRC/SSU, or use a derived E1 signal.

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7.3 Avoid timing loops Timing loops occur when a clock is being referenced to itself. A condition like this will make the network timing drift and become unstable and ultimately will cause slips in the network. A potential timing loop example is shown in Figure. In the figure, when the synchronization output from the SSU is cut, the network will enter into a timing loop.

SSU

SEC

SEC

SEC

SEC

Figure 2: Timing loop 7.4 Diversity Maintaining network reliability becomes paramount compared to the relative small cost of implementing a redundant PRC clock system such as shown in the next figure.

GPS

Cesium

Redundant PRC

Figure: Redundant PRC clock 7.5 Minimize cascading To limit the accumulation of jitter and wander in a synchronization distribution chain, a maximum number of SSU (Synchronization Supply Unit) and SEC (Synchronous Equipment Clock) are advised not to be exceeded. The maximum number of SSU in a single chain shall not be more than 10, and the number of SEC shall not be more than 20 between SSUs, with the restriction that the total number of SEC within the chain is limited to 60.

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This explanation is better visualized in the following diagram:

SSU

SSU 1

N SEC

SSU

SSU 2

N SEC

Maximum recommended nodes: K = 10 N = 20, with restriction that SEC clocks do not exceed 60 within a single chain

SSU

SSU K

N SEC

Figure 3: SSU and SEC limits However, there will be cases when some links may have more noise and thus requires an independent PRS source at that location. This discretion will be left up to the designer to determine the severity and importance of the link, and where additional PRS and/or SSU may need to be added. 8. Synchronization deployment Although synchronization networks are different, there are certain constraints that every operator will agree upon, and that is, a synchronization plan must avoid timing loops, minimizes jitter and wander, performance of the network should be enhanced such that yardsticks like dropped phone calls are reduced, and slip are minimized. In the following paragraphs, an approach to formulate a synchronization plan will be introduced. This approach adheres to recommendations based on standards, is by no way a firm straight and narrow systematic scheme.

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In practice, passing synchronization in networks is classified in one of two categories, Inter-Node or IntraNode. In an inter-node scheme, synchronization is passed between nodes usually by way of a transport device, such as via SDH. In an intra-node scheme, synchronization is passed from a device such as an SSU to all pieces of equipment co-located in the same site. 8.1 Inter-Node synchronization With Inter-Node synchronization, distribution of timing from the PRSs to the other clocks in the network has, for the most part, been hierarchical. Todays digital network is characterized by a much more distributed versus hierarchical synchronization topology, due to the advances in clock designs and distribution techniques. It is worthwhile to review the different approaches to network synchronization, in order to fully comprehend the effects of synchronization. Network elements at different sites can be brought to a common clock rate by employing at least one of the following topologies. The most prevalent are: Independent PRS; Distributed PRS; Chains Rings

8.1.1 Independent PRS The independent clock approach is based on the plesiochronous approach to network synchronization where data buffers are used to compensate for the frequency differences in the system clocks. Highly stable atomic clock references are used at each node of the network with a buffer large enough to maintain a specified accuracy over a pre-determined period. Conceptually, independent clocks constitute the simplest of all techniques for network synchronization. The chief advantage lies in system survivability, where link degradation, or failure of one node does not affect other nodal clocks.

NE PRS 1

Transmission link

NE PRS 2

Transmission link NE PRS 3 NE

Transmission link

Figure 4: Independent clock synchronization concept

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8.1.2 Distributed PRS A distributed PRS approach actually combines the attributes of the hierarchical and independent clock methods. This technique involves the deployment of multiple PRS types at the same site in an effort to flatten the distribution hierarchy. The distributed PRS approach has several advantages: It reduces the complexity of the planning effort, i.e. simpler distribution topology; Provides for increased performance and reliability; Provides an opportunity for multiple alternate references (timing diversity) and supports an active surveillance capability; Can be used to establish fail-safe timing to SDH ring architectures, independent of software based message techniques;

8.1.3 Chain Synchronization signals can be transported between network nodes via synchronization chains with clock-transparent paths (2 Mbit/s paths) being preferred. The 2 Mbit/s data signals which are part of the SDH payload are not suitable as reference timing signals. The main requirements for inter-node synchronization are: Transportation of synchronization signals between node clocks must maintain jitter and wander performance requirements. In principle, a maximum number of 20 SECs in a chain between two SSUs will meet the requirements. In practice however, long chains are discouraged and are limited to 4 to guarantee performance margins; SDH NEs require alternative synchronization trails be established in case of distribution link failures. Reconfiguration scenarios can be based on SSM (Sync Status Messaging) schemes, which will be explored shortly.

Under normal operation the synchronization information is transported from SSU 1 which is assumed to be synchronized to a PRS, to SSU 2 via a chain of NEs containing an SEC clock. Under normal operation the network elements between SSU 1 and SSU 2 perform the following tasks in the transport of synchronization: NE 1: Generate a transport signal whose timing is derived from the upstream SSU which is synchronized to a PRS; NE 2.n-1: Recover the clock from the incoming transport signal and use it as reference for the SEC. The timing of the outgoing transport signals is derived from the SEC clock; NE n: Recover the clock from the incoming transport signal and generate a reference signal for the SSU.

In order to keep a lower quality clock from timing a higher quality clock, the reference output signal is squelched when the quality falls below the SSU level (or in some cases, below the PRC level). For that

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purpose, certain signal criteria must be supervised and the quality information in the SSM is evaluated, if SSM processing is supported and enabled in the NE. Alternatively if SSM is not used during a failure, the NEs in the chain are programmed to accept synchronization from the downstream SSU, reversing the direction of synchronization transport up to the point of the fault, as shown in the diagram. One important point to add to this scenario is that the downstream SSU must have a higher quality clock than the SEC internal clocks, otherwise hierarchy principles will be violated. 8.1.4 Rings Synchronization rings are typically made up of two parallel chains between SSUs, as shown in the following figure. The synchronization signal is injected into the ring at one of the NEs of the ring via the external reference input and transported through one of the SDH transport chains. At some other NE of the ring the reference signal is recovered and passed to the downstream SSU. A ring creates additional or different synchronization properties, compared to the chain: Using automatic reconfiguration mechanisms, each NE in the ring can be reached from the upstream SSU via two synchronization trails. Therefore it is not necessary to inject synchronization from the downstream SSU into the ring, even under many failure conditions as shown in the previous diagrams; The downstream SSU can be synchronized via either of the chains, i.e. via two alternative synchronization trails. There are two single points of failure, the gateway NEs to the SSUs. Those can be eliminated by injecting and extracting the synchronization signal at two NEs. Measures must be taken to avoid timing loops around the ring under certain failure conditions in connection with automatic reconfiguration. One method is to not close the ring. As shown in the diagram, the SEC clock with the red highlight does not provide a sync reference to the adjacent SEC, thereby not closing the ring.

Another method to avoid timing loops is to use SSM which is explored next. SSM Synchronous Status Messaging SSM evolved as a method to transport the quality of a synchronization signal utilizing a message to identify the state of the sync signal in order to avoid timing loops and for auto restoration of the sync network when the original sync signal is lost. Or to describe it simply, usage of SSM will allow an SSU or a NE to select the best available sync signal based on the sync quality messge. ETSI and ITU have standardized on a SSM messaging scheme to enable this feature. The SSM is coded in the S1 byte of the STM-N section overhead reflecting the SSM quality message. The fundamental strategy behind SSM is when a timing failure occurs, the network elements now have the ability to take an alternate timing reference signal based upon the quality level message that is available at its input and auto correct itself. Further the network element will relay this information to its downstream network element.

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8.2 Intra-Node synchronization In an intra-node synchronization distribution, the synchronization reference provide a reference signal to all co-located network elements i.e., same site. The reference signals are generated in a node clock which is usually a SASE (StandAlone Synchronization Equipment). Although some NEs feature an embedded SSU, the SASE implementation is preferred from a planning and maintenance perspective. The SASE is synchronized to a reference signal coming from a PRS via inter-node synchronization transport. [TRANS-SYNC] It is recommended that intra-node synchronization distribution is in the form of a logical star. Properties and functionalities for intra-node synchronization: Dedicated signals for synchronization transport to and from the node clock: o 2048 kHz (G.703) o 2048 kbit/s (G.703) o 2048 kbit/s (G.704) supporting SSM For robustness against faults in the synchronization transport several transport signals arriving at the node are selected as potential reference sources; Ensure that the reference signal at the inputs of the node clock is sufficient. This can be achieved in several ways: o Squelch the reference output at the NE if the quality indicated by the SSM message in the incoming traffic signal is below a threshold message. The threshold must not be lower than the quality of the node clock (in holdover mode, i.e. SSUT). Additionally other supervision criteria like Loss of Signal, Loss of Frame etc can be used for squelching; o Sync signals at the inputs of the node clock with respect to frequency deviation, phase jumps, can be measured with performance monitoring from the SSU. Collect the quality information of the NEs in a management system and select the best signal at the node clock by management command. This solution requires that the NEs and the node clock can be accessed from a common management system; Provide an SSM message for the STM-N signals leaving the node. In order to insert the correct value it is necessary to have the information about the quality of the reference signal in use at the node clock; If the intra-node synchronization distribution is accomplished via 2048 kHz signals, the only way to transport information is squelching the signal dependent of some supervision criteria; If 2048 kbit/s signals supporting SSM are used for intra-node synchronization, the quality information can be forwarded using the SSM message. This solution requires that all involved pieces of equipment have 2048 kbit/s reference inputs and outputs also support SSM. If none of the enumerated options are available, a fixed SSM message must be inserted into the STM-N signals leaving the node. The assignment of the appropriate SSM message is a task for the synchronization planner.

The synchronization signal can be transported between network nodes via synchronization chains with clock-transparent paths (2 Mbit/s path) being preferred. The 2 Mbit/s signals which are part of the SDH payload are not suitable as reference signals because they are subject to wander caused by pointer adjustments.

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