Am A Lin

Lecture-1
Digital Electronics and Computer Organization (DECO)

CS GC391/EEE GC391/INSTR GC391
A.Amalin Prince
AAP CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus
1
03-08-07
Objective : Introduction to Digital Systems and Characteristics of Digital ICs
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CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus
Digital and Analog Quantities
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The Digital Advantage
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An Analog Electronic System
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A system using Digital and Analog Methods
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Advantages of Digital Techniques

The devices used in digital circuits operate only in one of the two states, resulting in a very simple operation Requires Boolean Algebra which is very easy to understand Requires basic concepts of electric network analysis A large no. of ICs. are available for performing various operations. These are highly reliable, accurate and speed of operation is very high
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Contd..
The effect of fluctuations in the characteristics of the components, ageing of the components, temperature and noise is very small in digital circuits. Digital circuits have capability of memory which makes these circuits highly suitable for computers, calculators, wrist watches etc. Most Digital Devices are programmable Cost is very less Storage and Data transfer is easy.
Applications of Digital Circuits

Communications Business Transactions Traffic Control Space guidance Medical Treatment Internet Weather monitoring etc, etc.
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Levels of Integration
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Characteristics of Digital ICs

Logic Level Fan-out Fan-in Power Dissipation Propagation delay Noise Margin
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Logic Families
Digital Integrated circuits are classified not only by their complexity or logical operation but also by the specific circuit technology to which they belong. The circuit technology is referred to as a Digital Logic Family
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Logic Families
RTL DTL TTL ECL MOS CMOS Resister-Transistor Logic Diode-Transistor Logic Transistor-Transistor Logic Emitter-coupled Logic Metal-Oxide Semiconductor Complementary Metal-Oxide Semiconductor
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Voltage ranges of logic inputs for positive logic.
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Example
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Fan-Out
Fan-out: The no. of standard loads that can be connected to the output of the gate without degrading its normal operation. Unit: number Standard Load: The amount of current needed by an input of another gate in the same logic family.
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Calculated from the ratio:
I OH
I IH
or
I OL
I IL
whichever is smaller
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Fan-In
Fan-In: The number of inputs available in a Gate Unit: number
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Power Dissipation
It represents the amount of power needed by the gate. It refers to the power delivered to the gate from the power supply.( It does not include the power delivered from another gate) Unit: mW Calculated from : PD ( avg ) = I CC ( avg ) VCC
where I CC ( avg )
I CCH + I CCL = 2
Propagation delay
It is the average transition delay time for the signal to propagate from the input to the output when the binary signal changes in value. Unit: ns.
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Propagation delay times
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Noise Margin
It is the maximum noise voltage that can be added to an input signal of a digital circuit without causing an undesirable change in the circuit output. Noise: AC noise DC noise
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Noise effects. (a) Interconnection of two gates with induced noise. (b) Noise margins.
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Noise margin is
VOH VIH
or VIL VOL
Smaller of these will be the noise margin
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The End
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Lecture-2
A.Amalin Prince
1
06-08-07
Objective : Number Systems, Codes, Boolean Algebra and Logic Gates
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Number Systems
Decimal Binary Octal Hexadecimal
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Number Conversion
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Basic Arithmetic Operations

Addition Subtraction Multiplication Division
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Signed numbers and Complements

Addition and Subtraction with rsComplements and (r-1)s Complements
Where r is the base or radix of the number system.
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CODES
Weighted decimal codes Non-weighted decimal codes Unit-Distance codes Alphanumeric codes Error detecting codes
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Weighted decimal codes

Binary Coded Decimal : BCD
BCD are decimal numbers not binary although they use bit in their representation
BCD Arithmetic Why Weighted?

The corresponding decimal digit is easily determined by adding the weights associated with 1s in the code group.
Other BCD Codes

Decimal Digit
8421 (BCD) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
2421 0000 0001 0010 0011 0100 1011 1100 1101 1110 1111
5421
8 4 -2 -1 00 0 0 01 1 1 01 1 0 01 0 1 01 0 0 10 1 1 10 1 0 10 0 1 10 0 0 11 1 1
7 5 3 -6
0 1 2 3 4 5 6 7 8 9
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Non-weighted decimal codes

Decimal Digit
8421 (BCD) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Excess-3 Reflected Code 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
2-out-of-5-code 11000 00011 00101 00110
0 1 2 3 4 5 6 7 8 9
Self Complementing
01001 01010 01100 10001 10010 10100
* Except for 0, it is a weighted code having the weights 74210

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U.S. Postal Service bar code corresponding to the ZIP code 14263-1045.
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Unit-Distance Codes
Binary-to-Gray Code Conversion
The most significant bit (left-most) in the Gray code is the same as the corresponding MSB in the binary number. Going from left to right, add (or Ex-OR) each adjacent pair of binary code bits to get the next Gray code bit. Discard carries.
For example conversion from 10110 to Gray is as follows 1 0 1 1 0 Binary
Gray
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Unit-Distance Codes
Gray-to-Binary Code Conversion
The most significant bit (left-most) in the Binary number is the same as the corresponding MSB in the Gray code. Add (or Ex-OR) each binary code bit generated to the Gray code bit in the next adjacent position. Discard carries.
For example conversion from 11011 to Gray is as follows 1 1 0 1 1 Gray
Binary
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Unit-Distance Codes
Decimal Digit
Binary 0000 0001 0010 0011 0100 0101 0110 0111
Gray Code 0000 0001 0011 0010 0110 0111 0101 0100
Decimal Digit
Binary 1000 1001 1010 1011 1100 1101 1110 1111
Gray Code 1100 1101 1111 1110 1010 1011 1001 1000
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
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Angular position encoders. (a) Conventional binary encoder. (b) Gray code encoder.
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Angular position encoders with misaligned photosensing devices. (a) Conventional binary encoder. (b) Gray code encoder.
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Alphanumeric codes
ASCII Code
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Error detecting codes

Parity Code Hamming Code etc..
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Logic Gates
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Logic Gates
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Boolean Algebra
Boolean Algebra is used to simply/rearrange Boolean equation to make simple logic circuit.
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Laws of Boolean Algebra

Commutative Laws
Law 1: A+B = B+A Law 2: AB = BA
Associative Laws
Law 1: A+(B+C) = (A+B)+C Law 2: A(BC)= (AB)A
Distributive Laws
Law : A(B+C) = AB+AC
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No. 1. 2. 3. 4. 5. 6. 7. 8.
Rules A+0=A A+1=1 A+A=1 A+A=A A=A A+AB=A A+AB=A+B (A+B)(A+C)=A+BC
Law
Rules (Dual) A.1=A A.0=0 A.A=0 A.A=A A(A+B)=A A(A+B)=AB (AB)+(AC)=A(B+C)
Complementary Idempotent Involution Absorption Absorption
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Duality Theorem
The duality theorem says that, starting with a Boolean relation, you can derive another Boolean relation by
Changing each OR sign to an AND sign Changing each AND sign to an OR sign Complementing any 0 or 1 appearing in the expression
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Theorems
DeMorgans Law 1: A.B = A+B Law 2: A+B = A.B
Consensus theorem Law : AB+AC+BC = AB+AC Dual of Consensus theorem Law : (A+B)(A+C)(B+C) = (A+B)(A+C)
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Operator Precedence
Parentheses NOT AND OR
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Reduce the following
1. F = XY + XYZ + XY Z + XYZ
2. AB + A + AB
3. AB + AC + ABC ( AB + C )
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The End
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Lecture-3
A.Amalin Prince
1
08-08-07
Objective : Simplification of Boolean functions (Gate Level Minimization)
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Combinational circuits can be specified in one of the following ways

A set of statements Boolean expression Truth table
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Canonical and Standard Forms

Minterm or Standard product
Maxterm or Standard sum
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Minterms and Maxterms for three binary variables

X 0 0 0 0 1 1 1 1
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Y Z 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1
Minterms Term Designation XYZ m0 XYZ XYZ XYZ XYZ XYZ XYZ XYZ m1 m2 m3 m4 m5 m6 m7
Maxterms Term Designation X+Y+Z M0 X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z X+Y+Z M1 M2 M3 M4 M5 M6 M7
Function table of three variables

P 0 0 0 0 1 1 1 1
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Q 0 0 1 1 0 0 1 1
R 0 1 0 1 0 1 0 1
Function F1 0 0 0 0 0 1 1 1
Function F2 0 1 0 1 0 1 0 1
Sum of Minterms (SOP form) Product of Maxterms (POS form)
F1 = m(5, 6, 7)
SOP
F 2 = m(1,3,5, 7)
F1 = M (0,1, 2,3, 4)
Conversion between canonical forms
POS
F 2 = M (0, 2, 4, 6)
Try yourself
Convert the given expression in canonical SOP form Y=AC+AB+BC Y=ABC+ABC+ABC+ABC Convert the given expression in canonical POS form Y=A(A+B)(A+B+C) Y=(A+B+C)(A+B+C)(A+B+C)(A+B+C)
Digital Design
Optimizations and Tradeoffs
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Introduction
We now know how to build digital circuits
How can we build better circuits?
Lets consider two important design criteria

Delay the time from inputs changing to new correct stable output Size the number of transistors For quick estimation, assume
Every gate has delay of 1 gate-delay Every gate input requires 2 transistors Ignore inverters
w x y w x y F1 = wxy + wxy (a)
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i s
Transforming F1 to F2 represents an optimization: Better in all criteria of interest

20 size (transistors) 15 10 5 F2 1 2 3 4 delay (gate-delays) (c) F1
e r s o )
16 transistors 2 gate-delays F1
4 transistors 1 gate-delay w x F2
( t
= wx(y+y) = wx
F2 = wx
CS GC391/EEE GC391/INSTR GC391 (b) BITS-Pilani Goa Campus
Introduction
Tradeoff
Improves some, but worsens other, criteria of interest
Transforming G1 to G2 represents a tradeoff: Some criteria better, others worse.
14 transistors 2 gate-delays w G1 w y z G1 = wx + wy + z x y z G2 = w(x+y) + z
w x
size (transistors)
12 transistors 3 gate-delays
e z
20 15 10 5 1 2 3 4 delay (gate-delays) G1 G2
G2
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Introduction
Tradeoffs Optimizations
All criteria of interest are improved (or at least kept the same) size size
e e z z i s i s
Some criteria of interest are improved, while others are worsened
delay
i s
delay
a n s i
We obviously prefer optimizations, but often must accept tradeoffs

e z
You cant build a car that is the most comfortable, and has the best fuel efficiency, and is the fastest you have to give up something to gain other things.
Combinational Logic Optimization and Tradeoffs

Two-level size optimization using algebraic methods
Goal: circuit with only two levels (ORed AND gates), with minimum transistors
Though transistors getting cheaper (Moores Law), they still cost something Example
F = xyz + xyz + xyz + xyz F = xy(z + z) + xy(z + z) F = xy*1 + xy*1 F = xy + xy
x y F x y 0 0 y x m n y m 1 x 1 1 y n F n m n m
Define problem algebraically

Sum-of-products yields two levels
F = abc + abc is sum-of-products; G = w(xy + z) is not.
4 literals + 2 terms = 6 gate inputs
6 gate inputs = 12 transistors

0
Transform sum-of-products equation tox have fewest literals and terms

Each literal and term translates to a gate y input, each of which translates to about x 2 transistors Ignore inverters for simplicity
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Note: Assuming 4-transistor 2-input AND/OR CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus NAND/NOR are so efficient. in reality, only
circuits;
Algebraic Two-Level Size Minimization

Previous example showed common algebraic minimization method
(Multiply out to sum-of-products, then) Apply following as much possible
ab + ab = a(b + b) = a*1 = a Combining terms to eliminate a variable
(Formally called the Uniting theorem) F = xyz + xyz + xyz + xyz F = xy(z + z) + xy(z + z) F = xy*1 + xy*1 F = xy + xy F = xyz + xyz + xyz F = xyz + xyz + xyz + xyz F = xy(z+z) + xz(y+y) F = xy + xz G = xyz + xyz + xyz + xyz G = xy(z+z) + xy(z+z) G = xy + xy (now do again) G = x(y+y) G=x
Duplicating a term sometimes helps

Note that doesnt change function
c + d = c + d + d = c + d + d + d + d ...
Sometimes after combining terms, can combine resulting terms

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Karnaugh Maps for Two-Level Size Minimization

Two variable map
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Three variable k-map
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Easy to miss seeing possible opportunities to combine terms Karnaugh Maps (K-maps)
Graphical method to help us find opportunities to combine terms Minterms differing in one variable are adjacent in the Notice not in binary order map F yz
x 0 1 00 01 11 10
XYZ XYZ XYZ XYZ XYZ XYZ XYZ XYZ
Treat left & right as adjacent too

The End
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Lecture-4
A.Amalin Prince
1
10-08-07
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Karnaugh Maps for Two-Level Size Minimization

Two variable map
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Three variable k-map
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F = xyz + xyz + xyz + xyz Can clearly see opportunities to combine terms look for adjacent 1s
For F, clearly two opportunities Top left circle is shorthand for xyz+xyz = xy(z+z) = xy(1) = xy Draw circle, write term that has all the literals except the one that changes in the circle
Circle xy, x=1 & y=1 in both cells of the circle, but z changes (z=1 in one cell, 0 in the other)
F yz 00 01 11 10 x 0 1 1 0 0 1 0 0 1 1
F yz 00 01 11 10 x 0 1 1 0 0 1 0 0 1 1 xy xy F = xy + xy
F = xyz + xyz + xyz + xyz F = xy(z + z) + xy(z + z) F = xy*1 + xy*1 F = xy + xy
Minimized function: OR the final terms

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CS GC391/EEE GC391/INSTR GC391 Easier BITS-Pilani Goa Campus
than all that algebra:
K-maps
Four adjacent 1s means two variables can be eliminated
G = xyz + xyz + xyz + xyz G = x(yz+ yz + yz + yz) (must be true) G = x(y(z+z) + y(z+z)) G = x(y+y) G = x G yz x 00 01 11 10
0 0 0 0 0 Makes intuitive sense those two variables 1 1 1 1 1 x appear in all combinations, so one Draw the biggest circle possible, or youll have more terms than really needed must be true G yz x 00 01 11 10 Draw one big circle 0 0 0 0 0 shorthand for the algebraic 1 1 1 1 1 xy xy transformations above
K-maps
H = xyz + xyz + xyz + xyz
H yz (xy appears in all combinations) Four adjacent cells can be in x shape of a square 00 01 11 10 0 0 1 1 0 OK to cover a 1 twice z Just like duplicating a term 1 0 1 1 0 Remember, c + d = c + d + d I yz yz No need to cover 1s x 00 01 11 10 more than once 0 0 1 0 0 Yields extra terms not minimized 1 1 1 1 1
J yz xy yz x 00 01 11 10 0 1
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1 0
1 1
0 1
0 0
xz
x The two circles are shorthand for: I = xyz + xyz + xyz + xyz + xyz I = xyz + xyz + xyz + xyz + xyz + xyz I = (xyz + xyz) + (xyz + xyz + xyz + xyz) I = (yz) + (x)
K-maps
Circles can cross left/right sides Remember, edges are adjacent Minterms differ in one variable only Circles must have 1, 2, 4, or 8 cells 3, 5, or 7 not allowed 3/5/7 doesnt correspond to algebraic transformations that combine terms to eliminate a variable Circling all the cells is OK Function just equals 1
K yz x 00 0 1 0
1
xyz 01 1 0 11 0 0 10 0
1
xz
L yz x 00 0 1 0 1
01 11 0 1 0 1
10 0 0
E yz x 00 0 1 1 1
01 11 10 1 1 1 1 1 1 1
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An illustrative three-variable Boolean function.
xz
xy
f xy+xz
Try yourself
Simplify 1. f(x,y,z) = m(0,1,2,3,5,7) 2. Y=ABC+ABC+ABC+ABC
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K-maps for Four Variables
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K-maps for Four Variables

Four-variable K-map follows same principle
Adjacent cells differ in one variable Left/right adjacent Top/bottom also adjacent
F yz wx 00 01 11 10 00 0 0 1 0
01 1 11 0 10 0
1 0 0 yz
1 1 1
0 0 0
G yz wx 00 01 11 10 00 0 1 1 0 01 0 11 0 10 0 z
F=wxy+yz
1 1 1
1 1 1
0 0 0
G=z
Two-Level Size Minimization Using K-maps Four Variable Example

Minimize: H = ab(cd + cd) + abcd + abcd + abd + abcd 1. Convert to sum-of-products: H = abcd + abcd + abcd + abcd + abd + abcd 2. Place 1s in K-map cells 3. Cover 1s 4. OR resulting terms
abcd abcd abcd abd abcd abcd bd bc a abd
H c d ab 00 01 11 10 00 01 11 10 1 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1
H = bd + abc + abd
Funny-looking circle, but remember that left/right adjacent, and top/bottom adjacent
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Karnaugh map for f(w,x,y,z) = m(1,2,3,5,6,7,8,13)
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Try Yourself
F ( P, Q, R, S ) = m(0,1, 4,8,9,10)
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K-maps for Five Variables
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1 1 1 1 1
1 1 1
1
Simplify F=m(0,2,4,6,9,13,21,23,25,29,31)
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5 and 6 variable maps exist

But hard to use
Two-variable maps exist

But not very useful easy to do algebraically by hand
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The End
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Lecture-5
A.Amalin Prince
1
13-08-07
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Dont Care Input Combinations

What if particular input combinations can never occur?
e.g., Minimize F = xyz, given that xyz 11 10 (xyz=000) can never be true, and that xyz 0 X 0 0 0 (xyz=101) can never be true 1 0 0 So it doesnt matter what F outputs when 1 X xyz or xyz is true, because those cases Good use of dont cares will never occur Thus, make F be 1 or 0 for those cases in F yz yz unneeded a way that best minimizes the equation
F yz yz x 00 01
On K-map
Draw Xs for dont care combinations
Include X in circle ONLY if minimizes equation Dont include other Xs
00 0 1 X 1
01 11 10 0 X 0 0 0 0 xy
Unnecessary use of dont cares; results in extra term
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Minimizization Example using Dont Cares

Minimize:
F = abc + abc + abc Given dont cares: abc, abc
F a 0 1 bc 00 0 0 01 1 0 ac 11 X X 10 1 1 b
Note: Use dont cares with caution

Must be sure that we really dont care what the function outputs for that input combination If we do care, even the slightest, then its probably safer to set the output to 0
F = ac + b
Minimization with Dont Cares Example:

Sliding Switch
Switch with 5 positions
3-bit value gives position in binary
1 2 3 4 5 x y z G yz Without dont x 00 01 11 10 cares: 0 0 0 1 1 F = xy + xyz 0 0 2,3,4, detector G
Want circuit that
Outputs 1 when switch is in position 2, 3, or 4 1 1 0 Outputs 0 when switch is in G yz position 1 or 5 y x 00 01 11 10 Note that the 3-bit input can 0 X 0 1 1 never output binary 0, 6, or 7
Treat as dont care input combinations
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xy xyz
With dont cares: F = y + z
Try yourself
F ( P, Q, R, S ) = m(1,3, 7,11,15) + d (0, 2, 4)
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Automating Two-Level Logic Size Minimization

Minimizing by hand
Is hard for functions with 5 or more variables May not yield minimum cover depending on order we choose Is error prone
I x 0
(a)
yz 00 1 1 01 1 0 11 1 1 10 0 1 xy
1 yz I x 0
(b)
Minimization thus typically done by automated tools

Exact algorithm: finds optimal solution Heuristic: finds good solution, but not necessarily optimal
yz 00 1 1
xy yz 4 terms 01 1 0 11 1 1
10 0 1
1 yz
xz xy Only 3 terms
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Basic Concepts Underlying Automated Two-Level F yz Logic Minimization xyz

Definitions
On-set: All minterms that define when F=1 Off-set: All minterms that define when F=0 Implicant: Any product term (minterm or other) that when 1 causes F=1
On K-map, any legal (but not necessarily largest) circle Cover: Implicant xy covers minterms xyz and xyz
x 00 0 1 0 0 01 1 0 11 0 1 10 0 1 xyz xyz xy
4 implicants of F
Note: We use K-maps here just for intuitive illustration of concepts; automated tools do not use K-maps.
Expanding a term: removing a variable (like larger K-map circle)

xyz
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xy is an expansion of xyz
Prime implicant: Product term obtained by combining the maximum possible number of adjacent squares in the map. xyz, and xy, above But not xyz or xyz they can be expanded
Basic Concepts Underlying Automated TwoLevel Logic Minimization not essential

Definitions (cont)
G x yz 00 1 0 01 1 1 yz 11 0 1 10 0 1 xy essential
Essential prime implicant: If a minterm in a square is 0 covered by only one prime 1 implicant, that prime implicant xy is essential prime implicat. essential
Importance: We must include all essential PIs in a functions cover In contrast, some, but not all, non-essential PIs will be included
xz not essential
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Automated Two-Level Logic Minimization Method
Steps 1 and 2 are exact Step 3: Hard. Checking all possibilities: exact, but computationally expensive. Checking some but not all: heuristic.
Example of Automated Two-Level Minimization

1. Determine all prime implicants 2. Add essential PIs to cover
Italicized 1s are thus already covered Only one uncovered 1 remains
I yz x z x 00 01 11 10 1 0 1 1 1 0 (a) 1 1 0 0 1 1 y x z y I yz x z x 00 01 11 10 (b) 0 1 1 1 1 0 1 0 0 1 xz xz
3. Cover remaining minterms with non-essential PIs

Pick among the two possible PIs
y x z y I yz x z x 00 01 11 10 (c ) 0 1 1 1 y z 1 0 1 0 0 1
xz
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The End
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Lecture-6
A.Amalin Prince
1
17-08-07
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Quine-McCluskey Method
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Motivation
Karnaugh maps are very effective for the minimization of expressions with up to 5 or 6 inputs. However they are difficult to use and error prone for circuits with many inputs. Karnaugh maps depend on our ability to visually identify prime implicants and select a set of prime implicants that cover all minterms. They do not provide a direct algorithm to be implemented in a computer. For larger systems, we need a programmable method!!
Quine-McCluskey
Willard van Orman Quine 1908-2000, Edgar Pierce Chair of Philosophy at Harvard University.
http://members.aol.com/drquine/wv-quine.html
Quine, Willard, The problem of simplifying truth functions.
American Mathematical Monthly, vol. 59, 1952.

Quine, Willard, A way to simplify truth functions.
American Mathematical Monthly, vol. 62, 1955.
Edward J. McCluskey, Professor of Electrical Engineering and Computer Science at Stanford

http://www-crc.stanford.edu/users/ejm/McCluskey_Edward.html
McCluskey Jr., Edward J. Minimization of Boolean Functions.
Bell Systems Technical Journal, vol. 35, pp. 1417-1444, 1956

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Outline of the Quine-McCluskey Method

1. Produce a minterm expansion (standard sum-of-products form) for a function F 2. Eliminate as many literals as possible by systematically applying XY + XY = X. 3. Use a prime implicant chart to select a minimum set of prime implicants that when ORed together produce F, and that contains a minimum number of literals.
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Determination of Prime Implicants

ABCD + ABCD = ABC 1010 +1011=101-
(The dash indicates a missing variable)
We can combine the minterms above because they differ by a single bit. The minterms below wont combine
ABCD + ABCD 0101 +0110
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Quine-McCluskey Method An Example f (a, b, c, d ) = m(0,1,2,5,6,7,8,9,10,14)

Decimal 0 1 2 5 6 7 8 9 10 14
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binary 0000 0001 0010 0101 0110 0111 1000 1001 1010 1110
1. Find all the prime implicants

group 0 0 0000 1 0001 group 1 2 0010 8 1000 5 0101 group 2 6 0110 9 1001 10 1010 7 0111 group 3 14 1110
Group the minterms according to the number of 1s in the minterm. This way we only have to compare minterms from adjacent groups.
Quine-McCluskey Method An Example

Column I group 0 group 1 Combining group 0 and group 1:
0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
group 2
group 3
7 0111 14 1110
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0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 000-
group 2
group 3
7 0111 14 1110
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0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0
group 2
group 3
7 0111 14 1110
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Column I Does it make group 0 sense to no combine group 0 group 1 with group 2 or 3? No, there are at least two bits that group 2 are different. group 3
0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000
7 0111 14 1110
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Column I Does it make group 0 sense to no combine group 0 group 1 with group 2 or 3? No, there are at least two bits that group 2 are different. Thus, next we combine group 1 group 3 and group 2.
0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000
7 0111 14 1110
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Column I group 0 group 1 Combine group 1 and group 2. group 2
0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 00000-0 -000 0-01
group 3
7 0111 14 1110
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0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 00000-0 -000 0-01
group 3
7 0111 14 1110
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0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 00000-0 -000 0-01 -001
group 3
7 0111 14 1110
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0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 00000-0 -000 0-01 -001
group 3
7 0111 14 1110
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0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 00000-0 -000 0-01 -001
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 00000-0 -000 0-01 -001
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 00000-0 -000 0-01 -001 0-10
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 00000-0 -000 0-01 -001 0-10
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 00000-0 -000 0-01 -001 0-10 -010
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 00000-0 -000 0-01 -001 0-10 -010
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 00000-0 -000 0-01 -001 0-10 -010
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 00000-0 -000 0-01 -001 0-10 -010 100-
group 3
7 0111 14 1110
AAP

Column I Again, there is no need to try to combine group 1 with group 2. group 0 group 1
0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 00000-0 -000 0-01 -001 0-10 -010 10010-0
group 2
group 3
7 0111 14 1110
AAP

Column I Again, there is no need to try to combine group 1 with group 3. group 0 group 1
0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 00000-0 -000 0-01 -001 0-10 -010 10010-0
Lets try to combine group 2 group 2 with group 3. group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 5,7 00000-0 -000 0-01 -001 0-10 -010 10010-0 01-1
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 5,7 00000-0 -000 0-01 -001 0-10 -010 10010-0 01-1
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 5,7 6,7 00000-0 -000 0-01 -001 0-10 -010 10010-0 01-1 011-
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 5,7 6,7 6,14 00000-0 -000 0-01 -001 0-10 -010 10010-0 01-1 011-110
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 5,7 6,7 6,14 00000-0 -000 0-01 -001 0-10 -010 10010-0 01-1 011-110
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 5,7 6,7 6,14 00000-0 -000 0-01 -001 0-10 -010 10010-0 01-1 011-110
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0,2 0,8 1,5 1,9 2,6 2,10 8,9 8,10 5,7 6,7 6,14 00000-0 -000 0-01 -001 0-10 -010 10010-0 01-1 011-110
group 3
7 0111 14 1110
AAP

Column I We have now completed the first step. All minterms in column I were included. We can divide column II into groups. group 0 group 1
0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
group 2
group 3
7 0111 14 1110
AAP

Column I group 0 group 1
0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0 0,8,1,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0 0,8,1,9 -00-
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 -00-0-0 -00-0-0
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 -00-0-0 -00-0-0
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 -00-0-0 -00-0-0
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 -00-0-0 -00-0-0
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 -00-0-0 -00-0-0
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 2,6,10,14 -00-0-0 -00-0-0 --10
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 2,6,10,14 2,10,6,14 -00-0-0 -00-0-0 --10 --10
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 2,6,10,14 2,10,6,14 -00-0-0 -00-0-0 --10 --10
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 2,6,10,14 2,10,6,14 -00-0-0 -00-0-0 --10 --10
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 2,6,10,14 2,10,6,14 -00-0-0 -00-0-0 --10 --10
group 2
group 3
7 0111 14 1110
No more combinations are possible, thus we stop here.
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 0,2,8,10 0,8,1,9 0,8,2,10 2,6,10,14 2,10,6,14 -00-0-0 -00-0-0 --10 --10
group 2
group 3
7 0111 14 1110
We can eliminate repeated combinations
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0 2,6,10,14 --10
Now we form f with the terms not checked f = acd
group 2
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0 2,6,10,14 --10
group 2
f = acd + abd
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0 2,6,10,14 --10
group 2
f = acd + abd + abc
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0 2,6,10,14 --10
group 2
f = acd + abd + abc + bc
group 3
7 0111 14 1110
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0 2,6,10,14 --10
group 2
group 3
7 0111 14 1110
f = acd + abd + abc + bc + bd
AAP

0 0000 1 0001 2 0010 8 1000 5 6 9 10 0101 0110 1001 1010
Column II
0,1 0000,2 00-0 0,8 -000 1,5 0-01 1,9 -001 2,6 0-10 2,10 -010 8,9 1008,10 10-0 5,7 01-1 6,7 0116,14 -110 10,14 1-10
Column III
0,1,8,9 -000,2,8,10 -0-0 2,6,10,14 --10
group 2
group 3
7 0111 14 1110
f = acd + abd + abc + bc + bd + cd
AAP

But, the form below is not minimized, using a Karnaugh map we can obtain:
f = acd + abd + abc + bc + bd + cd f ab a cd 00 01 11 10 00 01 1 11 c 10 b
1 d
AAP

f = acd + abd + abc + bc + bd + cd f ab a cd 00 01 11 10 00 01 1 11 c 10 b
1 d 1
AAP

f = acd + abd + abc + bc + bd + cd f ab a cd 00 01 11 10 00 01 1 11 c 10 1 b
1 d 1
AAP

f = acd + abd + abc + bc + bd + cd f ab a cd 00 01 11 10 00 1 1 01 1 11 c 10 1 b
1 1
1 d
AAP

f = acd + abd + abc + bc + bd + cd f ab a cd 00 01 11 10 00 1 1 01 1 11 c 10 1 1 b
1 1
1 d 1
AAP

But, the form below is not minimized. Using a Karnaugh map we can obtain:
1 1 1
1 d 1
AAP

F = abd
1 1 1
1 d 1
AAP

F = abd + cd
1 1 1
1 d 1
AAP

F = abd + cd + bc
1 1 1
1 d 1
AAP

What are the extra terms in the solution obtained with the Quine-McCluskey method?
f = acd + abd + abc + bc + bd + cd f ab a cd 00 01 11 10 00 1 1 01 1 1 1 1 1 b
F = abd + cd + bc
1 d 1 1
Thus, we need a method to 11 c eliminate this redundant terms 10 from the Quine-McCluskey solution.
AAP
The Prime Implicant Chart

The prime implicant chart is the second part of the Quine-McCluskey procedure. It is used to select a minimum set of prime implicants. Similar to the Karnaugh map, we first select the essential prime implicants, and then we select enough prime implicants to cover all the minterms of the function.
AAP
Prime Implicant Chart (Example)

Prime Implicants minterms 0 1 2 5 6 7 8 9 10 14 X X (0,1,8,9) bc X X X X X (0,2,8,10) bd X X X X X (2,6,10,14) cd X X (1,5) acd X X (5,7) abd X X (6,7) abc
Question: Given the prime implicant chart above, how can we identify the essential prime implicants of the function?
AAP

Similar to the Karnaugh map, all we have to do is to look for minterms that are covered by a single term.
AAP

Once a term is included in the solution, all the minterms covered by that term are covered. Therefore we may now mark the covered minterms and find terms that are no longer useful.

AAP

As we have not covered all the minterms with essential prime implicants, we must choose enough non-essential prime implicants to cover the remaining minterms.
AAP

What strategy should we use to find a minimum cover for the remaining minterms?
AAP

We choose first prime implicants that cover the most minterms. Should this strategy always work??
AAP

Therefore our minimum solution is:

f(a,b,c,d) = bc + cd + abd
AAP
Cyclic Prime Implicant Chart

F(a,b,c) = m(0, 1, 2, 5, 6, 7) minterms 0 1 2 5 6 7 (0,1) ab X X X (0,2) ac X X X (1,5) bc X X (2,6) bc X X (5,7) ac X X (6,7) ab
0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-
Which ones are the essential prime implicants in this chart? There is no essential prime implicants, how we proceed?
Prime Implicants

0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-
Also, all implicants cover the same number of minterms. We will have to proceed by trial and error.
F(a,b,c) = ab
AAP
Prime Implicants

0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-
Also, all implicants cover the same number of minterms. We will have to proceed by trial and error.
F(a,b,c) = ab + bc
AAP
Prime Implicants

0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-
Thus, we get the minimization:

F(a,b,c) = ab + bc + ac
AAP
Prime Implicants

0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-
Lets try another set of prime implicants.
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Prime Implicants

0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-

F(a,b,c) = ac
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Prime Implicants

0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-

F(a,b,c) = ac + bc
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Prime Implicants

0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-

F(a,b,c) = ac + bc+ ab
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Prime Implicants

0 1 2 5 6 7
000 001 010 101 110 111
0,1 0,2 1,5 2,6 5,7 6,7
000-0 -01 -10 1-1 11-
This time we obtain:

F(a,b,c) = ac + bc+ ab
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Prime Implicants

F(a,b,c) = ab + bc + ac F(a,b,c) = ac + bc+ ab
Which minimal form is better? Depends on what terms we must form for other functions that we must also implement. Often we are interested in examining all minimal forms for a given function. Thus we need an algorithm to do so.
Try Yourself: Simplify F=m(0,1,9,15,24,29,30) + d(8,11,31)
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F=m(0,5,7,8,9,12,13,23,24,25,28,29,37,40 ,42,44,46,55,56,57,60,61)
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The End
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Lecture-7
A.Amalin Prince
1
20-08-07
Objective : Combinational Logic & MSI Components
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Combinational Networks
Block diagram of a combinational network
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Analysis Procedure
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Design Procedure
From the specification of the circuit, determine the required number of inputs and out-puts and assign a symbol to each. Derive the truth table that defines the required relationship between inputs and outputs. Obtain the simplified Boolean function for each output as a function of the input variables. Draw the logic diagram and verify the corrections of the diagram.
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Code Converter
What is a code converter? Why it is needed? Design a BCD to Excess-3 code converter?
Possibilities? Step1:
A B C D W
Excess-3 Output
BCD Input
BCD to Excess-3 Code Converter
X Y Z
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Step 2
A 0 0 0 0 0 0 0 0 1 1
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BCD Input B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0
D 0 1 0 1 0 1 0 1 0 1
Excess-3 Output W X Y Z 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0
Step-3
W = m(5, 6, 7,8,9) + d (10,11,12,13,14,15) X = m(1, 2,3, 4,9) + d (10,11,12,13,14,15) Y = m(0,3, 4, 7,8) + d (10,11,12,13,14,15) Z = m(0, 2, 4, 6,8) + d (10,11,12,13,14,15)
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Step-4
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Binary Adder-Subtractor
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Half-Adder
Half-adder: Adds 2 bits, generates sum and carry Design using combinational design process
Step 2: Convert to equations
co = ab s = ab + ab (same as s = a xor b)
a b a b
Step 1: Capture the function

Inputs a b 0 0 0 1 1 0 1 1 Outputs co s 0 0 0 1 0 1 1 0
Step 3: Create the circuit
Half-adder
co s co s
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Full-Adder
Full-adder: Adds 3 bits, generates sum and carry Design using combinational design process
Step 1: Capture the function
Inputs a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 ci 0 1 0 1 0 1 0 1 Outputs co 0 0 0 1 0 1 1 1 s 0 1 1 0 1 0 0 1
Step 3: Create the circuit

a b ci
Full adder
Step 2: Convert to equations
co
co = abc + abc + abc + abc co = abc +abc +abc +abc +abc +abc co = (a+a)bc + (b+b)ac + (c+c)ab co = bc + ac + ab s = abc + abc + abc + abc s = a(bc + bc) + a(bc + bc) s = a(b xor c) + a(b xor c) s = a xor b xor c
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Implementation of Full adder using Two Half adders and an OR Gate

a b s
co
ci
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Half Subtractor
Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a difference bit D and a borrow out bit B-out. This operation is called half subtraction and the circuit to realize it is called a half subtractor. D(X,Y) = (1,2) Half Subtractor Truth Table D = XY + XY Outputs Inputs D = XY
X 0 0 1 1
X Y
Y 0 1 0 1
Half Subtractor
D B-out 0 0 1 1 1 0 0 0
D B-OUT
B-out(x, y, C-in) = (1) B-out = XY

X Y Difference D
B-out
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Full Subtractor
Subtracting two single-bit binary values, Y, Difference D XY B-in from a single-bit value X produces a B-in 00 01 difference bit D and a borrow out B-out 0 2 bit. This is called full subtraction. 1 0
X
11
6 7
10
4 5
1
B-in
Full Subtractor Truth Table

Inputs Outputs
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
B-in 0 1 0 1 0 1 0 1
D 0 1 1 0 1 0 0 1
B-out 0 1 1 1 0 0 0 1
S = XY(B-in) + XY(B-in) + XY(B-in) + XY(B-in) S = X Y (C-in)
Borrow B-out
XY B-in 0
00 0
1
01
2 3
11
6 7
10
4 5
1 1
Y
B-in
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S(X,Y, C-in) = (1,2,4,7) CS GC391/EEE GC391/INSTR GC391 C-out(x, y, C-in) = (1,2,3,7)

BITS-Pilani Goa Campus
B-out = XY + X(B-in) + Y(B-in)
Full Subtractor Circuit Using AND-OR

X X X Y Y B-in B-in
X Y B-in X Y B-in X Y B-in X Y B-in XYB-in XYB-in XYB-in
Difference D
B-in
XYB-in
X Y
XY
B-out
Full Subtractor
D
B-in
X B-in Y B-in
XB-in
B-out
YB-in
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Full Subtractor Circuit Using XOR
X Y B-in
Difference D
B-out
Full Subtractor
D
B-in
Y X B-in Y B-in
XY
XB-in
B-out
YB-in
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Method to Design an Parallel Adder: Imitate Adding by Hand

1 1 0
Create component for each column

Adds that columns bits, generates sum and carry bits
+
A: B:
1 1 1 1 + 0 1 1 0
1 0 1 0 1 1 A: 1 B: 0 b a ci co s 1 0 1 1 1 b a ci co s 1 0 1 1 b a ci co s 0 1 0 b a co s 1 SUM
Full-adders
Half-adder
Carry-Ripple Adder
Using half-adder and full-adders, we can build adder that adds like we would by hand Called a carry-ripple adder
4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output
5-bit output can be considered 4-bit sum plus 1-bit carry out
Can easily build any size adder

a3 b3 a b ci F A co s co a2 b2 a b ci F A s co a1 b1 a b ci F A s co a0 b0 a b HA s co
a3 a2 a1 a0
b3 b2b1b0
4-bit adder s3 s2 s1s0
co
s3
s2 (a)
s1
s0 (b)
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Carry-Ripple Adder
Using full-adder instead of half-adder for first bit, we can include a carry in bit in the addition
Will be useful later when we connect smaller adders to form bigger adders
a3 b3 a b ci F A co s co a2 b2 a b ci F A s co a1 b1 a b ci F A s co a0 b0 ci a b ci F A s co
a3 a2 a1 a0
b3 b2b1b0 ci
4-bit adder s3 s2 s1 s0
co
s3
s2 (a)
s1
s0 (b)
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Carry-Ripple Adders Behavior

000 a b ci F A co 0 s 0 00 0 a b ci F A co 0 s 0 10 0 a b ci F A co s 0 co2 1 000 a b ci F A co 0 s 0 100 a b ci F A co s 0 co1 1 co 0 0 0 0 a b ci F A s 0 1 1
Assume all inputs initially 0
000 a b ci F A co 0 s 0
0111+ 0001
(answer should be 01000)
a b ci F A co s 0 1 co0
Output after 2 ns (1 del y) FA a
Wrong answer -- something wrong? No -- just need more time for carry to ripple through the chain of full adders.

000 a b ci F A co s 0 0 100 a b ci F A c s o 0 1 100 1 a b ci F A c s o 1 c o2 0 101 a b ci F A c s o 1 0 (b) 101 a b ci F A c s o 1 co1 0 101 a b ci F A c s o 1 0 101 a b ci F A c s o 1 0 11 0 0111+0001 (answer should be 01000) a b ci F A c s o 1 0 11 0 Outputs after 4ns (2 FA delays)
000 a b ci F A co s 0 0
(c)
a b ci F A c s o 1 0 11 0
Outputs after 6ns (3 FA delays)
0 00 1 a b ci F A co s 0 1
(d) Correct answer appears after 4 FA delays

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a b ci F A c s o 1 0
Output after 8ns (4 FA delays)
Cascading Adders
a7a6a5a4 a3a2a1a0
b7b6b5b4 b3b2b1b0 ci
a3a2a1a0 a3a2a1a0
b3b2b1b0 b3b2b1b0 ci co a7.. a0 b7.. b0 ci
4-bit adder co co s3s2s1s0 s7s6s5s4
4-bit adder co s3s2s1s0 s3s2s1s0 (a)
8-bit adder s7.. s0
(b)
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Adder Example: DIP-Switch-Based Adding Calculator

Goal: Create calculator that adds two 8-bit binary numbers, specified using DIP switches
DIP switch: Dual-inline package switch, move each switch up or down Solution: Use 8-bit adder DIP switches
1 0
a7..a0
b7..b0 ci 0
8-bit carry-ripple adder co s7..s0
CALC LEDs
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Adder Example: DIP-Switch-Based Adding Calculator

To prevent spurious values from appearing at output, can place register at output
Actually, the light flickers from spurious values would be too fast for humans to detect -but the principle of registering outputs to avoid spurious values being read by external devices (which normally arent humans) applies here.
DIP switches 1 0
a7..a0
b7..b0 8-bit adder ci 0
co e clk
s7..s0
ld
8-bit register CALC LEDs
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Adder Example: Compensating Weight Scale

Weight scale with compensation amount of 0-7
To compensate for inaccurate sensor due to physical wear Use 8-bit adder 0 7 1
weight sensor 6 5 4 2 3
01000010
a7..a0
0 0 0 0 0 010 000 b7..b0
8-bit adder co s7..s0
ci
1 clk
ld
display register 01000010 01000100
Weight Adjuster
to display
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The End
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Lecture-8
A.Amalin Prince
1
22-08-07
AAP

000 a b ci F A co 0 s 0 00 0 a b ci F A co 0 s 0 10 0 a b ci F A co s 0 co2 1 000 a b ci F A co 0 s 0 100 a b ci F A co s 0 co1 1 co 0 0 0 0 a b ci F A s 0 1 1
Assume all inputs initially 0
000 a b ci F A co 0 s 0
0111+ 0001
(answer should be 01000)
a b ci F A co s 0 1 co0
Output after 2 ns (1 del y) FA a
Wrong answer -- something wrong? No -- just need more time for carry to ripple through the chain of full adders.

000 a b ci F A co s 0 0 100 a b ci F A c s o 0 1 100 1 a b ci F A c s o 1 c o2 0 101 a b ci F A c s o 1 0 (b) 101 a b ci F A c s o 1 co1 0 101 a b ci F A c s o 1 0 101 a b ci F A c s o 1 0 11 0 0111+0001 (answer should be 01000) a b ci F A c s o 1 0 11 0 Outputs after 4ns (2 FA delays)
000 a b ci F A co s 0 0
(c)
a b ci F A c s o 1 0 11 0
Outputs after 6ns (3 FA delays)
0 00 1 a b ci F A co s 0 1
(d) Correct answer appears after 4 FA delays

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a b ci F A c s o 1 0
Output after 8ns (4 FA delays)
Carry Look-Ahead Adders: Carry Adders Propagation

Gi = Ai Bi
Gi = Ai Bi
Pi = Ai Bi
Si = Pi Ci
Ci +1 = Gi + PCi i
Gi = Ai Bi
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For a 4-bit carry look-ahead adder the expanded expressions for all carry bits are given by:
C0 = input carry
C1 = G0 + P0C0
C2 = G1 + PC1 = G1 + P (G0 + P0C0 ) 1 1 = G1 + PG0 + P P0C0 1 1
C3 = G2 + P2C2 = G2 + P2G1 + P2 PG0 + P2 P P0C0 1 1
The additional circuits needed to realize the expressions are usually referred to as the carry look-ahead logic. Using carry-ahead logic all carry bits are available after three gate delays regardless of the size of the adder.
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Binary Subtractor
B3
A3 B2
A2
B1
A1 B 0
A0 1 1
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Adder Subtractor
0
B3
A3
B2
A2
B1
A1
B0
A0
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Adder Subtractor
1
B3
A3 B2
A2
B1
A1
B0
A0
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The End
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Lecture-9
A.Amalin Prince
1
24-08-07
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Binary Sum K
BCD Sum C S8 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 S4 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 S2 S1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
D e c i m a l A d d e r
Z8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0
Z4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
Z2 Z1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0 1
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1 CS GC391/EEE GC391/INSTR1GC391 0 1 0 BITS-Pilani Goa Campus 1 1 1 1 0
Decimal Adder
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Digital Comparator
A B
N-bit comparator
A>B
A=B
A<B
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XOR Comparator
Compare two numbers and decide if they are equal.
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Inputs A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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Outputs B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0
A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
Logic Diagram
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7485 4-bit Magnitude Comparator
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Truth table for a 74HC85 (7485, 74LS85) fourbit magnitude comparator.
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Function Table
Comparing Inputs AB A>B A=B Cascading Inputs If Outputs I(A>B) I(A=B) I(A<B) A>B A=B A<B 0 0 1 1 0 0 1 A<B 0 1 0 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1
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Design 74HC85 wired as a four-bit comparator
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Design an 8-bit comparator using 74HC85s
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Design a 5-bit comparator using one 7485.
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Decoder
A decoder accepts a set of inputs that represents a binary number and activates only the output that corresponds to that input number.
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General Decoder Diagram
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2.9
Decoders
Decoder: Popular combinational logic building block, in addition to logic gates
Converts input binary number to one high output
2-input decoder: four possible input binary numbers

So has four outputs, one for each possible input binary number
d0 0 0 i0 d1 i1 d2 d3 1 0 1
0 0
d0 i0 d1 i1 d2 d3
0 1 0
0 1
d0 i0 d1 i1 d2 d3
0 0 1
1 1
d0 i0 d1 i1 d2 d3
0 0
0
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Internal design
AND gate for each output to detect input combination
i1i0 i1i0 i1i0 i1i0
d0 d1 d2 d3
Decoder with enable e

Outputs all 0 if e=0 Regular behavior if e=1
i1 i0 1 1 i0 i1 e 1 d0 1 1 i0 i1 e 0
d0 d1 d2 d3
0 0 0 1
n-input decoder: 2n outputs
0 0 0 0
d1 d2 d3
A 3-to-8-line decoder.
Truth table Logic Symbol
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Logic Diagram
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Realization of the Boolean expressions f1(x2,x1,x0) = m(1,2,4,5) and f2(x2,x1,x0) = m(1,5,7) with a 3-to-8-line decoder and two or-gates.
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Realization of the Boolean expressions f1(x2,x1,x0) = m(0,1,3,4,5,6) = m(2,7) and f2(x2,x1,x0) = m(1,2,3,4,6) = m(0,5,7) with a 3-to-8-line decoder and two nor-gates.
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A decoder realization of f1(x2,x1,x0) = M(0,1,3,5) and f2(x2,x1,x0) = M(1,3,6,7) (a) Using output or-gates. (b) Using output nor-gates.
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A 3-to-8-line decoder using nand-gates.
Symbol
Truth table
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Logic Diagram
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Realization of the pair of maxterm canonical expressions f1(x2,x1,x0) = M(0,3,5) and f2(x2,x1,x0) = M(2,3,4) with a 3-to-8-line decoder and two and-gates.
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Realization of the Boolean expressions f1(x2,x1,x0) = M(0,1,3,4,7) = M(2,5,6) and f2(x2,x1,x0) = M(1,2,3,4,5,6) = M(0,7) with a 3to-8-line decoder and two nandgates.
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A decoder realization of f1(x2,x1,x0) = m(0,2,6,7) and f2(x2,x1,x0) = m(3,5,6,7) (a) Using output and-gates. (b) Using output nand-gates.
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And-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.
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Nand-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.
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Construct 416 decoder using 38 Decoders.
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Decoder Example
New Years Eve Countdown Display
Microprocessor counts from 59 down to 0 in binary on 6-bit output Want illuminate one of 60 lights for each binary number Use 6x64 decoder
4 outputs unused
essor c o r
2 10
0 1 0 0 0 0 10 00 00 00 00 00
i0 i1 i2 i3 i4 i5 d0 d1 d2 d3
21 0
0 0 1 0 01 10 00 00
0 1 2 3
op
ic
d58 e d59 d60 d61 6x64 d62 dcd d63
000 000
58 59
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The End
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Lecture-10
A.Amalin Prince
1
27-08-07
AAP
realize f1(x2,x1,x0) = M(0,1,3,5) and f2(x2,x1,x0) = M(1,3,6,7) (a) Using Decoder and output OR-gates. (b) Using Decoder and output NOR-gates.
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A 3-to-8-line decoder using nand-gates.
Symbol
Truth table
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Logic Diagram
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Realize the pair of maxterm canonical expressions f1(x2,x1,x0) = M(0,3,5) and f2(x2,x1,x0) = M(2,3,4) with a 3-to-8-line decoder and two AND-gates.
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Realize the Boolean expressions f1(x2,x1,x0) = M(0,1,3,4,7) = M(2,5,6) and f2(x2,x1,x0) = M(1,2,3,4,5,6) = M(0,7) with a 3to-8-line decoder and two NANDgates.
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realize f1(x2,x1,x0) = m(0,2,6,7) and f2(x2,x1,x0) = m(3,5,6,7) (a) Using Decoder and output ANDgates. (b) Using Decoder and output NAND-gates.
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And-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.
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Nand-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.
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Construct 416 decoder using 38 Decoders.
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Construct a 4-to16-line decoder from 2-to-4-line decoder.
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Encoders
Has several inputs only of which one is usually active at a time. Produces an N-bit output code dependent upon which input is activated. (opposite of decoding)
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8-Line-To-3-Line Encoder
Note that A0 is not internally connected (A1A7=1111111, then Q2Q1Q0=000 Only one input should be low. Example: If A3 = A5 =0, and all other are High, then Q2Q1Q0=0112 (=310), NOT ACCEPTABLE
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Priority Encoders
Priority encoders When 2 or more inputs are activated, the output code will correspond to the highest-numbered input. Example: If both A3 and A5 are low, then output code = 101 (510) If A6, A2, and A0 are all low, then output code = 110 (610) The 74148, 74LS148, and 74HC148 octal to binary priority encoders
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Truth table for a priority encoder

(assume active high input) Inputs D0 0 1 X X X
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Outputs D3 0 0 0 0 1 X X 0 0 1 1 Y X 0 1 0 1 V 0 1 1 1 1
D1 0 0 1 X X
D2 0 0 0 1 X
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Priority Encoders
74147 decimal-to-BCD priority encoder.
Nine active low inputs representing decimal 1 thru 9 Output: inverted BCD code corresponding to the highest numbered activated input. Outputs can be converted to normal BCD by putting each through an inverter. No A0. When all inputs are high, it corresponds to decimal 0
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Priority Encoders
The 74147 as a Decimal-to-BCD switch encoder
Example: a keyboard switch or a calculator Simultaneous key depressions will produce the BCD code for the highernumbered key.
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Priority Encoders
The 74148, 74LS148, and 74HC148 octal to binary priority encoders It has Enable Input (EI) and Enable Output (EO) that can be used to cascade two ICs producing a hexadecimal-to-binary encoder
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Gate Delays
In verilog delay is specified in terms of time units and the symbol #. Compiler directive timescale (Compiler directive start with the [backquote symbol]) Usage
timescale <reference_time_unit>/<time_precision> Example timescale 100 ns/1 ps
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// Description of circuit with delay timescale 1ns/100ps module cir_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C); endmodule
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Output of gates after delay

Time Units (ns) --------------10 20 30 40 50 Input A B C 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Output y e x 1 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1
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Self Study: System Tasks and Compiler Directives

Refer Ch.3.3 of Sameer Palnitkar
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The End
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Lecture-11
A.Amalin Prince
1
29-08-07
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Multiplexer
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Multiplexer (Mux)
Mux: Another popular combinational building block
Routes one of its N data inputs to its one output, based on binary value of select inputs
4 input mux needs 2 select inputs to indicate which input to route through 8 input mux 3 select inputs N inputs log2(N) selects
Like a railyard switch
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Multiplexers (Data Selectors)

A multiplexer (MUX) selects 1 out of N input data sources and transmits the selected data to a single output
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Mux Internal Design

21 i0 i1 s0 d i0 i1 s0 0 21 d i0 i1 s0 1 21 d i0 i1
i0 (1*i0=i0) 1 0 0
d
i0 (0+i0=i0)
2x1 mux
4 1 i0 i1 i2 i3 s1 s0 d
0 s0
i0 i1 d i2 i3
4x1 mux
s1
s0
Mux Example
City mayor can set four switches up or down, representing his/her vote on each of four proposals, numbered 0, 1, 2, 3 City manager can display any such vote on large green/red LED (light) by setting two switches to represent binary 0, 1, 2, or 3 Mayors switches Use 4x1 mux
1 i0 2 i1 i2 3 i3 s1 s0 d Green/ Red LED manager's switches 4x1 on/off
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Muxes Commonly Together -- N-bit Mux

a3 b3 i0 i1 2 1 d s0 a2 b2 a1 b1 a0 b0 s0 2 1 i0 d i1 s0 i0 i1 2 1 d s0 A B 4 4 I0 I1 s0 c3 s0 c2 c1 c0 4-bit 2x1 D Simplifying notation: 4 C is short for 4 C
2 1 i0 d i1 s0
Ex: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1 b0)

4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B
N-bit Mux Example
Four possible display items

Temperature (T), Average miles-per-hour (A), Instantaneous mph (I), and Miles remaining (M) -- each is 8-bits wide Choose which to display using two inputs x and y Use 8-bit 4x1 mux
Eight-input multiplexer: The 74151
AAP
74157 Quad Two-Input Mux
AAP
Multiplexers
Realize 8 to 1 mux using 4 to 1 mux.
AAP
Multiplexers
Implement 16 to 1 mux using 74HC151s
AAP
Multiplexer Applications
Applications include data selection, data routing, operation sequencing, parallel to serial conversion, waveform generation, and logic function generation.
Data routing Parallel to serial conversion Operation sequencing Logic function generation
AAP
Multiplexer Applications
Parallel to serial conversion
AAP
Multiplexer Applications cont.
Realization of a threevariable function using a 8-to-1-line multiplexer. (a) Three-variable truth table. (b) General realization.
AAP
Realization of f(x,y,z) = m(0,2,3,5). (a) Truth table. (b) 8-to-1-line multiplexer realization.
AAP
Realization of f(x,y,z) = m(0,2,3,5) using a 4-to-1-line multiplexer.
I0 I4
X
I1 I5
X
I2 I6
X
I3 I7
X
AAP
y

Z Z Z
I0 I2 I4 I6
I1 I3 I5 I7
AAP
The End
AAP
Lecture-12
A.Amalin Prince
1
31-08-07
AAP

Z Z Z
I0 I2 I4 I6
I1 I3 I5 I7
AAP
AAP
Implement F=m(1,2,7) using 74151
AAP
Demultiplexers (Data Distributors)
A demultiplexer (DEMUX) distributes a single input to multiple outputs.


A 1-line-to-8line demultiplexer
AAP
Demultiplexer Applications
serial to Parallel conversion
AAP

a) The 74ALS138 decoder can function as a demultiplexer with E1 used as the data input; (b) typical waveforms for a select code of A2A1A0 = 000 show that O0 is identical to the data input I on E1.
AAP
Implement full subtractor using demultiplexer

We know D(A,B,C)= m(1,2,4,7) and Bout(A,B,C)= m(1,2,3,7)
AAP
The End
AAP
Behavioral Modeling
AAP
Self Study: System Tasks and Compiler Directives
Refer Ch.3.3 of Sameer Palnitkar
AAP
Structured Procedures
Initial statement Always statement
AAP
Initial statement
module stimulus; reg x,y, a,b, m; Initial m= 1b0; //single statement; does not need to be grouped initial begin #5a =1b1; //multiple statements; need to be grouped #25 b=1b0; end initial begin #10x = 1b0; #25y = 1b1; end initial #50 $finish; endmodule
Always Statement
module clock_gen (output reg clock); //initialize clock at time zero initial clock = 1b0; //toggle clock every half-cycle (time period =20) always #10 clock =~clock Initial #1000 $finish; endmodule
AAP
Procedural Assignments
Updates values of reg, integer, real or time register variable or a memory element . The value placed on a variable will remain unchanged until another procedural assignment updates the variable with different value. Two types
Blocking Unblocking
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Blocking Assignments
reg x,y,z; reg [15:0] reg_a, reg_b; integer count; //All behavioral statements must be inside an initial or always block initial begin x =0;y =1; // scalar assignments count =0; //Assignment to integer variables reg_a = 16b0; reg_b =reg_a; //initialize vectors #15reg_a[2] =1b1; //Bit selectassignment with delay #10 reg_b[15:13] = {x,y,z} //Assign result of concatenation to //part select of a vector count = count +1; //Assiggnment to an integer (increment) end
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Nonblocking Assignments
reg x,y,z; reg[15:0]reg_a,reg_b; integer count; //All behavioral statements must be inside an initial or always block initial begin x =0;y =1;z =1; //Scalar assignments count = 0; //Assignment to integer variables reg_a =16b0; reg_b =reg_a; //Initialize vectors reg_a[2] <=#15 1b1; //Bit select assignment with delay reg_b[15:13]<=#10{x,y,z}; //Assign result of concatenation //to part select of a vector count <= count+1; //Assignment to an integer (increment)
AAP
Timing Controls
Delay-Based Timing Control Event-Based Timing Control Level-Sensitive Timing Control
AAP
Event-Based Timing Control

Regular event control Named event control Event OR control
AAP
Regular event control

@(clock)q =d; //q=d is executed whenever signal clock changes value @(posedge clock)q =d; //q =d is executed whenever signal clock does
//a positive transition (0 to 1,x or z, //x to 1,z to 1) @(negedge clock)q =d; //q =d is executed whenever signal clock does //a negative transition (1 to 0,x orz //z to 0,z to 0) q = @(posedge clock) d; //d is evaluated immediately and assigned //to q at the positive edge clock
AAP
Named event control

//This is an example of a data buffer storing data the //last packet of data has arrived. event received_data; //Define an event called recevied_data always@(posedge clock) //check at each clock edge
begin If (last_data_packet) //If this is the last data packet ->recevied_data; //trigger the event recevied_data end always@(recevied_data) //Await triggering of event recevied_data
//when event is triggered data in data buffer //use concatenation operator{}
data_buf ={data_pkt[10], data_pkt[1],data_pkt[2],data_pkt[3]};
AAP
Event OR control
//A level-sensitive latch with asynchronous reset always@(reset or clock or a) //wait for reset or clock or d to change begin if (reset) //if reset signal is high ,set q to 0. q =1b0; else if(clock) //if clock is high ,latch input q =d; end
AAP
//A level sensitive latch with asynchronous reset always@(reset, clock, d) //Wait for reset or clock or d to change begin if (reset) //if reset signal is high ,set q to 0. q = 1b0; else if(clock) //if clock is high ,latch input q =d; end //A positive edge triggered D flipflop with asynchronous falling //reset can be modeled as shown below always @(posedge clk,negedge reset) //Note use of comma operator if (!reset) q<=0; else q<=d;
Conditional Statements
if and else case statement casex, casez keywords Loops
while loop for loop repeat loop forever loop
while and forever are not synthesizable only used for simulation
AAP
Behavioral Modeling
Refer Ch.7 of Sameer Palnitkar http://www.asicworld.com/verilog/vbehave.html
AAP
Verilog code for a 2-to-4 Decoder

module dec2to4 (o,i); output [3:0]o; input [1:0]i; reg [3:0]o; Always @ (i) begin case(i) 2b00:0=4h0; 2b01:0=4h1; 2b10:0=4h2; 2b11:0=4h3; default: begin $display (error); 0=4h0; end endcase end endmodule
Verilog code for a 2-to-1 mux

module mux2to1 (a,b,select,out); input a,b,select; output out; reg out; always @ (select or a or b) if (select==1) out=a; else out=b; endmodule
The End
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Lecture-13
A.Amalin Prince
1
03-09-07
Objective : Digital Integrated Circuits
AAP
Switches
Electronic switches are the basis of binary digital circuits
Electrical terminology
A 5 4 .
Voltage: Difference in electric potential between two points

Analogous to water pressure
A 5 4 .
9V
Current: Flow of charged particles

Analogous to water flow
2 ohms 9V
Resistance: Tendency of wire to resist current flow

Analogous to water pipe diameter
0V 4.5 A
V = I * R (Ohms Law)
AAP
Switches
A switch has three parts
Source input, and output
Current wants to flow from source input to output
source input output control input control input off
Control input
Voltage that controls whether that current can flow
source input
on output
The amazing shrinking switch

1930s: Relays 1940s: Vacuum tubes 1950s: Discrete transistor 1960s: Integrated circuits (ICs)
Initially just a few transistors on IC Then tens, hundreds, thousands...
relay
(b)
discrete transistor vacuum tube
IC
quarter (to see the relative size) CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus
AAP
Moores Law
IC capacity doubling about every 18 months for several decades
Known as Moores Law after Gordon Moore, co-founder of Intel
Predicted in 1965 predicted that components per IC would double roughly every year or so
Book cover depicts related phenomena

For a particular number of transistors, the IC shrinks by half every 18 months
Notice how much shrinking occurs in just about 10 years Enables incredibly powerful computation in incredibly tiny devices
Todays ICs hold billions of transistors

The first Pentium processor (early 1990s) needed only 3 million
An Intel Pentium processor IC having millions of transistors
AAP
The Diode
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The Bipolar Transistor
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The CMOS Transistor

CMOS transistor
Basic switch in modern ICs
nMOS
A positive voltage here...
...attracts electrons here, turning the channel between source and drain into a conductor.
gate
gate oxide source drain

pMOS gate
conducts
IC package
does not conduct
(a)
IC
does not conduct conducts
Silicon -- not quite a conductor or insulator: Semiconductor

AAP
Boolean Logic Gates

Building Blocks for Digital Circuits
(Because Switches are Hard to Work With)
Logic gates are better digital circuit building blocks than switches (transistors)
Why?...
Characteristics of Digital ICs

Logic Level Fan-out Fan-in Power Dissipation Propagation delay Noise Margin
AAP
Logic Families
RTL DTL TTL ECL MOS CMOS Resister-Transistor Logic Diode-Transistor Logic Transistor-Transistor Logic Emitter-coupled Logic Metal-Oxide Semiconductor Complementary Metal-Oxide Semiconductor
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RTL Logic Family
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DTL Logic Family
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The End
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Lecture-14
A.Amalin Prince
1
05-09-07
AAP
TTL Logic Family

Transistor Transistor Logic (TTL) is one of the most popular and widespread of all logic families.
Very high number of SSI and MSI devices available in the market. Several number of sub-families that provide a wide range of speed and power consumption.
Sub families:
74xx : The original TTL family.
These devices had a propagation delay of 10ns and a power consumption of 10mW, and they were introduced in the early 60s.
AAP
TTL Logic Family

Sub families:
74Hxx : High speed.
Speed was improved by reducing the internal resistors. Note that this improvement caused an increase in the power consumption.
74Lxx : Low power.

Power consumption was improved by increasing the internal resistances, and the speed decreased.
AAP
TTL Logic Family

Sub families:
74Sxx : Schottky.
The use of Schottky transistors improved the speed. The power dissipation is less than the 74Hxx subfamily.
74LSxx : Low power Schottky.

Uses Schottky transistors to improve speed. High internal resistances improves power consumption.
AAP
TTL Logic Family

Sub families:
74ASxx : Advanced Schottky.
Twice as fast as 74Sxx with approximately the same power dissipation.
74ALSxx : Advanced Low power Schottky.

Lower power consumption and higher speed than 74LSxx .
74Fxx : Fast.
Performance is between 74ASxx and 74ALSxx.
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TTL Logic Family

Note that parameters like VOHMin , VIHMin , VILMax , and VOLMax are all the same for the different sub-families, but parameters like IILMax , IIHMax , IOLMax , and IOHMax may differ. Most TTL sub-families have a corresponding 54-series (military) version, and these series operate in a wider temperature and voltage ranges.
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TTL Logic Family

Output configurations
Open-collector output Totem-pole output Three-State (or tristate) output
AAP
Open collector output
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Open Collector Devices

Can be used to drive a load, such as LEDs, relays or other device. It is important to calculate a suitable resistor R. The current through the load must not exceed IOLMax .
AAP

Wired AND Logic When two or more open-collector outputs are tied together with an external pull-up resistor, the circuit behaves as if the gates were connected to an AND gate.
AAP

Common Bus Several open collector outputs may be connected together to create a common bus. The decoder, in the circuit shown below, selects which device outputs to the common bus by sending a high to the open collector output NAND gate connected to the chosen device. 1 0 1 0 10 1 1 0 01 10 10 0 1
AAP
TTL :
Faster Switching
+5 V
To obtain faster switching

Take advantage of input diodes being realised in terms of transistors change the circuit the following
R1
R2
Output A B C Q3 Q1
Now the charge on the base of Q1 is removed through transistor Q3 Results in a considerable reduction in the saturation delay time ts.
TTL :
Collector Capacitance
Another factor limiting transition speed is the collector capacitance

Must be charged as output voltage switches from low to high value only path for charging capacitance is via the collector resistor R2 Can reduce value of R2 increases charging speed
but also increases power dissipation Output circuit of this form known as passive pull-up circuit.
Output capacitance is pulled-up via passive element R2.
Passive Pull up Circuit

+5 V
R1
R2
Output A B C Q3 Q1
AAP
TTL : Active Pull Up Circuit (Totem-Pole Output)

An alternative which provides faster charging without increased power dissipation +5 V
the active pull-up circuit.
Totem-Pole
Q2 A B C Q4 Q3 Q1 R1 D1 Output
AAP
In output Low condition

The phase splitter transistor Q3 is in saturation The saturation current through R1 large enough to cause positive voltage drop
This positive voltage causes Q1 to saturate.
+5 V
Base of Q2 is at 0.9 V
due to VBE of Q1 at 0.7 V and VCE of Q3 at 0.2 V
A B C Q4 Q3
Q2 D1 Output Q1 R1
Because of D1,
emitter of Q2 is more positive than collector of Q3 Q2 is off
D1 in the circuit to ensure that Q2 is cut-off when Q1 saturated.

In output High condition

Output High due to one of the inputs dropping low Q3 and Q1 go into cut-off However output remains momentarily low as voltage across load capacitance cannot change instantaneously
+5 V
As soon as Q3 turns off Q2 conducts as its base is connected to VCC via resistor. Current needed to charge load capacitance causes Q2 to momentarily saturate output voltage rises with a time constant RC
AAP
In output High condition

But as the Resistance R is typically :
Collector resistance of 130 + resistance of the diode + saturation resistance of Q2 = 150
The value of R is << passive pull-up resistance used in the open collector circuit
Transition from Low to High is much faster

Changes in Capacitive load

As the capacitive load charges the output voltage rises and current in Q4 decreases brings transistor into active region when in steady state condition Q2 acts as an emitter follower as output terminal essentially at its emitter In contrast to other transistors Q2 is in active region
due to charging of capacitive loads
Thus the output circuit effectively acts as a two pole switch

switching the output between ground and the supply voltage
Metrics
VOH, VOL
VCC = +5 V but due to voltage drops in the output circuit
VOL = 0.2 V (VCE of Q1) VOH = 3.6 V (VCC- (VBE of Q2 +D1)) Speed
standard TTL is 3 times faster than DTL
Fan-out
8-10
NOTE
High inputs at A, B and C will have to supply a small diode leakage current , IIH = 10 uA If one or more inputs are low, substantial current will flow through input terminal to ground, IIL = 1 mA
AAP
Metrics :
With Q1 on
Vout will be a very low voltage
VOL depends on how much collector current Q1 conducts
With Q2 off

No current from +5 V supply through collector resistance. Can only come from inputs to which gate is connected. Q1 performs a current sinking action
called the pull-down transistor
With Q2 on
AAP
Q2 supplies input current required by Q4 of other load gates Performs current sourcing actions called the pull-up transistor
Advantages of the Totem Pole Output Stage

1.
Same output could be generated without Q2 and D1 and connecting resistor to collector of Q1.
However Q1 would conduct a fairly large current in saturation state
with Q2 in circuit no current through collector resistance in low state keeps power dissipation in circuit low.
AAP
Advantages of the Totem Pole Output Stage

2.
In the high state

Q2 acts as an emitter follower with associated low o/p impedance (10 ) Provides a short time constant for charging capacitive load on the output This action, known as active pull-up provides faster switching times
AAP
Disadvantages of the Totem Pole Output Stage

1.
In transition from Low High output state

Q1 turns off much faster than Q2 turns on
few nanoseconds when BOTH conduct.

relatively high current 30 40 mA will be drawn from supply. current spike generates noise on power supply distribution line if change in state is frequent power dissipation increases.
AAP
The End
Walter Schottky b. July 23, 1886, Zrich, Switzerland d. March 4, 1976, Pretzfeld, W.Germany
Lecture-15
A.Amalin Prince
1
07-09-07
AAP
TTL : Active Pull Up Circuit (Totem-Pole Output)

An alternative which provides faster charging without increased power dissipation +5 V
the active pull-up circuit.
Totem-Pole
AAP
The Standard TTL series Characteristics

The propagation delay of a transistor which goes into saturation. depends on two factors
Saturation delay (storage time delay) RC time constant
By reducing resistor values

reduces RC time constant decreases propagation delay
Trade-off is high power dissipation

lower resistance draws more current from the power supply
AAP
Low Power, 74L series

Similar as standard TTL But all resistor values have been increased. low power dissipation greater propagation delay
1 mW 33 nseconds
good for applications with low frequency, battery operated circuits

calculators etc.
AAP
High Speed, 74H series

Similar as standard TTL But all resistor values have been reduced. Emitter follower has been replaced by a double emitter follower (Darlington Pair)
but
faster switching propagation delay increased power dissipation
6 nseconds 23 mW
AAP
How to increase speed ?

Whatever is done to the value of the resistors Speed is ultimately limited by the time required to pull the output transistors out of saturation.
74, 74L and 74H series all operate with saturated switching many of the transistors, when conducting will be in a saturated condition As has been seen this causes a saturation delay (storage delay), when switching from ON to OFF limits the circuits switching speed.
AAP
Schottky TTL, 74S series

Can this be improved ?
In Schottky TTL (STTL) Transistors kept out of saturation by using Schottky barrier diodes (SD) Formed by a junction of a metal and semiconductor
conventional diode with a junction of p-type and n-type semiconductor material

SD connected between the base and the collector Do not allow the transistors to go as deeply into saturation SD has a forward voltage drop of 0.4V
AAP

When the Collector-Base junction becomes forward biased at the on-set of saturation
SD will conduct, diverting some input current away from base. this has effect of reducing the excess base current. decreases saturation (storage time) delay at turn-off
74S00 NAND has average propagation delay of 3 nsecs

twice as fast as the 74H00 makes the 74H series redundant nowadays
AAP

+5 V
55 2.8k 760
Q3 A B C Q1 Q2 Q4
3.5k
Output Q5
370
350
Q6
AAP

Schottky Transistor used
3 Schottky diodes inserted to limit negative inputs values no diode in the Totem-pole output Circuit also uses smaller resistor values to improve switching times Improves the circuit average power dissipation to 20 mW
NOTE All transistor are Schottky Transistors. Q4 is not required to be a Schottky as it does not saturate but stays in active region
AAP

New combination of Q3 and Q6 still gives the two VBE drops
necessary to prevent Q4 from conducting when the output is low.
Combination comprises a double-emitter follower (Darlington pair)

Provides high current gain and extremely low resistance needed during the low-to high swing of the output rapid output rise time when switching ON-to-OFF
Results in a decrease in propagation delay.
AAP
Low Power Schottky TTL, 74LS series

74 LS is a low powered version of the 74S series uses Schottky clamped configuration but with larger resistor values then 74S Low circuit power requirements but at the expense of increase in switching times. Power Dissipation 2 mW Propagation Delay 9.5 nseconds
This is the mainstay of the TTL family Found in nearly all new designs that do not require max speed.
AAP
Advanced Schottky TTL, 74AS series

As a result of the recent development in IC design and manufacturing process
High speed Schottky diodes
Power Dissipation Propagation Delay
8 mW 1.7 nseconds
AAP
Advanced Low-Power Schottky TTL, 74ALS series

Improvement in both power and speed. Power Dissipation Propagation Delay 1.2 mW 4 nseconds
This series has the lowest speed-power product of the TTL series very close to the lowest gate power dissipation (c.f. 74L) This will eventually replace 74LS as the most widely used TTL series.
AAP
Comparison of TTL Series Characteristics

74 Performanc e Ratings
Propagation Delay (nSec) Power Dissipation (mW) 9
74L 33 1
74H 6
23
74S 3
20
74LS 9.5
2
74AS 1.7
8
74 ALS 4
1.2
10
Speed Power (pJ) Max Clock rate (MHz) Fan-out (same series)
90
33
138
60
19
13.6
4.8
35 10
3 20
50 10
125 20
45 20
200 40
70 20
Voltage Parameters
VOH(min) VOL(max) VIH(min) VIL(max)
2.4 0.4 2.0 0.8
2.4 0.4 2.0 0.7
2.4 0.4 2.0 0.8
2.7 0.5 2.0 0.8
2.7 0.5 2.0 0.8
2.5 0.5 2.0 0.8
2.5 0.4 2.0 0.8
AAP
All of the performance ratings are for a NAND gate in each series.
Tri-State Devices
This kind of device include a third electrical state called high impedance or Hi-Z. This new state is controlled by an input control line called output enable. When this input is asserted the device behaves like a normal gate, otherwise, the output behaves like an open circuit.
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Tri-state Inverter
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Tri-State Devices
One application of tri-state devices is to be used to connect several devices to a single bus. When changing which output is connected to bus one must ensure that all outputs must first go into the hi-Z state thus avoiding the possibility that two outputs would be connected to the bus simultaneously.
AAP
CMOS Logic Family

Complementary metal oxide semiconductor (CMOS) replaced TTL devices in the 90s due to advances in the design of MOS circuits made in mid 80s. Advantages:
Operate with a wider range of voltages that any other logic family. Has high noise immunity. Dissipates very low power at low frequencies. It requires an extremely low driving current. High fanout.
AAP
CMOS Logic Family

Disadvantages:
Power consumption increases with frequency. Susceptible to ESD - electro-static discharges.
Sub-families:
40xx : Original CMOS family.
Fairly slow, but it has a low power dissipation.
74HCxx : High speed CMOS.

Better current sinking and sourcing than 40xx. It uses voltage supply between 2 and 6 volts. Higher voltage higher speed. Lower voltage lower power consumption.
AAP
CMOS Logic Family

Sub-families:
74HCTxx : High speed CMOS, TTL compatible.
Better current sinking and sourcing than 40xx. It uses voltage supply of 5V. Compatible with TTL family.
74ACxx : Advanced CMOS.

Very fast. It can source and sink high currents. Not TTL compatible.
74ACTxx : Advanced CMOS, TTL compatible.

Same as 74ACxx, but it is compatible with TTL family.
AAP
Logic Families
Sub-families:
74FCTxx : Fast CMOS, TTL compatible.
It is faster and has lower power dissipation than the 74ACxx and 74ACTxx sub-families. Compatible with TTL family.
Prefixes, usually added to device designation to identify the manufacturer.

SN : Texas Instrument. MN : Motorola. DM : National N : Signetics P : Intel H : Harris AMD : Advanced Micro Devices
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Logic Families
Prefixes, usually added to device designation to identify the manufacturer.
SN : Texas Instrument. MN : Motorola. DM : National N : Signetics P : Intel H : Harris AMD : Advanced Micro Devices
Suffixes, identifies the packaging.

N : Plastic DIP (dual in-line package) P : Plastic DIP J : Ceramic DIP W : Ceramic flat package. D : Plastic small outline package
AAP
CMOS logic Circuit
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Transmission Gate (TG)
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Bilateral Switch
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Components of a Simulation
Design Block Stimulus Block
AAP
Test Bench
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//designblock module mm(a,b,s, o); input a,b,s; output o; assign o=s ? a:b; endmodule
Example (2-1 Mux)
//stimulus block module testmux; reg ta,tb,ts; wire y; mm mux (ta,tb,ts,y); //instantiate mux initial begin ts=1;ta=0;tb=1; #10 ta=1;tb=0; #10 ts=0; #10 ta=0;tb=1; end initial $monitor("s=%b a=%b b=%b o=%b time=%0d", ts,ta,tb,y,$time); endmodule
The End
Walter Schottky was a German physicist whose research in solid-state physics and electronics yielded many effects and devices that now bear his name (Schottky effect, Schottky barrier, Schottky diod).
Walter Schottky b. July 23, 1886, Zrich, Switzerland d. March 4, 1976, Pretzfeld, W.Germany
Lecture-16
A.Amalin Prince
A.Amalin Prince EEE/INSTR Group CS GC391/EEE GC391/INSTR GC391 Digital Electronics and Computer Organization BITS-Pilani Goa Campus
10-09-07
Objective : Sequential Logic,
Latches and Flip-Flops
Sequential Circuits
Introduction
Sequential circuit
Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs
Stores bits, also known as having state
a b 1 1 0 Combinational digital circuit F
Simple example: a circuit that counts up in binary
In sequential Logic, we will:

Design a new building block, a flip-flop, that stores one bit Combine that block to build multi-bit storage a register Describe the sequential behavior using a finite state machine Convert a finite state machine to a controller a sequential circuit having a register and combinational logic
i s a n s i e z
a b
1 0 Sequential digital circuit
Must know sequence of past inputs to know output
Example Needing Bit Storage

Call button Blue light Bit Storage
Flight attendant call button

Press call: light turns on
Stays on after button released
Cancel button
1. Call button pressed light turns on

Call button Cancel button Blue light Bit Storage
Press cancel: light turns off Logic gate circuit to implement this?
Call Cancel Q
2. Call button released light stays on
Doesnt work. Q=1 when Call=1, but doesnt stay 1 when Call returns to 0 Need some form of feedback in the circuit
Call button Cancel button
Blue light Bit Storage
3. Cancel button pressed light turns off
First attempt at Bit Storage

We need some sort of feedback
Does circuit on the right do what we want?
No: Once Q becomes 1 (when S=1), Q stays 1 forever no value of S can bring Q back to 0
S 0 0 t 0Q S 1
0 t 0Q
S t
S 1 0 t
1Q
S 1 1 t
1Q
S 0 1 t
1Q
S t Q
1 0 1 0 1 0
Bit Storage Using an SR Latch

Does the circuit to the right, with cross-coupled NOR gates, do what we want?
Yes! How did someone come up with that circuit? Maybe just trial and error, a bit of insight...
R (reset)
S=0 0 1 R=1 1 t S=0 0 1 R=0 1 t S=1 1 0 R=0 0 t S=0 1 0 Q R=0 0 t
0 0
. l e c a R
S (set)
SR latch
Recall
1
1 X
0 Q
0 Q
1 0 R1 0 t 1 0 1 Q 0
Example Using SR Latch for Bit Storage

SR latch can serve as bit storage in previous example of flight-attendant call button
Call=1 : sets Q to 1
Q stays 1 even after Call=0
Call but ton
Blue ligt h Bit S torage
Cancel=1 : resets Q to 0
But, theres a problem...

Cancel
but ton
Blue ligt h Q R
Problem with SR Latch

Problem
If S=1 and R=1 simultaneously, we dont know what value Q will take
1 S=1 0 0 t S=0 0 1 t S=0 1 0 t S R t Q 0 0 1 0 1 0 1
0 R=1
0 Q R=0
1 Q R=0
0 Q
Q may oscillate. Then, because one path will be slightly longer than the other, Q will eventually settle to 1 or 0 but we dont know which.
t Q
1 0 1 0
Problem with SR Latch

Problem not just one of a user pressing two buttons at same time Can also occur even if SR inputs come from a circuit that supposedly never sets S=1 and R=1 at same time
But does, due to different delays of different paths
1
X Arbitrary circuit S SR latch
X 0 1 Y
Q Y R
0 1 S
The longer path from X to R than to S causes SR=11 for short time could be long enough to cause oscillation
R
0 SR= 11 1 0
SR NOR Latch
SR Latch with NAND Gates (SR Latch)
Solution: Level-Sensitive SR Latch

Add enable input C as shown
Only let S and R change when C=0
Enure circuit in front of SR never sets SR=11, except briefly due to path delays
S Level-sensitive SR latch S1
Change C to 1 only after sufficient time for S and R to be stable When C becomes 1, the stable S and R value passes through the two AND gates to the SR latchs S1 R1 inputs.
Level-sensitive SR latch X S
C Q R R1
S
Though SR=11 briefly...

S
1
C R
Q Q
S1
1 R0
Clk C
Level-sensitive SR latch symbol
C
Q R R1
1 0
1
S1
0
1
R1 0
...S1R1 never = 11
Clock Signals for a Latch
How do we know when its safe to set C=1?

Most common solution make C pulse up/down
C=0: Safe to change X, Y C=1: Must not change X, Y Well see how to ensure that later
X Level-sensitive SR latch S S1 C Q R Y R1
Clock signal -- Pulsing signal used to enable latches

Because it ticks like a clock
Clk
Sequential circuit whose storage components all use clock signals: synchronous circuit
Most common type Asynchronous circuits important topic, but left for advanced course
Clocks
Clock period: time interval between pulses

Above signal: period = 20 ns
Freq 100 GHz 10 GHz 1 GHz 100 MHz 10 MHz Period 0.01 ns 0.1 ns 1 ns 10 ns 100 ns
Clock cycle: one such time interval

Above signal shows 3.5 clock cycles
Clock frequency: 1/period

Above signal: frequency = 1 / 20 ns = 50 MHz
1 Hz = 1/s
The End
Lecture-17
A.Amalin Prince
12-09-07
Objective :Synchronous Sequential Logic
Flip-Flops and Register
Solution: Level-Sensitive SR Latch

Add enable input C as shown
Only let S and R change when C=0
Enure circuit in front of SR never sets SR=11, except briefly due to path delays
S Level-sensitive SR latch S1
Change C to 1 only after sufficient time for S and R to be stable When C becomes 1, the stable S and R value passes through the two AND gates to the SR latchs S1 R1 inputs.
Level-sensitive SR latch X S
C Q R R1
S
Though SR=11 briefly...

S
1
C R
Q Q
S1
1 R0
Clk C
Level-sensitive SR latch symbol
C
Q R R1
1 0
1
S1
0
1
R1 0
...S1R1 never = 11
Clock Signals for a Latch
How do we know when its safe to set C=1?

Most common solution make C pulse up/down
C=0: Safe to change X, Y C=1: Must not change X, Y Well see how to ensure that later
X Level-sensitive SR latch S S1 C Q R Y R1
Clock signal -- Pulsing signal used to enable latches

Because it ticks like a clock
Clk
Sequential circuit whose storage components all use clock signals: synchronous circuit
Most common type Asynchronous circuits important topic, but left for advanced course
Clocks
Clock period: time interval between pulses

Above signal: period = 20 ns
Freq 100 GHz 10 GHz 1 GHz 100 MHz 10 MHz Period 0.01 ns 0.1 ns 1 ns 10 ns 100 ns
Clock cycle: one such time interval

Above signal shows 3.5 clock cycles
Clock frequency: 1/period

Above signal: frequency = 1 / 20 ns = 50 MHz
1 Hz = 1/s
Level-Sensitive D Latch
SR latch requires careful design to ensure SR=11 never occurs D latch relieves designer of that burden
Inserted inverter ensures R always opposite of S
D 1 0 1 0 1 0 1 0 1 0
D C Q Q
D latch S
C Q R
D latch symbol
Problem with Level-Sensitive D Latch

D latch still has problem (as does SR latch)
When C=1, through how many latches will a signal travel? Depends on for how long C=1
Clk_A -- signal may travel through multiple latches Clk_B -- signal may travel through fewer latches
Hard to pick C that is just the right length

Can we design bit storage that only stores a value on the rising edge of a clock signal?
Y D1 C1 Clk Clk_A
rising edges
Q1
D2 C2
Q2
D3 C3
Q3
D4 C4
Q4
Clk
Clk_B
D Flip-Flop
Flip-flop: Bit storage that stores on clock edge, not level One design -- master-servant (master-slave)
Two latches, output of first goes to input of second, master latch has inverted clock signal So master loaded when C=0, then servant when C=1 When C changes from 0 to 1, master disabled, servant loaded with value that was at D just before C changed -- i.e., value at D during rising edge of C
D flip-flop D latch D Dm Cm master Clk
rising edges
Clk
Note: Hundreds of different flip-flop designs exist
Clk D/Dm Cm
D latch Ds Cs Qs Qs
Qm
Q Q
Qm/Ds Cs Qs
servant
D Flip-Flop
D
The triangle means clock input, edge triggered
Q Q
Q Q
Internal design: Just invert servant clock rather than master
Symbol for rising-edge triggered D flip-flop

rising edges
Clk
Symbol for falling-edge triggered D flip-flop

falling edges
Clk
D Flip-Flop
Solves problem of not knowing through how many latches a signal travels when C=1
In figure below, signal travels through exactly one flip-flop, for Clk_A or Clk_B Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously -- then all four no longer pay attention to their input, until the next rising edge. Doesnt matter how long Clk is 1.
T n i s e a d c h
D1
Q1
D2
Q2
D3
Q3
D4
Q4
i l f
l o
o l p f
Two latches inside each flip-flop

t c h e s
Clk Clk_A Clk_B
D Latch vs. D Flip-Flop

Latch is level-sensitive: Stores D when C=1 Flip-flop is edge triggered: Stores D when C changes from 0 to 1
Saying level-sensitive latch, or edge-triggered flip-flop, is redundant Two types of flip-flops -- rising or falling edge triggered.
Comparing behavior of latch and flip-flop:

Clk D3 Q (D latch) 1 2
4 7
6 8
Q (D flip-flop)
10
Flight-Attendant Call Button Using D Flip-Flop

D flip-flop will store bit Inputs are Call, Cancel, and present value of D flip-flop, Q Truth table shown below
Flight attendant call-button system
Blue light
Preserve value: if Q=0, make D=0; if Q=1, make D=1 Cancel -- make D=0 Call -- make D=1 Lets give priority to Call -- make D=1
Circuit derived from truth table, using Chapter 2 combinational logic design process
Call button
Call
Cancel
button
Cancel
Clk
Blue light
Bit Storage Summary

SR latch S (set) Level-sensitive SR latch S S1 C Q R (reset) R R1 Q R D latch D C Q Clk S D D latch DmQm C m master D flip-flop D latch Ds Qs Cs Qs servant Q Q
Feature: S=1 sets Q to 1, R=1 resets Q to 0. Problem: SR=11 yield undefined Q.
Feature: S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden.
Feature: SR cant be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store.
Feature: Only loads D value present at rising clock edge, so values cant propagate to other flip-flops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR but gate count is less of an issue today.
We considered increasingly better bit storage until we arrived at the robust D flip-flop bit storage
More on Flip-Flops
Other flip-flop types
SR flip-flop: like SR latch, but edge triggered JK flip-flop: like SR (S J, R K)
But when JK=11, toggles 1 0, 0 1
T flip-flop: JK with inputs tied together

Toggles on every rising clock edge
Previously utilized to minimize logic outside flip-flop

Today, minimizing logic to such extent is not as important D flip-flops are thus by far the most common
SR Flip-Flop
D Flip-Flop
JK Flip-Flop
T Flip-Flop
Flip-Flop Set and Reset Inputs (Asynchronous inputs)

Some flip-flops have additional inputs
Synchronous reset: clears Q to 0 on next clock edge Synchronous set: sets Q to 1 on next clock edge Asynchronous reset: clear Q to 0 immediately (not dependent on clock edge)
Example timing diagram shown
D Q Q
D Q Q
D AR Q Q
AR
AS
cycle 1 clk
cycle 2
cycle 3
cycle 4
D AR
Asynchronous set: set Q to 1 immediately
D Flip-Flop with Asynchronous reset
Active Low Inputs

Weve assumed input action occur when input is 1
Some inputs are instead active when input is 0 -- active low Shown with inversion bubble So to reset the shown flip-flop, set R=0. Else, keep R=1.
Q Q
Basic Register
Typically, we store multi-bit items
e.g., storing a 4-bit binary number
Register: multiple flip-flops sharing clock signal

From this point, well use registers for bit storage
No need to think of latches or flip-flops But now you know whats inside a register
I3 I2 I1 I0 4-bit register D Q clk Q3 Q2 Q1 Q0 D Q D Q D Q
I3 I2 I1 I0 reg(4)
Q3 Q2 Q1 Q0
Example Using Registers: Temperature Display

Temperature history display
Sensor outputs temperature as 5-bit binary number Timer pulses C every hour Record temperature on each pulse, display last three recorded values
Present Display 1 hour ago Display 2 hours ago Display
t u
r o s n e
e m p
x4 x3 x2 x1 x0 C
a4 a3 a2 a1 a0
b4 b3 b2 b1 b0
c4 c3 c2 c1 c0
TemperatureHistoryStorage
We will design later
timer
(In practice, we would actually avoid connecting the timer output C to a clock input, instead only connecting an oscillator output to a clock input.)
Example Using Registers: Temperature Display

Use three 5-bit registers
a4 a3 a2 a1 a0 x4 x3 x2 x1 x0 C I4 I3 I2 I1 I0 Ra Q4 Q3 Q2 Q1 Q0 I4 I3 I2 I1 I0 Rb Q4 Q3 Q2 Q1 Q0 b4 b3 b2 b1 b0 I4 I3 I2 I1 I0 Rc TemperatureHistoryStorage Q4 Q3 Q2 Q1 Q0 c4 c3 c2 c1 c0
x4...x0 C Ra Rb Rc
15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27
0 0 0
18 0 0
21 18 0
24 21 18
25 24 21
26 25 24
27 26 25
The End
Lecture-18
A.Amalin Prince
14-09-07
Registers and Shift Registers
Introduction to datapath components

Chapters 4 & 5: Introduced increasingly complex digital building blocks
Gates, multiplexors, decoders, basic registers, and controllers (yet to be discussed)
Controllers good for systems with control inputs/outputs

Control input: Single bit (or just a few), representing environment event or state
e.g., 1 bit representing button pressed
Data input: Multiple bits collectively representing single entity

e.g., 7 bits representing temperature in binary
i s a n s i
Need building blocks for data

Datapath components, aka register-transfer-level (RTL) components, store/transform data
e z
Put datapath components together to form a datapath
Here I introduce numerous datapath components, and simple datapaths

In chapter 8 : will combine controllers and datapaths into processors
Registers
Can store data, very common in datapaths Basic register : Loaded every cycle
Useful for implementing FSM -- stores encoded state For other uses, may want to load only on certain cycles
b Combinational n1 logic n0 s1 s0 clk State register x
load
clk
I3
I2
I1
I0 4-bit register
D Q
D Q
D Q
D Q
i s
a n s i
I3 I2 I1 I0 reg(4)
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
e
Basic register loads on every clock cycle How extend to only load on certain cycles?
Register with Parallel Load
Register with Parallel Load

Add 2x1 mux to front of each flip-flop Registers load input selects mux input to pass
Either existing flip-flop value, or new value to load
I3 load 1 0 2 1 D Q Q3 I2 1 0 I1 1 0 I0 1 0 I3 load D Q Q2 (a) I3 I2 1 0 D Q Q2 I1 1 0 D Q Q1 I0 1 0 D Q Q0 (b) I3 I2 1 0 D Q Q2 I1 1 0 D Q Q1 D Q Q1 D Q3 Q Q0 (c) I0 1 0 D Q Q0 Q2 Q1 Q0 I2 I1 I0
load = 0
1 0 D Q Q3
load = 1
1 0 D Q Q3
Basic Example Using Registers

a3 a2 a1 a0 1 clk ld I3 I2 I1 I0
This example will show how registers load simultaneously on clock cycles
Notice that all load inputs set to 1 in this example -- just for demonstration purposes
R0 Q3 Q2 Q1 Q0
ld I3
I2
I1
I0 R1
1 ld I3
I2
I1
I0 R2
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Basic Example Using Registers

clk (a)
given
1 a3..a0 1111 0001
2 1010
R 0 R 1 R 2
a3 a2 a1 a0 1 ld I3 I2 I1 I0
???? ???? ????
1111 ???? ???? 1111>0001 1111 R 0
0001 1111 0000 0001>1010 0001 R 0
1010 0001 1110 1010 1010 R 0
1010 1010 0101 1010 1010 R 0 1010
1010 1010 0101
>1111 ???? R 0
clk
R0
Q3 Q2 Q1 Q0
(b)
1010 R 0
???? R 1
1 ld I3 I2 I1 I0 1 ld I3 I2 I1 I0
???? R 2
???? R 1
???? R 2
1111 R 1
0000 R 2
0001 R 1
1110 R 2
1010 R 1
0101 R 2
1010 R 1
0101 R 2
R1
Q3 Q2 Q1 Q0
R2
Q3 Q2 Q1 Q0
Register Example using the Load Input:

Weight Sampler
Scale has two displays
Present weight Saved weight Useful to compare present item with previous item
Scale Weight Sampler
0011 0
Save 2 3 pounds Present weight b clk
Use register to store weight

Pressing button causes present weight to be stored in register
Register contents always displayed as Saved weight, even when new present weight appears
load
I3 I2 I1 I0 Q3 Q2 Q1 Q0
0011
3 pounds Saved weight
Register Example: Temperature History Display

Recall example
Timer pulse every hour Previously used as clock. Better design only connects oscillator to clock inputs -- use registers with load input, connect to timer pulse.
a4 a3 a2 a1 a0
a4 a3 a2 a1 a0
b4 b3 b2 b1 b0 I4 Q4 I3 Q3 I3 Q3 I2 Q2 I2 RbQ2 I1 Q1 I1 Q1 I0 Q0 I0 Q0 Rb
b4 b3 b2 b1 b0
I4 Q4 I3 Q3 I3 Q3 I2 Q2 Q2 I2 Rc I1 Q1 I1 Q1 I0 Q0 I0 Q0 Rc
c4 c3 c2 c1 c0
c4 c3 c2 c1 c0
t4 x4 t3 x3 t2 x2 t1 x1 t0
x0
I4 Q4 I4 Q4 I3 Q3 I3 Q3 I2 Q2 I2 Ra Q2 I1 Q1 I1 Q1 I0 Q0
I0 Q0
I4
Q4
I4
Q4
Clk oscC C timer
ld
Ra
ld
ld
new line
Register Example: Above-Mirror Display

Shorthand notation
0001010
e r t
8 d0 2 4 a0
Loaded on clock edge

load reg0 T
i m T
p o u m
a l
t o h m e a 'c s r
Lecture-11 example: Four simultaneous values from cars computer To reduce wires: Computer writes only 1 value at a time, loads into one of four registers
Was: 8+8+8+8 = 32 wires Now: 8 +2+1 = 11 wires
0 1
d1 i0 i1 d2
8 load reg1
i0 8-bit 41
0001010
A 8
i1 d i2 8
a1
load reg2
I 8
load
d3
load reg3
M 8 i3 s1 s0 x y
8
a b h e t o r r o d s r i p l o v a e y
Register Example: Computerized Checkerboard

Each register holds values for one column of lights
1 lights light
LED lit LED 1 0 1 0 0 0 1 0 R7 d7 8 D microprocessor
Microprocessor loads one register at a time

Occurs fast enough that user sees entire board change at once
R6 d6 e
R5 d5
R4
R3
R2
R1
R0
Q I
R0
load
10100010
d4 d3 i2 i1 i0
d2 d1 d0 3 8 decoder
from from microprocessor decoder (b)
(a)
Register Example: Computerized Checkerboard

LED lit LED
R7
R6
R5
R4
R3
R2
R1
R0
10100010 10100010 10100010 10100010 01000101 01000101 01000101 01000101
D i2,i1,i0 e clk
10100010 000 (R0)
010000101 001 (R1)
10100010 010 (R2)
010000101 011 (R3)
10100010 100 (R4)
010000101 101 (R5)
10100010 110 (R6)
010000101 111 (R7)
Shift Register
Shift right
Move each bit one position right Shift in 0 to leftmost bit
1 1 0 1 0 0 1 1 0 Register contents before shift right Register contents after shift right
Q: Do four right shifts on 1001, showing value after each shift A: 1001 (original) 0100 0010 0001 0000
Implementation: Connect flip-flop

output to next flip-flops input
shr_in
Shift Register
To allow register to either shift or retain, use 2x1 muxes
shr: 0 means retain, 1 shift shr_in: value to shift in
May be 0, or 1
Note: Can easily design shift register that shifts left instead
shr_in shr 1 0 2 1 D Q Q3 1 0
shr=1
1 0
1 0
1 0 2 1 D Q
1 0 D Q Q2 (b)
1 0 D Q Q1
1 0 D Q Q0
D Q Q2 (a)
D Q Q1
D Q Q0
Q3
shr_in shr Q3
Q2 (c)
Q1
Q0
Rotate Register
1 1 0 1 Register contents before shift right Register contents after shift right
Rotate right: Like shift right, but leftmost bit comes from rightmost bit
1 1 1 0
Shift Register Example: Above-Mirror Display

11 wir es
C
From the car's central computer
8 load reg0 T
Earlier example: 8 +2+1 = 11wires from cars computer to above-mirror displays four registers
Better than 32 wires, but 11 still a lot -want fewer for smaller wire bundles
d0
To the above mirror display
2 4 d1 load reg1 A
i0 8 8-bit 4 1 i1 8 load reg2 I i2 8 d 8
a0
i0
a1
i1
d2
e load
d3
load
reg3
M 8 i3 s1 s0 x y
Use shift registers

Wires: 1+2+1=4 Computer sends one value at a time, one bit per clock cycle
Note: this line is 1 bit, rather than 8 bits like before x y c shr_in shr reg0 d0 T s1 s0 i0 2 4 8 shr_in 41 shr reg1 d1 A a0 i0 i1 8 i1 a1 shr_in d shr reg2 d2 8 I i2 e d3 shr_in shr reg3 8 M i3 8
shift
Multifunction Registers
Many registers have multiple functions
Load, shift, clear (load all 0s) And retain present value, of course
Functions:
s1 0 0 1 1
I0 0 3210 shr_in s1 s0 I3 I2 I1 I0
Easily designed using muxes

Just connect each mux input to achieve desired function
shr_in I3 0 s1 3 2 1 0 s0 4 1 D Q Q3
s0 0 1 0 1
Operation Maintain present value Parallel load Shift right (unused - let's load 0s)
I2 0 3210
I1 0 3210
D Q Q2 (a)
D Q Q1
D Q Q0
Q3 Q2 Q1 Q0
(b)
Multifunction Registers
s1 0 0 1 1 s0 0 1 0 1 Operation Maintain present value Parallel load Shift right Shift left
I3 shr_in
I2
I1
I0 shl_in
3210
3210
3210
3210 shl_in shr_in s1 s0
I3
I2
I1
I0
D Q Q3
D Q Q2 (a)
D Q Q1
D Q Q0
Q3 Q2 Q1 Q0
(b)
Multifunction Registers with Separate Control Inputs

ld 0 0 0 0 1 1 1 1 shr 0 0 1 1 0 0 1 1 shl 0 1 0 1 0 1 0 1 Operation Maintain present value Shift left Shift right Shift right shr has priority over shl Parallel load Parallel load ld has priority shr_in Parallel load ld has priority Parallel load ld has priority ld shr shl combinational circuit
I3 shr_in s1 s0 I3
I2 I2
I1 I1
I0 I0 shl_in
Truth table for combinational circuit

Inputs shr ld 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 shl 0 1 0 1 0 1 0 1 Outputs s1 s0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 1 Note Operation Maintain value Shift left Shift right Shift right Parallel load Parallel load Parallel load Parallel load
shl_in Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
s1 = ld*shr*shl + ld*shr*shl + ld*shr*shl s0 = ld*shr*shl + ld
Register Operation Table

Register operations typically shown using compact version of table
X means same operation whether value is 0 or 1
One X expands to two rows Two Xs expand to four rows
Put highest priority control input on left to make reduced table simple
Inputs shr shl ld 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Outputs s1 s0 0 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 Note Operation Maintain value Shift left Shift right Shift right Parallel load Parallel load Parallel load Parallel load ld 0 0 0 1 shr 0 0 1 X shl 0 1 X X Operation Maintain value Shi t left f Shift right Parallel load
Register Design Process

Can design register with desired operations using simple four-step process
Register Design Example

Desired register operations
Load, shift left, synchronous clear, synchronous set
s2 0 0 0 0 1 1 1 1 s1 0 0 1 1 0 0 1 1 s0 0 1 0 1 0 1 0 1 Operation Maintain present value Parallel load Shift left Synchronous clear Synchronous set Maintain present value Maintain present value Maintain present value
Step 1: Determine mux size

5 operations: above, plus maintain present value (dont forget this one!) --> Use 8x1 mux
1 0
s2 s1 s0
In from Qn-1
7 6 5 4 3 2 1 0 D Q Qn
Step 2: Create mux operation table Step 3: Connect mux inputs Step 4: Map control lines
s2 = clr*set s1 = clr*set*ld*shl + clr s0 = clr*set*ld + clr
Inputs clr set ld 0 0 0

0 0 0 0 0 1
shl 0
1 X
Outputs s2 s1 s0 0 0 0
0 0 1 0 0 1
Operation Maintain present value

Shift left Parallel load
0 1
1 X
X X
X X
1 0
0 1
0 1
Set to all 1s Clear to all 0s
Register Design Example

I3 shl ld set clr combinational circuit s2 s1 s0 I3 I2 I2 I1 I1 I0 I0 shl_in
shl_in Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Step 4: Map control lines

s2 = clr*set s1 = clr*set*ld*shl + clr s0 = clr*set*ld + clr
clr 0
0 0
Inputs set ld 0 0
0 0 0 1
shl 0
1 X
Outputs s2 s1 s0 0 0 0
0 0 1 0 0 1
Operation Maintain present value

Shift left Parallel load
0 1
1 X
X X
X X
1 0
0 1
0 1
Set to all 1s Clear to all 0s
The End
Lecture-19
A.Amalin Prince
17-09-07
Counters
Counters
Synchronous Counters Ripple Counters Counter with unused states or Self Correcting Counters Counters based on Shift Registers
Ring Counter Johnson Counter
Ring Counter
Johnson Counter (Switch-tail Counter)
DC = (A+C)B
Ripple Counters
The Flip-Flop output transition serves as a source for triggering other Flip-Flops All Flip-Flops are not triggered by same clock
Binary Ripple Counter
BCD Ripple Counter
BCD Ripple Counter

Q8 Q4 Q2 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 Q1 0 1 0 1 0 1 0 1 0 1
Three decade decimal counter
The End
HDL FOR SEQUENTIAL CIRCUITS

LECTURE- 20
PREFER BEHAVIORAL MODELING TWO KINDS OF BEHAVIORAL STATEMENTS

initial Always
Syntax initial begin block of statements end always@(event control expn) begin block of statements end
Keywords for positive and negative edge trigering posedge and negedge
D Latch
module Latch(Q,D,EN); output Q; input D,EN; reg Q; always@(EN,D) if(EN) Q=D; endmodule
D -FLIP FLOP
module DFF(Q,D,CLK); output Q; input D,CLK; reg Q; always@(posedge CLK) Q=D; endmodule
D ff with asynchronous reset

module DFF(Q,D,CLK,RST); output Q; input D,CLK,RST; reg Q; always@(posedge CLK,negedge RST) if (~RST) Q=1b0; else Q=D; endmodule
T ff from DFF
module Tff(Q,T,CLK,RST); output Q; input T,CLK,RST; wire DT; assign DT = Q^T; DFF (Q,DT,CLK,RST); endmodule
Sequential statements
PARALLEL BLOCKS
Keyword fork and join All statement execute concurrently inside the initial statement initial fork x=1bo; //completes at time 0 #5 y = 1b1; // completes at time 5 #10 z = {x,y}; //completes at time 10 join
Counter counts 0 to N.
Shift registers
8 bit shift registers It shifts 1 bit right when r_l =1 other wise it shifts left Barrel shifter
Lecture-21
A.Amalin Prince
28-09-07
Counters
Counters
Synchronous Counters Ripple Counters Counter with unused states or Self Correcting Counters Counters based on Shift Registers
Ring Counter Johnson Counter
COUNTER TYPES
Asynchronous Counter (a.k.a. Ripple or Serial Counter): each FF is triggered one at a time with output of one FF serving as clock input of next FF in the chain. Synchronous Counter (a.k.a. Parallel Counter): all the FFs in the counter are clocked at the same time. Up Counter: counter counts from zero to a maximum count. Down Counter: counter counts from a maximum count down to zero. BCD Counter: counter counts from 0000 to 1001 before it recycles. Pre-settable Counter: counter that can be preset to any starting count either synchronously or asynchronously Ring Counter: shift register in which the output of the last FF is connected back to the input of the first FF. Johnson Counter: shift register in which the inverted output of the last FF is connected to the input of the first FF.
Synchronous Counters
N-bit up-counter: N-bit register that can increment (add 1) to its own value on each clock cycle
0000, 0001, 0010, 0011, ...., 1110, 1111, 0000 Note how count rolls over from 1111 to 0000
Terminal (last) count, tc, equals1 during value just before rollover
cnt ld 4-bit register
1 0
cnt
4-bit up-counter tc C 4
0 0 1
0101 0100 0011 0010 0001 0000 0001 0000 1111 1110 ...
4-bit up-counter
Internal design
Register, incrementer, and N-input AND gate to detect terminal count
tc
4 4 C
4 +1 4
Incrementer
Counter design used incrementer Incrementer design
Could use carry-ripple adder with B input set to 00...001
But when adding 00...001 to another number, the leading 0s obviously dont need to be considered -- so just two bits being added per column
Use half-adders (adds two bits) rather than full-adders (adds three bits)
a3 a2 a b HA co s s2 (a) a1 a b HA co s s1 a0 1 a3 a2 a1 a0 +1 co s3s2 s1 s0 (b)
011 0011 unused + 1 0 0 10 0
carries:
a b HA co s co s3
a b HA co s s0
Incrementer
Can build faster incrementer using combinational logic design process
Capture truth table Derive equation for each output
c0 = a3a2a1a0 ... s0 = a0
Inputs a3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 a2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 c0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Outputs s3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 s2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 s1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 s0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Results in small and fast circuit Note: works for small N -- larger N leads to exponential growth, like for N-bit adder
Counter Example: Mode in Above-Mirror Display

Recall above-mirror display already discussed
Assumed component that incremented xy input each time button pressed: 00, 01, 10, 11, 00, 01, 10, 11, 00, ... Can use 2-bit up-counter
Assumes mode=1 for just one clock cycle during each button press
Remember Button press synchronizer
mode
cnt tc
2-bit up counter c1c0
clk
x y
Counter Example: 1 Hz Pulse Generator Using 256 Hz

Oscillator
Suppose have 256 Hz oscillator, but want 1 Hz pulse
1 Hz is 1 pulse per second -- useful for keeping time Design using 8-bit upcounter, use tc output as pulse
Counts from 0 to 255 (256 counts), so pulses tc every 256 cycles
1
cnt
osc (256 Hz)
8-bit up-counter tc C 8 p (unused) (1 Hz)
Down-Counter
4-bit down-counter
1111, 1110, 1101, 1100, , 0011, 0010, 0001, 0000, 1111, Terminal count is 0000
Use NOR gate to detect
cnt ld 4-bit register 4-bit down-counter
Need decrementer (-1) design like designed incrementer

tc
4 4 C
4 1 4
Up/Down-Counter
Can count either up or down
Includes both incrementer and decrementer Use dir input to select, using 2x1: dir=0 means up Likewise, dir selects appropriate terminal count value
dir 4-bit up/down counter
4-bit 2 x 1 0 4
clr cnt
clr ld
4-bit register
4 4
4 1 4
4 +1 4
1 2x 1 0 tc
Counter Example: Light Sequencer

Illuminate 8 lights from right to left, one at a time, one per second Use 3-bit up-counter to counter from 0 to 7 Use 3x8 decoder to illuminate appropriate light Note: Used 3-bit counter with 3x8 decoder
NOT an 8-bit counter why not?
1 clk (1 Hz) cnt 3-bit up-counter tc unused 3x 8 dcd c2 c1 c0
0 0 1 0 0 1
i2 i1 i0
d7 d6 d5 d4 d3 d2 d1 d0
lights
Counter with Parallel Load

Up-counter that can be loaded with external value
Designed using 2x1 mux ld input selects incremented value or external value Load the internal register when loading external value or when counting
L ld 1 4 4-bit 2x 1 0 4
cnt
ld 4-bit register
4 4 tc C
4 +1

Useful to create pulses at specific multiples of clock
Not just at N-bit counters natural wrap-around of 2N
ld 1 cnt
1000
4
Example: Pulse every 9 clock cycles

Use 4-bit down-counter with parallel load Set parallel load input to 8 (1000) Use terminal count to reload
When count reaches 0, next cycle loads 8.
4-bit down-counter
tc 4 C
clk
Why load 8 and not 9? Because 0 is included in count sequence:

8, 7, 6, 5, 4, 3, 2, 1, 0
9 counts
4-bit binary counter with parallel load

Clear CLK Load Count Function
0 1 1 1
X 1 0 0
X X 1 0
Clear to 0 Load inputs Count to next state No change
BCD Counter using a Counter with Parallel Load
Counter Example:
New Years Eve Countdown Display
Above example previously used microprocessor to counter from 59 down to 0 in binary Can use 8-bit (or 7- or 6-bit) down-counter instead, initially loaded with 59
59 8 L ld reset c0 c1 c2 c3 c4 c5 c6 c7 i0 i1 i2 i3 i4 i5 d0 d1 d2 d3 0 1 2 3 Happy New Year
cnt countdown clk (1 Hz)
8-bit down- tc counter
d58 d59 d60 d61 d62 6x64 dcd d63
58 59
fireworks
Counter Example:
1 Hz Pulse Generator from 60 Hz Clock
U.S. electricity standard uses 60 Hz signal
Device may convert that to 1 Hz signal to count seconds
1 osc (60 Hz) clr cnt 6-bit up counter tc p C
Use 6-bit up-counter

Can count from 0 to 63 Create simple logic to detect 59 (for 60 counts)
Use to clear the counter back to 0 (or to load 0)
(1 Hz)
59 in binary 111011
Timer
A type of counter used to measure time
If we know the counters clock frequency and the count, we know the time thats been counted
Example: Compute cars speed using two sensors

First sensor (a) clears and starts timer Second sensor (b) stops timer Assuming clock of 1kHz, timer output represents time to travel between sensors. Knowing the distance, we can compute speed
IC ASYNCHRONOUS COUNTERS
Logic Diagram for 7493
___ CPo ___ CP1 MR1 MR2 Qo (LSB) Q1 Q2
*All J, K inputs internally connected HIGH
___ CP1 ___ CPo
J Q CP K QN R
J Q CP K QN R
J Q CP K QN R
J Q CP K QN R
Q3 (MSB)
7493
MR1 MR2
Q3
Q2
Q1
Qo
7493 AS A MOD-16 COUNTER

Logic Diagram for 7493
*All J, K inputs internally connected HIGH J Q CP K QN R J Q CP K QN R J Q CP K QN R J Q CP K QN R
Q3 (MSB)
7493
MR2 Q3 Q2 Q1 Qo
___ CP1 ___ CPo 10 kHz
MR1
F= 10 kHz/16 = 625 Hz
TEST
Build a MOD 10 counter with a 7493
*All J, K inputs internally connected HIGH J Q CP K QN R J Q CP K QN R J Q CP K QN R J Q CP K QN R
Q3 (MSB)
7493
MR2 Q3 Q2 Q1 Qo
___ CP1 ___ CPo
10 kHz
MR1
F= 10 kHz/10 = 1KHz
BCD COUNTER
Binary counter that counts from 0000 to 1001 before it recycles (MOD-10). Widespread applications where pulses or events are to be counted and the results displayed on a decimal numerical read-out. Also used for dividing a pulse frequency exactly by 10.
Hundreds
BCD counter D C B A D
Tens
BCD counter C B A D
Units
BCD counter C B A
Input
Decoder/display 0-9
Decoder/display 0-9
Decoder/display 0-9
Cascading BCD counters to count and display from 000 to 999.

MOD-60 COUNTER
MOD 6 MOD 10
7493
MR2 Q3 Q2 Qo not used
___ CP1 ___ CPo

Q1 MR1
7493
MR2 Q3 Q2 Qo
___ CP1 ___ CPo

Q1
fin
fout = fin/60
fin/10
Two 7493s can be combined to produce a MOD-60 Counter
DIGITAL CLOCK
Counters with unused states (Self Correcting Counter)

Design a counter: 000-001-010-100-101-110-000
What happens if we fall in unused states? In this case, 111 results in 000. 011 results in 100. The Counter is self-correcting.
Counters with unused states
Present State A B C 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0
Next State A B C 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 0
Flip-Flop Inputs JA KA JB KB JC KC 0 X 0 X 1 X 0 X 1 X X 1 1 X X 1 0 X X 0 0 X 1 X X 0 1 X X 1 X 1 X 1 0 X
JA=KA=B JB=C, KB=1 JC=B KC=1

The End
Lecture-22
A.Amalin Prince
01-10-07
Objective :Analysis of Clocked Sequential Circuits, FSM (Finite State Machine) and Controller Design
Synchronous Sequential (Clocked) Networks
General model of a sequential network
Structure an Operation of Clocked Synchronous Sequential Networks
Structure of a clocked synchronous sequential network
Models
The Synchronous or Clocked sequential circuits are represented by two models
Mealy circuit: The output depends on both the present state of the flipflop(s) and on the input(s). Moore Circuit: The output depends only on the present state of the flip-flop(s)
Mealy Machine (Model)
Moore Machine (Model)
a) Its output is a a) Its output is a function of function of present state as present state well as present only input b) Input changes b) Input changes does not affect may affect the the output output c) It requires more c) It requires less number of states number of states for implementing for implementing same function. same function.
Mealy Machine
Mealy model of a clocked synchronous sequential network
Q + = f ( X , Q)
Z = g ( X , Q)
Moore Machine
Moore model of a clocked synchronous sequential network
Q + = f ( X , Q)
Z = g (Q )
Analysis of Clocked Synchronous Sequential Networks

Two main reason for beginning the study of clocked sequential networks with analysis
Useful when sequential networks are to be designed The steps involved in the synthesis of clocked synchronous sequential network are basically the reverse of those involved in the analysis procedure
The analysis procedure
Example: Mealy Machine
E x ita tio n e x p re s s io n s D 1 = x Q 2 + Q 1Q 2 D 2 = x Q 1 + Q 2Q 2
Output expressions z= xQ1 + xQ1 Q 2

Transition Equations
By substituting the excitation expressions for a flip-flop into its characteristic equation, an algebraic description of the next state of the flip-flop is obtained. These expressions are referred to as transition equations
Q = D1 = xQ2 + Q1Q2 Q = D2 = xQ1 + Q1Q2

+ 2
+ 1

Transition Table
The transition table is the tabular representation of the transition and output equations.
Present State (Q1Q2) 00 01 10 11
Next state (Q1+ Q2+) Input (x) 0 10 11 10 00 1 01 11 00 00
Output (z) Input (x) 0 0 0 1 1 1 1 0 0 0

Excitation Tables
Present State (Q1Q2) 00 01 10 11 Excitation (D1 D2) Input (x) 0 10 11 10 00 1 01 11 00 00 Output (z) Input (x) 0 0 0 1 1 1 1 0 0 0

State Tables
Present State (Q1Q2) 00 00A 01 01B 10 10C 11 11D Next state (Q1+ Q2+) Input (x) 0 C 10 D 11 C 10 A 00 1 B 01 D 11 A 00 A 00 Output (z) Input (x) 0 0 0 1 1 1 1 0 0 0 A B C D Present State (Q1Q2)
Next state, Output
(Q1+ Q2+)
Input (x)
0 C,0 D,0 C,1 A,1
1 B,1 D,0 A,0 A,0

State Diagrams
Present State (Q1Q2) A B C D
Next state, Output
(Q1+ Q2+)
Input (x)
0 C,0 D,0 C,1 A,1
1 B,1 D,0 A,0 A,0
Example: Moore Machine
Logic diagram for Example
E x ita tio n e x p re s s io n s J1 = y , K1 = y + xQ 2
J 2 = x Q 1 + x y Q1 , K 2 = x y + y Q 1
Output expressions
z1 = Q1 Q 2 z 2 = Q1 + Q 2

Transition Equations
By substituting the excitation expressions for a flip-flop into its characteristic equation, an algebraic description of the next state of the flip-flop is obtained. These expressions are referred to as transition equations
Q1+ = J1 Q1 + K1Q1 = yQ1 + x yQ1 + yQ1Q2

+ Q2 = J 2 Q2 + K 2Q2
= xQ1 Q 2 + xyQ1 Q 2 + x yQ2 + xQ1Q2 + yQ1Q2


Transition Table
The transition table is the tabular representation of the transition and output equations.
Present State (Q1Q2)
Next state (Q1+ Q2+) Inputs (xy) 00 01 10 11 11 11 00 00
Output (z)
00 01 10 11
00 10 01 01 11 00 10 01 00 11 00 10
01 00 11 01

Excitation Tables Present
State (Q1Q2) 00 00 01 10 11
Exitation (J1K1, J2K2) Inputs (xy) 01 10 11 11,10 11,10 11,01 11,01
Output (z)
00,00 11,00 01,11 00,00 11,00 00,11 00,00 11,11 01,01 00,00 11,11 00,01
01 00 11 01

State Tables
Present State (Q1Q2) 00 A 00 01 B 01 10 C 10 11 D 11 Next state (Q1+ Q2+) Inputs (xy) 00 01 10 00 10 01 A C B 01 11 00 B D A 10 01 00 C B A D A C 11 00 10 11 11 D 11 D 00 A A 00 01 00 11 01 Output (z)

State Diagrams
Present State (Q1Q2) 00 A B C D A B C D Next state (Q1+ Q2+) Inputs (xy) 01 C D B A 10 B A A C 11 D D A A 01 00 11 01 Output (z)

Network Terminal Behavior
Input seq. x State seq.

0 A 0
0 C 1
1 C 0
1 A 1
0 B 0
1 D 0
1 A 1
1 B 0
0 D 1
1 A 1 B
Output seq.
The End
Lecture-23
A.Amalin Prince
03-10-07
Objective :FSM (Finite State Machine) and Controller Design
Controller Design
Five step controller design process
Finite-State Machines (FSMs)

Want sequential circuit with particular behavior over time Example: Laser timer
Push button: x=1 for 3 clock cycles How? Lets try three flip-flops
b=1 gets stored in first D flip-flop Then 2nd flip-flop on next cycle, then 3rd flip-flop on next OR the three flip-flop outputs, so x should be 1 for three cycles
b Controller x clk patient laser
b clk
Need a Better Way to Design Sequential Circuits

Trial and error is not a good design method
Will we be able to guess a circuit that works for other desired behavior?
How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10 cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input? Laser timer: What if press button again while x=1? x then stays one another 3 cycles. Is that what we want?
And, a circuit built by guessing may have undesired behavior
Combinational circuit design process had two important things

1. A formal way to describe desired circuit behavior
Boolean equation, or truth table
2. A well-defined process to convert that behavior to a circuit
We need those things for sequence circuit design

Describing Behavior of Sequential Circuit: FSM

Finite-State Machine (FSM)
A way to describe desired behavior of sequential circuit
Akin to Boolean equations for combinational behavior
Outputs: x x=0 Off clk^
Off On Off On Off On Off On
clk^
x=1 On
List states, and transitions among states

Example: Make x change toggle (0 to 1, or 1 to 0) every clock cycle Two states: Off (x=0), and On (x=1) Transition from Off to On, or On to Off, on rising clock edge Arrow with no starting state points to initial state (when circuit first starts)
clk state Outputs: x
cycle 1
cycle 2
cycle 3
cycle 4
Off
On
Off
On
FSM Example: 0,1,1,1,repeat

Want 0, 1, 1, 1, 0, 1, 1, 1, ...
Each value for one clock cycle
Outputs: x x=0 Off clk^ x=1 On1 clk^ clk^ x=1 On2 clk^ x=1 On3
Can describe as FSM

Four states Transition on rising clock edge to next state
clk State Off On1On2On3 Off On1On2 On3 Off Outputs: x
Extend FSM to Three-Cycles High Laser Timer

Four states Wait in Off state while b is 0 (b) When b is 1 (and rising clock edge), transition to On1
Sets x=1 On next two clock edges, transition to On2, then On3, which also set x=1
clk Inputs: b State Off Off Off Off Off On1 On2 On3 Off Outputs: x
Inputs: b; Outputs: x x=0 Off b*clk^ x=1 clk^ On1 b*clk^ clk^
x=1 On2
clk^
x=1 On3
So x=1 for three cycles after button pressed

FSM Simplification: Rising Clock Edges Implicit

Showing rising clock on every transition: cluttered
Make implicit -- assume every edge has rising clock, even if not shown What if we wanted a transition without a rising edge
We dont consider such asynchronous FSMs -- less common, and advanced topic Only consider synchronous FSMs -- rising edge on every transition
Note: Transition with no associated condition thus transistions to next state on next clock cycle
Inputs: b; Outputs: x
x=0 Off b*clk ^ x=1 clk^ On1 b *clk^ clk^
x=1 On2
clk^
x=1 On3
Inputs: b; Outputs: x x=0 Off b x=1 On1 x=1 On2 x=1 On3 b
FSM Definition
FSM consists of
Set of states
Ex: {Off, On1, On2, On3}
Set of inputs, set of outputs

Ex: Inputs: {x}, Outputs: {b}
Initial state
Ex: Off
Set of transitions
Describes next states Ex: Has 5 transitions
We often draw FSM graphically, known as state diagram

Can also use table (state table), or textual languages
Set of actions
Sets outputs while in states Ex: x=0, x=1, x=1, and x=1
FSM Example: Secure Car Key

Many new car keys include tiny computer chip
When car starts, cars computer (under engine hood) requests identifier from key Key transmits identifier
If not, computer shuts off car
Wait r=0 a K1 r=1 a K2 r=1 K3 r=0 K4 r=1
Inputs: a; Outputs: r
FSM
Wait until computer requests ID (a=1) Transmit ID (in this case, 1101)
FSM Example: Secure Car Key (cont.)

Nice feature of FSM
Can evaluate output behavior for different input sequence Timing diagrams show states and output values for different input waveforms
Wait r=0 a K1 r=1 a K2 r=1 K3 r=0 K4 r=1 Inputs: a; Outputs: r
Q: Determine states and r value for given input waveform:

clk Inputs a State Outputs r Wait Wait K1 K2 K3 K4 Wait Wait clk Inputs a State Output r Wait Wait K1 K2 K3 K4 Wait K1
FSM Example: Code Detector

Unlock door (u=1) only when buttons pressed in sequence:
start, then red, blue, green, red
Start Red Green Blue s u r g b a Code detector Door lock
Input from each button: s, r, g, b

Also, output a indicates that some colored button pressed
FSM
Wait for start (s=1) in Wait Once started (Start)
If see red, go to Red1 Then, if see blue, go to Blue Then, if see green, go to Green Then, if see red, go to Red2
In that state, open the door (u=1) Wait u=0 s Start u=0 ar Red1 u=0 ab a Blue u=0 ag a s a ar ab ag
Inputs: s,r,g,b,a; Outputs: u ar
Green u=0
ar a
R ed2 u=1
Wrong button at any step, return to Wait, without opening door

Q: Can you trick this FSM to open the door, without knowing the code? A: Yes, hold all buttons simultaneously
Improve FSM for Code Detector

Inputs: s,r,g,b,a; Outputs: u s ar ab ag ar
Wait u=0 s Start u=0 ar Red1 u=0 ab a
a Blue u=0 ag a Green u=0 ar a Red2 u=1

Note: small problem still remains; well discuss later
New transition conditions detect if wrong button pressed, returns to Wait FSM provides formal, concrete means to accurately define desired behavior
Standard Controller Architecture

How implement FSM as sequential circuit?
Use standard architecture
State register -- to store the present state Combinational logic -- to compute outputs, and next state For laser timer FSM
2-bit state register, can represent four states Input b, output x
s p u o t
FSM inputs
b Combinational n1 logic n0 s1 s0 clk State register
Known as controller
FSM inputs I
O Combinational logic
S
m
m
clk
m-bit state register N
General version
FSM outputs
FSM outputs
M S F
Standard Controller Architecture

FSM inputs
Flip-flop types for state resister
O Combinational logic
S
SR flip-flop: like SR latch, but edge triggered JK flip-flop: like SR (S J, R K)

But when JK=11, toggles 1 0, 0 1
clk
m
m
m-bit state register N
T flip-flop: JK with inputs tied together

Toggles on every rising clock edge
General version
Previously utilized to minimize logic outside flip-flop

Today, minimizing logic to such extent is not as important D flip-flops are thus by far the most common While designing, depends on the type of FF make changes in the State Table and Flip-Flop Input Equations
Flip-Flops
FSM outputs
The End
Lecture-24
A.Amalin Prince
05-10-07
State Reduction (State Minimization)

Goal: Reduce number of states in FSM without changing behavior
Fewer states potentially reduces size of state register
Consider the two FSMs below with x=1, then 1, then 0, 0

Inputs: x; Outputs: y x x S0 y=0 S1 y=1
S0 S1
x x S2 y=0
S1
x x S3 y=1
S2
x x S0 y=0 S1 y=1
S1
state x y
S2
state x y
x
S0
S1
S0
S0
For the same sequence of inputs, the output of the two FSMs is the same
if x = 1,1,0,0 then y = 0,1,1,0,0
State Reduction: Equivalent States

Two states are equivalent if: 1. They assign the same values to outputs
e.g. S0 and S2 both assign y to 0, S1 and S3 both assign y to 1
Inputs: x; Outputs: y x x S0 y=0 S1 y=1 x x S2 y=0 x x S3 y=1 x x
States S0 and S2 equivalent States S1 and S3 equivalent
2. AND, for all possible sequences of inputs, the FSM outputs will be the same starting from either state
e.g. say x=1,1,0,0,
starting from S1, y=1,1,0,0, starting from S3, y=1,1,0,0,
S0, S2 y=0
x x S1, S3 y=1
State Reduction: Example with no Equivalencies

Another example State S0 is not equivalent with any other state since its output (y=0) differs from other states output Consider state S1 and S3
Outputs are initially the same (y=1) From S1, when x=0, go to S2 where y=1
Inputs: x; Outputs: y x x x S0 y=0 S1 y=1 x x x S2 y=1 x x x S2 y=1 x x S3 y=1 x x S3 y=1 x x S2 y=1 x x S3 y=1 x
Start from S1, x=0

x S0 x x S1
From S3, when x=0, go to S0 where y=0 y=0 y=1 Outputs differ, so S1 and S3 are not Start from S3, x=0 equivalent.
x S0
x x S1 y=1
y=0
State Reduction with Implication Tables

State reduction through visual inspection (what we did in the last few slides) isnt reliable and cannot be automated a more methodical approach is needed: implication tables Example:
S0 S1 S2 S3 S0 S1 S2 S3 Diagonal Redundant
To compare every pair of states, construct a table of state pairs (above right) Remove redundant state pairs, and state pairs along the diagonal since a state is equivalent to itself (right)
S1 S2 S3 S0 S1 S2

Mark (with an X) state pairs with different outputs as non-equivalent:
(S1,S0): At S1, y=1 and at S0, y=0. So S1 and S0 are non-equivalent. (S2, S0): At S2, y=0 and at S0, y=0. So we dont mark S2 and S0 now. (S2, S1): Non-equivalent (S3, S0): Non-equivalent (S3, S1): Dont mark (S3, S2): Non-equivalent
S1 S2 S3 S0 S1 S2
We can see that S2 & S0 might be equivalent and S3 & S1 might be equivalent, but only if their next states are equivalent (remember the example from two slides ago)

We need to check each unmarked state pairs next states We can start by listing what each unmarked state pairs next states are for every combination of inputs
(S2, S0)
From S2, when x=1 go to S3 From S0, when x=1 go to S1 So we add (S3, S1) as a next state pair From S2, when x=0 go to S2 From S0, when x=0 go to S0 So we add (S2, S0) as a next state pair
S1 S2 S3 S0
(S3, S1) (S2, S0) (S3, S1) (S0, S2)
(S3, S1)
By a similar process, we add the next state pairs (S3, S1) and (S0, S2)
S1
S2

Next we check every unmarked state pairs next state pairs We mark the state pair if one of its next state pairs is marked
(S2, S0)
Next state pair (S3, S1) is not marked Next state pair (S2, S0) is not marked So we do nothing and move on
S1 S2 S3 S0
(S3, S1) (S2, S0) (S3, S1) (S0, S2)
(S3, S1)
Next state pair (S3, S1) is not marked Next state pair (S0, S2) is not marked So we do nothing and move on
S1
S2

We just made a pass through the implication table
Make additional passes until no change occurs
Then merge the unmarked state pairs they are equivalent

x x
S0,S2 S1,S3
S1 S2
(S3, S1) (S2, S0) (S3, S1) (S0, S2)
S3 S0
S1
S2
y=0
y=1
State Reduction Example

Given FSM on the right
Step 1: Mark state pairs having different outputs as nonequivalent
S1 S2 S3 S0 S1 S2

Step 1: Mark state pairs having different outputs as nonequivalent Step 2: For each unmarked state pair, write the next state pairs for the same input values
S1 S2 S3 S0
(S2, S2) (S3, S1)
x=0 x=1
(S0, S2) (S0, S2) (S3, S1) (S3, S3)
S1
S2

Step 1: Mark state pairs having different outputs as nonequivalent Step 2: For each unmarked state pair, write the next state pairs for the same input values Step 3: For each unmarked state pair, mark state pairs having nonequivalent next state pairs as nonequivalent.
Repeat this step until no change occurs, or until all states are marked.
S1 S2 S3 S0
(S2, S2) (S3, S1) (S0, S2) (S0, S2) (S3, S1) (S3, S3)
S1
S2
Step 4: Merge remaining state pairs

All state pairs are marked there are no equivalent state pairs to merge
A Larger State Reduction Example

Inputs: x; Outputs: y x S3 x y=0 x x S2 y=1 S0 y=0 x x S1 y=1 S4 (S4,S2) (S0,S1) S0 S1 S2 x S4 y=0 x S3 (S3,S2) (S0,S1) (S4,S3) (S0,S0) S3 x S2 (S3,S4) (S2,S1) S1

A Larger State Reduction Example

Inputs: x; Outputs: y x S3 x y=0 x x S2 y=1 S0 y=0 x x S1 y=1 S4 (S4,S2) (S0,S1) S0 S1 S2 x S4 y=0 x S3 (S3,S2) (S0,S1) (S4,S3) (S0,S0) S3 x S2 (S3,S4) (S2,S1) S1
Inputs: x; Outputs: y x x S0 y=0 S3,S4 y=0 x x x S1,S2 y=1 x

Need for Automation

Automation needed
Table for large FSM too big for humans to work with
n inputs: each state pair can have next state pairs. 4 inputs 24=16 next state pairs 2n
x SE z=0 x Inputs: x; Outputs: z x x x SA z=1 x SC z=0 x x x SD z=1 x x SF z=1 x SB z=0 x SH x z=0 x SJ x x SK z=1 x z=0 SL z=0 x x x SI z=1 x' x x SM z=1 x SN z=1 x x x SO z=0 x
x SG z=0
100 states would have table with 100*100=100,000 state pairs cells State reduction typically automated
Often using heuristics to reduce compute time
State Assignment (State Encoding)

State S0 S1 S2 S3 S4 Assignment-1 Binary 000 001 010 011 100 Assignment-2 Gray code 000 001 011 010 110 Assignment-3 One-hot 00001 00010 00100 01000 10000
The End
Lecture-25
A.Amalin Prince
08-10-07
Controller Design
Five step controller design process
Controller Design: Laser Timer Example

Step 1: Capture the FSM
Already done
Inputs: b; Outputs: x x=0 00 b Off b x=1 01 On1 x=1 10 On2 x=1 11 On3
Step 2: Create architecture

2-bit state register (for 4 states) Input b, output x Next state signals n1, n0
s p u o t
FSM inputs
Step 3: Encode the states

Any encoding with each state unique will work
FSM outputs
M S F
Controller Design: Laser Timer Example (cont)

Step 4: Create state table
Inputs: b; Outputs: x x=0 00 b O ff b x=1 01 On1 x=1 10 On2 x=1 11 On3
FSM outputs
FSM inputs

Step 5: Implement combinational logic
FSM outputs FSM inputs
x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0

= 1)
n1 = s1s0b + s1s0b + s1s0b + s1s0b n1 = s1s0 + s1s0 n0 = s1s0b + s1s0b + s1s0b n0 = s1s0b + s1s0

s p u o t M S F
FSM inputs
Step 5: Implement combinational logic (cont)
b
b
n S i p F M u t s
Combinational Logic x
FSM outputs
x Combinational n1 logic n0 s1 s0
n1
clk
State register
n0
s1 clk
s0
State register
x = s1 + s0 n1 = s1s0 + s1s0 n0 = s1s0b + s1s0

Understanding the Controllers Behavior

x=0
00 Off
x=0 b x=1
10 On2 00 Off
x=0 b x=1
10 On2 00 Off
b x=1
10 On2
x=1
01 On1
x=1
11 On3
x=1
01 On1
x=1
11 On3
x=1
01 On1
x=1
11 On3
b 0
0 0 0 0 0
x 0 n1 0
b 1
0 0 0 0 1
x 0 n1 0
b 1
0 1 1 0 0
x 1 n1 1 n0 0
n0 0 0 clk s1 0 0 s0 0 0 state=00 clk s1 0 0 s0 0 1 state=00 0
n0 1 0 clk s1 0 1 s0 1 0 state=01
clk Inputs: b Outputs: x
Controller Design: Laser Timer Example

Implement the same design using
JK FF. T FF
State Encoding
Encoding: Assigning a unique bit representation to each state Different encodings may optimize size, or tradeoff size and performance Consider 3-Cycle Laser Timer
Binary encoding: 15 gate inputs Try alternative encoding
x = s1 + s0 n1 = s0 n0 = s1b + s1s0 Only 8 gate inputs 1 1 0 0
Inputs: b; Outputs: x x=0 00 b x=1 01 On1 x=1 11 10 On2 x=1 10 11 On3 Off b
1 1 0 0
One-Hot Encoding Example:

Three-Cycles-High Laser Timer
Four states Use four-bit one-hot encoding
State table leads to equations:
x = s3 + s2 + s1 n3 = s2 n2 = s1 n1 = s0*b n0 = s0*b + s3
b x=1 0010 On1 x=1 0100 On2 x=1 1000 On3 Inputs: b; Outputs: x x=0 0001 Off b
Smaller
3+0+0+2+(2+2) = 9 gate inputs Earlier binary encoding : 15 gate inputs
Faster
Critical path: n0 = s0*b + s3 Previously: n0 = s1s0b + s1s0 2-input AND slightly faster than 3-input AND
State Encoding: One-Hot Encoding

One-hot encoding
One bit per state a bit being 1 corresponds to a particular state Alternative to minimum bit-width encoding in previous example For A, B, C, D: A: 0001, B: 0010, C: 0100, D: 1000
Inputs: none; Outputs: x x=0 A 00 0001 x=1 D 11 1000
B 01 0010 x=1
C 10 0100 x=1
Example: FSM that outputs 0, 1, 1, 1

Equations if one-hot encoding:
n3 = s2; n2 = s1; n1 = s0; x = s3 + s2 + s1
Fewer gates and only one level of logic less delay than two levels, so faster clock frequency
8 binary 6 4 one-hot 2
clk n1
s3 s1 s0 n0 clk State register
s2
s1
s0
State register n0 n1
1 2 3 4 delay (gate-delays)
n2
n3
Output Encoding
Output encoding: Encoding method where the state encoding is same as the output values
Possible if enough outputs, all states with unique output values
Use the output values as the state encoding
Inputs: none; Outputs: x,y xy=00 A 00
xy=01 D 11
B 01 xy=11
C 10 xy=10
Output Encoding Example: Sequence Generator

Inputs: none; Outputs: w, x, y, z wxyz=0001 wxyz=1000 A D
w x y z
B wxyz=0011
C wxyz=1100
s3 s2 s1 s0
Generate sequence 0001, 0011, 1110, 1000, repeat

FSM shown
clk
State register
n2 n1 n0
Use output values as state encoding Create state table Derive equations for next state
n3 = s1 + s2; n2 = s1; n1 = s1s0; n0 = s1s0 + s3s2
n3
Controller Example:
Button Press Synchronizer
clk Inputs: bi cycle1 cycle2 cycle3 cycle4
bi
Button press synchronizer controller
bo
Outputs: bo
Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button actually pressed
We assumed such an ideal button press signal in earlier example, like the button in the laser timer controller
Controller Example:
Button Press Synchronizer (cont)
FSM inputs: bi; FSM outputs: bo bi A bo=0 bi B bo=1 bi bi bi C bi bo=0
clk bi Combinational logic s1 s0 bo n1 n0 n1 = s1s0bi + s1s0bi n0 = s1s0bi bo = s1s0bi + s1s0bi = s1s0 Combinational logic bo
M S F s p u o t
FSM outputs
FSM inputs
State register
Step 1: FSM
Combinational logic Inputs Outputs s1 s0 bi n1 n0 bo 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0 0
bi
n1
FSM inputs: bi; FSM outputs: bo bi 00 bo=0 bi 01 bo=1 bi bi bi 10 bi bo=0
A B C unused
n0
s1 clk
s0 State register
Step 3: Encode states
Step 4: State table

Step 5: Create combinational circuit
Controller Example: Sequence Generator

Want generate sequence 0001, 0011, 1100, 1000, (repeat)
Each value for one clock cycle Common, e.g., to create pattern in 4 lights, or control magnets of a stepper motor
Inputs: none; Outputs: w,x,y,z wxyz=0001 A wxyz=1000 D
Combinational logic s1 s0
B wxyz=0011
w x y z n1 n0
Inputs: none; Outputs: w,x,y,z

wxyz=0001 A wxyz=1000 D
00 01
11 10
B wxyz=0011
C wxyz=1100
clk
State register
C wxyz=1100
Step 1: Create FSM

w = s1 x = s1s0 y = s1s0 z = s1 n1 = s1 xor s0 n0 = s0 s1
Step 3: Encode states

w x y z
s p u o t M S F
Step 4: Create state table

clk
s0 State register
n0
n1
Step 5: Create combinational circuit
Controller Example: Secure Car Key

Inputs: a; Outputs: r Wait r=0 a K1 r=1 a K2 r=1 K3 r=0 K4 r=1
s t u p o
(from earlier example)
Step 1
a
S F M
r
Combinational logic
S F M
Step 2
s t u p i n
n2 n1
n0
s2 s1 s0
clk
State register
Inputs:a;Outputs:r
000
r=0
Step 3
001
r=1
010
r=1
011
r=0
100
r=1
Well omit Step 5

Step 4
Example: Seq. Circuit to FSM (Reverse Engineering)

What does this circuit do?
x
s t u p n S F i M S o F M u t p s
y z
y=s1 z = s1s0 n1=(s1 xor s0)x n0=(s1*s0)x
states
D C
Outputs:y, z A B yz=10 C yz=01
n1 n0 s1 clk s0
State register
x
yz=10 D yz=00
states with outputs
Inputs: x; Outputs:y, z x A yz=10 x B x C x yz=01 yz=10
Work backwards
Pick any state names you want
D yz=00
states with outputs and transitions
Common Pitfalls Regarding Transition Properties

a
Only one condition should be true

For all transitions leaving a state Else, which one?
b ab=11 next state?
a ab
ab a ab ab what if ab=00?
One condition must be true

For all transitions leaving a state Else, where go?
Verifying Correct Transition Properties

Can verify using Boolean algebra Answer:
a * ab = (a * a) * b =0*b =0 OK!
Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0 proves pair can never simultaneously be true One condition true: OR of all conditions of transitions leaving a state) should equal 1 proves at least one a + ab = a*(1+b) + ab condition must be true = a + ab + ab = a + (a+a)b Example
a ab
=a+b Fails! Might not be 1 (i.e., a=0, b=0)
Q: For shown transitions, prove whether: * Only one condition true (AND of each pair is always 0) * One condition true (OR of all transitions is always 1)
Evidence that Pitfall is Common

Recall code detector FSM
Wait We fixed a problem with the u=0 s transition conditions Do the transitions obey the two Start required transition properties? u=0ar s
a ab a Blue u=0 ag a Green u=0 ar a Red2 u=1
Consider transitions of state Start, and the only one true property
Red1 u=0
ar * a a * a(r+b+g) = (a*a)r = 0*r =0 =0
Fails! Means that two of Starts (likewise for ab, ag, ar) transitions could be true Note: As evidence the pitfall is common,
ar * a(r+b+g) Intuitively: press red and blue = (a*a)*(r+b+g) = 0*(r+b+g) buttons at same time: conditions = (a*a)*r*(r+b+g) = a*r*(r+b+g) ar, and a(r+b+g) will both be true. Which one should be = arr+arb+arg taken? = 0 + arb+arg Q: How to solve? = arb + arg = ar(b+g) A: ar should be arbg
we admit the mistake was not intentional. A reviewer of the book caught it.
Simplifying Notations
FSMs
Assume unassigned output implicitly assigned 0
a=0 b=1 c=0 a=0 b=0 c=1
clk a
Sequential circuits
Assume unconnected clock inputs connected to same external clock
b=1 c=1
Non-Ideal Flip-Flop Behavior

Cant change flip-flop input too close to clock edge
Setup time: time that D must be stable before edge
Else, stable value not present at internal latch
clk D
Hold time: time that D must be held stable after edge

Else, new value doesnt have time to loop around and stabilize in internal latch
Setup time violation
D latch D S Q C u Q u R R Q Q
setup time clk D
C D S 2 3 4 7 5 6 1
hold time
Leads to oscillation!
Metastability
Violating setup/hold time can lead to bad situation known as metastable state
Metastable state: Any flip-flop state other than stable 1 or 0
Eventually settles to one or other, but we dont know which
clk D
setup time violation Q metastable state

ai
For internal circuits, we can make sure observe setup time But what if input comes from external (asynchronous) source, e.g., button press?
Partial solution
Insert synchronizer flip-flop for asynchronous input
Special flip-flop with very small setup/hold time
ai
Doesnt completely prevent metastability

synchronizer
Metastability
One flip-flop doesnt completely solve problem How about adding more synchronizer flip-flops?
Helps, but just decreases probability of metastability
So how solve completely?

Cant! May be unsettling to new designers. But we just cant guarantee a design that wont ever be metastable. We can just minimize the mean time between failure (MTBF) -- a number often given along with a circuit
Probability of flip-flop being metastable is very low very very low incredibly low
low ai
synchronizers
Flip-Flop Set and Reset Inputs

Some flip-flops have additional inputs
Synchronous reset: clears Q to 0 on next clock edge Synchronous set: sets Q to 1 on next clock edge Asynchronous reset: clear Q to 0 immediately (not dependent on clock edge)
Example timing diagram shown
D Q Q
D Q Q
D AR Q Q
AR
AS
cycle 1 clk
cycle 2
cycle 3
cycle 4
D AR
Asynchronous set: set Q to 1 immediately
Initial State of a Controller

All our FSMs had initial state
But our sequential circuit designs did not Can accomplish using flip-flops with reset/set inputs
Shown circuit initializes flip-flops to 01
Inputs: x; Outputs: b x=0 Off b x=1 On1
b Combinational logic s1 State register D Q Q s0
b x=1 On2 x=1 On3

x n1 n0
Designer must ensure reset input is 1 during power up of circuit

By electronic circuit design
clk
Q Q
reset
Glitching
Glitch: Temporary values on outputs that appear soon after input changes, before stable new output values Designer must determine whether glitching outputs may pose a problem
If so, may consider adding flipflops to outputs
Delays output by one clock cycle, but may be OK
clk
s p u o t M S F
b
n S i p F M u t s
Combinational Logic x
n1
n0
s1
s0
State register
The End
Lecture-26
A.Amalin Prince
10-10-07
Objective : Modular approach for CPU design Register-Transfer Level (RTL) Design
Introduction
U Know: Controllers
Control input/output: single bit (or just a few) representing event or state Finite-state machine describes behavior; implemented as state register and combinational logic
bi bo Combinational logic n1 s1 clk s0 n0 FSM outputs FSM inputs
State register
U know: Datapath components

Data input/output: Multiple bits collectively representing single entity Datapath components included registers, adders, ALU, comparators, register files, etc. Register
i s a n s i
Comparator Register file
ALU
e
Discussion: custom processors

Processor: Controller and datapath components working together to implement an algorithm
bi
bo
Combinational n1 logic n0 s1 s0 State register
Register file ALU
Datapath Controller
RTL Design: Capture Behavior, Convert to Circuit

Recall
Chapter 4 T1: Combinational Logic Design
First step: Capture behavior (using equation or truth table) Remaining steps: Convert to circuit
Chapter 5 T1: Sequential Logic Design

First step: Capture behavior (using FSM) Remaining steps: Convert to circuit
Capture behavior
RTL Design (the method for creating custom processors)

First step: Capture behavior (using highlevel state machine, to be introduced) Remaining steps: Convert to circuit
Convert to circuit
RTL Design Method
5th step may be required: Determine the clock frequency

RTL Design Method: Preview Example

Soda dispenser
c: bit input, 1 when coin deposited c a: 8-bit input having value of deposited coin d s: 8-bit input having cost of a soda d: bit output, processor sets to 1 when total value of deposited coins equals or 0 1 0 1 0 exceeds cost of a soda c
d s a
Soda dispenser processor
a 25
50
25
0 1 0
Soda tot: tot: dispenser 25 processor50
How can we precisely describe this processors behavior?
Preview Example: Step 1 -Capture High-Level State Machine

Declare local register tot Init state: Set d=0, tot=0 Wait state: wait for coin
If see coin, go to Add state
c d s 8 Soda dispenser processor a 8
Add state: Update total value: tot = tot + a

Remember, a is present coins value Go back to Wait state
Inputs: c (bit), a (8 bits), s (8 bits) Outputs: d (bit) Local registers: tot (8 bits) c Add Init d=0 tot=0 Wait tot=tot+a c*(tot<s) c*(tot<s) Disp d=1
In Wait state, if tot >= s, go to Disp(ense) state Disp state: Set d=1 (dispense soda)
Return to Init state
Preview Example:
Step 2 -- Create Datapath
Need tot register Need 8-bit comparator to compare s and tot Need 8-bit adder to perform tot = tot + a Wire the components as needed for above Create control input/outputs, give them names
Inputs: c (bit), a(8 bits), s (8 bits) Outputs: d (bit) Local registers: tot (8 bits) c Add Init d=0 tot=0 Wait c (tot<s) tot= tot+a c (tot<s) Disp d=1
tot_ld tot_clr 8
ld clr
tot 8 8
tot_lt_s
8-bit < Datapath
8-bit adder 8
Preview Example: Step 3

Connect Datapath to a Controller
Controllers inputs
External input c (coin detected) Input from datapath comparators output, which we named tot_lt_s
tot_ld tot_clr 8 s a ld clr tot
8 8-bit < 8-bit adder 8
tot_lt_s
Datapath
s 8
a 8
Controllers outputs
External output d (dispense soda) Outputs to datapath to load and clear the tot register
c d tot_ld tot_clr Controller tot_lt_s Datapath
Preview Example: Step 4 Derive the Controllers

FSM
Same states and arcs as high-level state machine But set/read datapath control signals for all c datapath operations d and conditions
c Controller Datapath d tot_ld tot_clr tot_lt_s s Inputs: tot_lt_s :c, (bit) Outputs: tot_ld tot_clr(bit) d, , tot_ld c Add Init Wait
c* t ot _lt _s
s a 8 8
tot_ld tot_clr 8
ld tpt clr 8 8-bit < Datapath 8
tot_clr tot_lt_s tot_lt_s
tot_ld=1 c*tot_lt_s Disp d=1
d=0 tot_clr=1
8-bit adder 8
Controller
Preview Example: Completing the Design

Implement the FSM as a state register and logic
Init tot_lt_s tot_clr tot_ld
As in Previous lecture Table shown on right

Inputs:c, tot_lt_s(bit) : Outputs:d, tot_ld, tot_clr (bit) tot_ld
s1 0 0 0 0 0 0 0 0 1 1
s0 0 0 0 0 1 1 1 1 0 1
c 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 0
n1 0 0 0 0 1 0 1 1 0 0
n0 1 1 1 1 1 1 0 0 1 0
d 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0
c d
Init Wait
c* tot _lt _s
c Add tot_ld=1 c*tot_lt_s Disp d=1
tot_clr tot_lt_s
Add Disp
d=0 tot_clr=1
Controller
Wait
Step 1: Create a High-Level State Machine

Lets consider each step of the RTL design process in more detail , Inputs: c (bit), a (8 bits) s (8 bits) Outputs: d (bit) Step 1
Soda dispenser example Not an FSM because:
Multi-bit (data) inputs a and s Local register tot Data operations tot=0, tot<s, tot=tot+a.
Local registers: tot (8 bits) c Init d=0 tot=0 Wait c(tot<s) tot= tot+a c (tot<s) Disp d=1
Useful high-level state machine:

Data types beyond just bits Local registers Arithmetic equations/expressions
Step 1: Create a High-Level State Machine

Creating a high-level state machine is not the only possible extension to an FSM.
Dozens of varieties of extended FSM exist. One example is ASM Charts U know? we will discuss later
That particular high-level state machine is sometime called as FSM with Data or FSMD Conventions same as FSM
Each transition is implicitly ANDed with raising clock edge Any bit output not explicitly assigned a value in a state is implicitly assigned a 0.
This convention does not apply for multibit outputs
The End
Lecture-27
A.Amalin Prince
12-10-07
RTL Design Method
5th step may be required: Determine the clock frequency

Step 1 Example: Laser-Based Distance Measurer

T (in seconds) laser D Object of interest 2D = T sec * 3*108 m/sec
sensor
Example of how to create a high-level state machine to describe desired processor behavior Laser-based distance measurement pulse laser, measure time T to sense reflection
Laser light travels at speed of light, 3*108 m/sec Distance is thus D = T sec * 3*108 m/sec / 2

T (in seconds) laser from button B Laser-based distance measurer L to laser
sensor
to display
16
S from sensor
Inputs/outputs
B: bit input, from button to begin measurement L: bit output, activates laser S: bit input, senses laser reflection D: 16-bit output, displays computed distance

from button B L Laserbased distance measurer
Inputs: B, S(1 bit each) Outputs: L (bit), D (16 bits)

to display D 16
to laser
from sensor
S0 L = 0 (laser off) D = 0 (distance = 0)
Step 1: Create high-level state machine Begin by declaring inputs and outputs Create initial state, name it S0
Initialize laser to off (L=0) Initialize displayed distance to 0 (D=0)

Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits) B (button not pressed)
from button B L Laserbased distance measurer to laser to display D 16 S from sensor
S0 L=0 D=0
S1
? B (button pressed)
Add another state, call S1, that waits for a button press
B stay in S1, keep waiting B go to a new state S2
Q: What should S2 do?

A: Turn on the laser

Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)
from button B L Laserbased distance measurer to laser to display D 16 S from sensor
S0 L=0 D=0
S1
S2 L=1 (laser on)
S3 L=0 (laser off)
Add a state S2 that turns on the laser (L=1) Then turn off laser (L=0) in a state S3 Q: What do next? A: Start timer, wait to sense reflection

Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits) Local Registers: Dctr (16 bits)
to displ ay from but ton B Lase r-based distan ce measu rer L to laser D 16 S from sensor
S (no reflection) S (reflection) ?
S0 L=0 D=0
S1
S2 L=1
S3
Dctr = 0 (reset cycle count)
L=0 Dctr = Dctr + 1 (count cycles)
Stay in S3 until sense reflection (S) To measure time, count cycles for which we are in S3
To count, declare local register Dctr Increment Dctr each cycle in S3 Initialize Dctr to 0 in S1. S2 would have been O.K. too

from but ton B Lase r-based distan ce measu rer L to laser
Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits) Local Registers: Dctr (16 bits) B S0 L=0 D=0 S1 Dctr = 0 S2 L=1 S
to displ ay
16
from sensor
S3
S4
L=0 D = Dctr / 2 Dctr = Dctr + 1 (calculate D)
Once reflection detected (S), go to new state S4

Calculate distance Assuming clock frequency is 3x108, Dctr holds number of meters, so D=Dctr/2
After S4, go back to S1 to wait for button again

Step 2: Create a Datapath

Datapath must
Implement data storage Implement data computations
Look at high-level state machine, do three substeps

(a) Make data inputs/outputs be datapath inputs/outputs (b) Instantiate declared registers into the datapath (also instantiate a register for each data output) (c) Examine every state and transition, and instantiate datapath components and connections to implement any data computations
Instantiate: to introduce a new component into a design.

(a) Make data Local Registers: Dctr (16 bits) inputs/outputs be datapath B S inputs/outputs (b) Instantiate declared S4 S1 S2 S3 S0 registers into the B S datapath (also L=0 D = Dctr / 2 Dctr = 0 L=1 L=0 instantiate a D=0 Dctr = Dctr + 1 (calculate D) register for each data output) Datapath (c) Examine every Dreg_clr state and Dreg_ld transition, and clear clear I Dctr_clr instantiate Dctr: 16-bit Dreg: 16-bit count Dctr_cnt load register up-counter datapath Q Q components and connections to implement any 16 data computations
D
Inputs: B, S (1 bit each)
Outputs: L (bit), D (16 bits)

(c) (continued) Examine every state and transition, and instantiate datapath components and connections to implement any data computations
Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits) Local Registers: Dctr (16 bits) B S0 L=0 D=0
Datapath >>1 16 clear count Q 16 16 D
S S2 L=1 S3 S4
S1 Dctr = 0
D = Dctr / 2 L=0 Dctr = Dctr + 1 (calculate D)
Dreg_clr Dreg_ld Dctr_clr Dctr_cnt Dctr: 16-bit up-counter clear load
I Q
Dreg: 16-bit register
Step 2 Example Showing Mux Use

Localregisters : E , G, R (16 bits) ,F E F G E F G E F G
T0 R = E + F A T1 R = R + G R (a) (b) R
add_A_s0 add_B_s0
21 A
21
(c)
(d)
Introduce mux when one component input can come from more than one source
Step 3: Connecting the Datapath to a Controller

from button B Controller Dreg_clr Dreg_ld Dctr_clr Dctr_cnt D to display 16 300 MHz Clock Datapath S L to laser from sensor
Laser-based distance measurer example Easy just connect all control signals between controller and datapath
Datapath Dreg_clr Dreg_ld Dctr_clr Dctr_cnt clear count Q

>>1 16 Dctr: 16-bit up-counter 16 clear load I Q 16 D Dreg: 16-bit register
Step 4: Deriving the Controllers FSM

from button B Controller Dreg_clr Dreg_ld Dctr_clr Dctr_cnt D to displ y a 16 300 M Clock Hz Datapath S L to laser from sensor
Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits) Local Registers: Dctr (16 bits) B S
S0 L=0 D=0
S1 Dctr = 0
S2 L=1
S3
S4
L=0 D = Dctr / 2 Dctr = Dctr + 1 (calculate D)
Inputs: B, S FSM has same Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt structure as highB level state machine
Inputs/outputs all bits now Replace data operations by bit operations using datapath
S0
S1 L=0 Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 1 Dctr_cnt = 0 (clear count)
S2 L=1 Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser on)
S3
S4 L=0 Dreg_clr = 0 Dreg_ld = 1 Dctr_clr = 0 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting)
L=0 Dreg_clr = 1 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser off) A.Amalin Prince EEE/INSTR Group (clear D reg) CS GC391/EEE GC391/INSTR GC391
Digital Electronics and Computer Organization BITS-Pilani Goa Campus
L=0 Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 1 (laser off) (count up)
Step 4: Deriving the Controllers FSM

B S S0 L=0 Dreg_clr = 1 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser off) (clear D reg) S1 L=0 Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 1 Dctr_cnt = 0 (clear count) B S2 L=1 Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 0 (laser on) S3 S S4 L=0 Dreg_clr = 0 Dreg_ld = 1 Dctr_clr = 0 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting)
L=0 Dreg_clr = 0 Dreg_ld = 0 Dctr_clr = 0 Dctr_cnt = 1 (laser off) (count up)
Using shorthand of outputs not assigned implicitly assigned 0
Inputs: B, S
Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt B S
S0 L=0 Dreg_clr = 1 (laser off) (clear D reg)
S1 Dctr_clr = 1 (clear count)
S2 L=1 (laser on)
S3
S4 Dreg_ld = 1 Dctr_cnt = 0 (load D reg with Dctr/2) (stop counting)
L=0 Dctr_cnt = 1 (laser off) (count up)
Step 4
Controller from button B L Dreg_clr Dreg_ld Dctr_clr Dctr_cnt to display D 16
300 MHz Clock
Datapath
to laser from sensor
Datapath >>1 16 clear count Q Dctr: 16-bit up-counter 16 clear load I Q 16 D Dreg: 16-bit register
Dreg_clr Dreg_ld Dctr_clr Dctr_cnt
Inputs: B, S
Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt B S
S0 L=0 Dreg_clr = 1 (laser off) (clear D reg)
S1 Dctr_clr = 1 (clear count)
S2 L=1 (laser on)
S3
L=0 Dctr_cnt = 1 (laser off) (count up)
Implement FSM as state S4 register and Dreg_ld = 1 logic Dctr_cnt = 0 (load D reg with Dctr/2) (Studied) to (stop counting) complete the design
RTL Design Examples and Issues

Well use several more examples to illustrate RTL design Example: Bus interface
Master processor can read register from any peripheral
Each register has unique 4-bit address Assume 1 register/periph.
Per0 Per1 Master processor rd 32 4 D A Per15
to/from processor bus rd D A 32 Bus interface Q 32 Main part Peripheral 4 Faddr 4
Sets rd=1, A=address Appropriate peripheral places register data on 32-bit D lines
Periphs address provided on Faddr inputs (maybe from DIP switches, or another register)
RTL Example: Bus Interface

Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits) Outputs: D (32 bits) Local register: Q1 (32 bits) rd ((A = Faddr) and rd) WaitMyAddress (A = Faddr) and rd D = Z Q1 = Q rd SendData D = Q1
Step 1: Create high-level state machine

State WaitMyAddress
Output nothing (Z) on D, store peripherals register value Q into local register Q1 Wait until this peripherals address is seen (A=Faddr) and rd=1
State SendData
Output Q1 onto D, wait for rd=0 (meaning main processor is done reading the D lines)

Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits) Outputs: D (32 bits) Local register: Q1 (32 bits) rd ((A = Faddr) and rd) WaitMyAddress (A = Faddr) and rd D = Z Q1 = Q rd SendData D = Q1
clk Inputs rd State Outputs D

W Z
SD Q1
W Z
SD
SD Q1
W Z

Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits) Outputs: D (32 bits) Local register: Q1 (32 bits) rd ((A = Faddr) and rd) SendData WaitMyAddress (A = Faddr) D = Q1 and rd D = Z Q1 = Q A rd Q1_ld 4 Faddr 4 Q 32 ld Q1 = (4-bit) A_eq_ Faddr D_en 32
32 Datapath
Step 2: Create a datapath

(a) Datapath inputs/outputs (b) Instantiate declared registers (c) Instantiate datapath components and connections
Bus interface D

Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits) Outputs: D (32 bits) Local register: Q1 (32 bits) rd Inputs: rd, A_eq_Faddr= Faddr) ((A (bit) Outputs: Q1_ld, D_en (bit)rd) and rd SendData rd WaitMyAddress (A = Faddr) (A_eq_Faddr D = Q1 and rd D = Z and rd) Q1 = Q
WaitMyAddress D_en = 0 Q1_ld = 1 A_eq_Faddr and rd
rd Q1_ld
A 4
rd
Faddr 4 ld
Q 32 Q1 32
= (4-bit) A_eq_Faddr D_en Datapath
SendData D_en = 1 Q1_ld = 0
32
Bus interface
Step 3: Connect datapath to controller Step 4: Derive controllers FSM

RTL Example: Video Compression Sum of Absolute

Differences (SAD) Only difference: ball moving
Frame 1 Frame 2 Frame 1 Frame 2
Digitized
frame 1
Digitized
frame 2
Digitized
frame 1
Difference of
2 from 1
1 Mbyte
(a)
1 Mbyte
1 Mbyte
(b)
0.01 Mbyte
Video is a series of frames (e.g., 30 per second) Most frames similar to previous frame
Compression idea: just send difference from previous frame
Just send difference

compare
Frame 1
Differences (SAD)
Frame 2
Each is a pixel, assume represented as 1 byte (actually, a color picture might have 3 bytes per pixel, for intensity of red, green, and blue components of pixel)
Need to quickly determine whether two frames are similar enough to just send difference for second frame
Compare corresponding 16x16 blocks
Treat 16x16 block as 256-byte array
Compute the absolute value of the difference of each array item Sum those differences if above a threshold, send complete frame for second frame; if below, can use difference method (using another technique, not described)

Differences (SAD)
256-byte array 256-byte array
A SAD
B go
2 < 5 i ! 6 ( )
sad
integer
Want fast sum-of-absolute-differences (SAD) component

When go=1, sums the differences of element pairs in arrays A and B, outputs that sum

Differences (SAD)
A SAD B go sad
Inputs: A, B (256 byte memory); go (bit) Outputs: sad (32 bits) Local registers: sum, sad_reg (32 bits); i (9 bits) S0 go S1
2 < 5 i ! 6 ( )
!go sum = 0 i=0
S0: wait for go S1: initialize sum and index S2: check if done (i>=256) S3: add difference to sum, increment index S4: done, write to output sad_reg
(i<256)
S2 i<256 sum=sum+abs(A[i]-B[i]) S3 i=i+1 S4 sad_reg = sum

Differences (SAD)
Inputs: A, B (256 byte memory); go (bit) Outputs: sad (32 bits) Local registers: sum, sad_reg (32 bits); i (9 bits) S0 go S1
(i<256)
AB_addr i_lt_256 i_inc i_clr sum_ld sum_clr

2 < 5 i ! 6 ( )
A_data B_data
<256 9 i
!go sum = 0 i=0
8 32
S2 i<256 sum=sum+abs(A[i]-B[i]) S3 i=i+1
sum 32 32
abs 8
sad_reg_ld sad_reg Datapath 32 sad
) 6 5 2 t _ l i ( < !
S4
sad_reg=sum
Step 2: Create datapath


Differences (SAD)
go go i_inc sum=0 sum_clr=1 i=0 i_clr=1 i_clr sum_ld sum_clr
2 < 5 i ! 6 ( )
AB_ rd i_lt_256 <256
AB_addr
A_data B_data
S0 go S1
?
9 i
8 32
S2 i<256 i_lt_256 sum=sum+abs(A[i]-B[i]) S3 sum_ld=1; AB_rd=1 i=i+1 i_inc=1 S4
sum 32 32 sad_reg
abs 8
sad_reg_ld
i ( ) 6 5 2 _ l t < !
) 6 5 2 t _ l i ( < !
sad_reg=sum sad_reg_ld=1 Controller
32 sad
Step 3: Connect to controller Step 4: Replace high-level state machine by FSM A.Amalin Prince EEE/INSTR Group
CS GC391/EEE GC391/INSTR GC391 Digital Electronics and Computer Organization BITS-Pilani Goa Campus

Differences
Comparing software and custom circuit SAD
Circuit: Two states (S2 & S3) for each i, 256 is 512 clock cycles Software: Loop (for i = 1 to 256), but for each i, must move memory to local registers, subtract, compute absolute value, add to sum, increment i say about 6 cycles per array item 256*6 = 1536 cycles Circuit is about 3 times (300%) faster Later, well see how to build SAD circuit that is even faster
2 < 5 i ! 6 ( ) ) 6 5 2 t _ l i ( < !
(i<256)
S2 i<256 sum=sum+abs(A[i]-B[i]) S3 i=i+1
The End
Lecture-28
A.Amalin Prince
15-10-07
RTL Design Pitfalls and Good Practice

Common pitfall: Assuming register is update in the state its written
Final value of Q? Final state? Answers may surprise you
Value of Q unknown Final state is C, not D
Local registers: R, Q (8 bits) R<100 A R=99 Q=R B R=R+1 (a) R<100 clk R Q A 99 ? ? B 100 99 ? (b) C 100 ? C
R>=100 D
Why?
State A: R=99 and Q=R happen simultaneously State B: R not updated with R+1 until next clock cycle, simultaneously with state register being updated

Solutions
Read register in following state (Q=R) Insert extra state so that conditions use updated value Other solutions are possible, depends on the example
Local registers: R, Q (8 bits) R<100 A R=99 Q=R B R=R+1 Q=R (a) R<100 R>=100 clk R Q A 99 ? ? B 100 99 ? (b) B2 100 99 D 100 99 B2 C
R>=100 D

Common pitfall: Reading outputs
Outputs can only be written Solution: Introduce additional register, which can be written and read
Inputs: A, B (8 bits) Outputs: P (8 bits) Inputs: A, B (8 bits) Outputs: P (8 bits) Local register: R (8 bits)
S P=A (a)
T P=P+B
S R=A P=A (b)
T P=R+B

Good practice: Register all data outputs
In fig (a), output P would show spurious values as addition computes
Furthermore, longest register-to-register path, which determines clock period, is not known until that output is connected to another component
B R R
+ P (a)
Preg P
In fig (b), spurious outputs reduced, and longest register-to-register path is clear
(b)
Control vs. Data Dominated RTL Design

Designs often categorized as control-dominated or datadominated
Control-dominated design Controller contains most of the complexity Data-dominated design Datapath contains most of the complexity General, descriptive terms no hard rule that separates the two types of designs Laser-based distance measurer control dominated Bus interface, SAD circuit mix of control and data Now lets do a data dominated design
Data Dominated RTL Design Example: FIR Filter

Filter concept
Suppose X is data from a temperature sensor, and particular input sequence is 180, 180, 181, 240, 180, 181 (one per clock cycle) That 240 is probably wrong!
Could be electrical noise
X 12 clk digital filter 12
Filter should remove such noise in its output Y Simple filter: Output average of last N values
Small N: less filtering Large N: more filtering, but less sharp output

FIR filter
Finite Impulse Response Simply a configurable weighted sum of past input values y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
Above known as 3 tap Tens of taps more common Very general filter User sets the constants (c0, c1, c2) to define specific filter
X 12 clk digital filter 12 Y
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
RTL design
Step 1: Create high-level state machine
But there really is none! Data dominated indeed.
Go straight to step 2

Step 2: Create datapath
Begin by creating chain of xt registers to hold past values of X Suppose sequence is: 180, 181, 240
x(t) xt0 X clk 12 3-tap FIR filter x(t-1) xt1 12 x(t-2) xt2 12
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
240 180 181
180 181
180
12

Step 2: Create datapath (cont.)
Instantiate registers for c0, c1, c2 Instantiate multipliers to compute c*x values
x(t) xt0 X clk
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
c0
3-tap FIR filter x(t-1) c1 xt1
x(t-2) xt2
c2

Instantiate adders
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

3-tap FIR filter x(t) xt0 X clk c0 x(t-1) xt1 c1 x(t-2) xt2 c2

Add circuitry to allow loading of particular c register
CL Ca1 Ca0 C x(t) X clk xt0 c0 x(t-1) xt1 c1 x(t-2) xt2 c2 3 2x4 2 1 0 e X 12 clk digital filter 12 Y
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

3-tap FIR filter
* +
* +
*
yreg Y

Step 3 & 4: Connect to controller, Create FSM
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)
No controller needed Extreme data-dominated example (Example of an extreme control-dominated design an FSM, with no datapath)
Comparing the FIR circuit to a software implementation

Circuit
Assume adder has 2-gate delay, multiplier has 20-gate delay Longest past goes through one multiplier and two adders
20 + 2 + 2 = 24-gate delay
100-tap filter, following design on previous slide, would have about a 34-gate delay: 1 multiplier and 7 adders on longest path
Software
100-tap filter: 100 multiplications, 100 additions. Say 2 instructions per multiplication, 2 per addition. Say 10-gate delay per instruction. (100*2 + 100*2)*10 = 4000 gate delays
Circuit is more than 100 times faster (10,000% faster). Wow.

Determining Clock Frequency

Designers of digital circuits often want fastest performance
Means want high clock frequency
clk a b
Frequency limited by longest register-to-register delay

Known as critical path If clock is any faster, incorrect data may be stored into register Longest path on right is 2 ns
Ignoring wire delays, and register setup and hold times, for simplicity
2 ns delay
+
c
Critical Path
Example shows four paths
a to c through +: 2 ns a to d through + and *: 7 ns b to d through + and *: 7 ns b to d through *: 5 ns
2 ns delay
2 ns
1 / 7 ns = 142 MHz
Max
(2,7,7,5) = 7 ns
7 ns 7 ns
5 ns
Longest path is thus 7 ns Fastest frequency
+
7 ns 7 ns
5 ns delay
Critical Path Considering Wire Delays

Real wires have delay too
Must include in critical path
Example shows two paths

Each is 0.5 + 2 + 0.5 = 3 ns clk a 0.5 ns b 0.5 ns
Trend
1980s/1990s: Wire delays were tiny compared to logic delays But wire delays not shrinking as fast as logic delays
Wire delays may even be greater than logic delays!
+
3 ns
n s 3
2 ns 0.5 ns
3 ns
Must also consider register setup and hold times, also add to path Then add some time to the computed path, just to be safe
e.g., if path is 3 ns, say 4 ns instead
A Circuit May Have Numerous Paths

Paths can exist
In the datapath In the controller Between the controller and datapath May be hundreds or thousands of paths
Combinational logic
d
s 8
a 8
tot_ld c
tot_lt_s tot_clr (c) n1
ld
tot
clr 8
n0
tot_lt_s
8-bit < Datapath
8-bit adder
8
Timing analysis tools that evaluate all possible paths automatically very helpful
s1 clk
s0
(b) State register
(a)
The End
Lecture-29
A.Amalin Prince
17-10-07
RTL Design Optimizations and Tradeoffs

While creating datapath during RTL design, there are several optimizations and tradeoffs, involving
Pipelining Concurrency Component allocation Operator binding Operator scheduling
Pipelining
Intuitive example: Washing dishes with a friend, you wash, friend dries
You wash plate 1 Then friend dries plate 1, while you wash plate 2 Then friend dries plate 2, while you wash plate 3; and so on You dont sit and watch friend dry; you start on the next plate
Time
Without pipelining:
W1 D1 W2 D2 W3 D3
With pipelining:
W1 W2 W3 D1 D2 D3
Stage 1 Stage 2
Pipelining: Break task into stages, each stage outputs data for next stage, all stages operate concurrently (if they have data)
Pipelining Example
W X Y Z Stage 1 W X Y Z
+
s n 2 s n 2
+
2 n s 2 n s t s a g e 1
Longest path is only 2 ns pipeline registers
clk
Longest path is 2+2 = 4 ns Stage 2

s n 2
2ns
clk
So minimum clock period is 4ns clk S S(0) S(1)
2 n s
+
clk
So minimum clock period is 2ns
t s a g e 2
S S(0) S(1) S = W+X+Y+Z Datapath on left has critical path of 4 ns, so fastest clock period is 4 ns
Can read new data, add, and write result to S, every 4 ns
Datapath on right has critical path of only 2 ns

So can read new data every 2 ns doubled performance (sort of...)
Pipelining Example
W X Y Z W X Y Z
stage 1
2ns
2ns
2ns
+
Longest path is 2+2 = 4 ns
2ns
Longest path is only 2 ns pipeline registers
clk
clk
2ns
So mininum clock period is 4 ns clk S (a) S(0) S(1)
stage 2
2ns
+
clk S (b)
So mininum clock period is 2 ns
S(0)
S(1)
Pipelining requires refined definition of performance

Latency: Time for new data to result in new output data (seconds) Throughput: Rate at which new data can be input (items / second) So pipelining above system
Doubled the throughput, from 1 item / 4 ns, to 1 item / 2 ns Latency stayed the same: 4 ns
Recall: FIR Filter

CL Ca1 Ca0 C x(t) X clk xt0 c0 x(t-1) xt1 c1 x(t-2) xt2 c2 3 2x4 2 1 0 e 3-tap FIR filter
* +
* +
*
yreg Y
Pipeline Example: FIR Datapath

100-tap FIR filter: Row of 100 concurrent multipliers, followed by tree of adders
Assume 20 ns per multiplier 14 ns for entire adder tree Critical path of 20+14 = 34 ns
stage 1 20 ns
X xt registers
multipliers
Add pipeline registers

Longest path now only 20 ns Clock frequency can be nearly doubled
Great speedup with minimal extra hardware
pipeline registers adder tree

stage 2 14 ns
+ +
yreg Y
Concurrency
Concurrency: Divide task into Task subparts, execute subparts simultaneously
Dishwashing example: Divide stack into 3 substacks, give substacks to 3 neighbors, who work simultaneously -- 3 times speedup (ignoring time to move dishes to neighbors' homes) Concurrency does things side-byside; pipelining instead uses stages (like a factory line) Already used concurrency in FIR filter -- concurrent multiplications
Concurrency
Can do both, too
Pipelining
* *
Concurrency Example: SAD Design Revisited

Sum-of-absolute differences video compression example (Ch 5)
Compute sum of absolute differences (SAD) of 256 pairs of pixels Original : Main loop did 1 sum per iteration, 256 iterations, 2 cycles per iter.
AB_addr A_data B_data S0 go S1
(i<256)
!go sum = 0 i=0
i_lt_256 i_inc i_clr sum_ld sum_clr
<256 9 i
8 32 abs 8
S2 i<256 sum=sum+abs(A[i]-B[i]) S3 i=i+1 S4 sad_reg=sum
sum 32 32 sad_reg
sad_reg_ld
Datapath
32 sad
256 iters.*2 cycles/iter. = 512 cycles

-/abs/+ done in 1 cycle, but done 256 times

More concurrent design
Compute SAD for 16 pairs concurrently, do 16 times to compute all 16*16=256 SADs. Main loop does 16 sums per iteration, only 16 iters., still 2 cycles per iter.
go AB_ rd i_lt_16 S0 go !go sum_clr=1 i_clr=1 i_inc i_clr sum_ld sum_clr sad_ reg_ld sad_ reg sum abs abs abs abs i <16 AB_addr A0 B0 A1 B1 A14 B14 A15 B15
16 subtractors
Orig: 256*2 = 512 cycles
New: 16*2 = 32 cycles
S1
16 absolute values
) 6 1 t _ l i ! (
S2 i_lt_16 AB_ rd=1 sum_ld=1 i_inc=1 S4

sad_ reg_ld=1
i_lt_16
+
Adder tree to sum 16 values
+
Controller Datapath sad
All -/abs/+s shown done in 1 cycle, but done only 16 times

Comparing the two designs
Original: 256 iterations * 2 cycles/iter = 512 cycles More concurrent: 16 iterations * 2 cycles/iter = 32 cycles Speedup: 512/32 = 16x speedup
Versus software
Recall: Estimated about 6 microprocessor cycles per iteration
256 iterations * 6 cycles per iteration = 1536 cycles Original design speedup vs. software: 1536 / 512 = 3x
) 6 1 t _ l i ! (
(assuming cycle lengths are equal)
Concurrent designs speedup vs. software: 1536 / 32 = 48x
48x is very significant quality of video may be much better
Component Allocation
Another RTL tradeoff: Component allocation Choosing a particular set of functional units to implement a set of operations
e.g., given two states, each with multiplication
Can use 2 multipliers (*) OR, can instead use 1 multiplier, and 2 muxes Smaller size, but slightly longer delay due to the mux delay
A B A: (sl=0; sr=0; t1ld=1) B: (sl=1; sr=1; t4ld=1) t2 t5 t3 t6 sl 21 21 sr 2 mul 1 mul t1 t4 t1 (b) t4 delay (c)
t1 = t2*t3 t4 = t5*t6 FSM-A: (t1ld=1) B: (t4ld=1) t2 t3 t5 t6
(a)
Operator Binding
Another RTL tradeoff: Operator binding Mapping a set of operations to a particular component allocation
Note: operator/operation mean behavior (multiplication, addition), while component (aka functional unit) means hardware (multiplier, adder) Different bindings may yield different size or delay
A t1 = t2* t3 B t4 = t5* t6 C t7 = t8* t3 A t1 = t2* t3 B t4 = t5* t6 C t7 = t8* t3
sl 2x1
2 muxes 2x1 sr vs. 1 mux
sl 2x1
2 multipliers MULA allocated

t1 t4
size
t2
t3
t5 t8
t6 t3
t2 t8
t3
t5
t6
s i
Binding 1 Binding 2
MULB t7 t1
MULA t7
MULB t4
delay
Binding 1
Binding 2
Component allocation and Operator binding are sometimes refered to as Resource sharing
Operator Scheduling
Yet another RTL tradeoff: Operator scheduling Introducing or merging states, and assigning operations to those states.
A B C (some operations) A B B2 t4 = t5* t6 C (some operations) (some t1 = t2* t3 operations) t4 = t5* t6 t2 t5 t2 * t1 t3 t5 * t4
size
e z
(some t1 = t2*t3 operations) t4 = t5*t6
t3 t6 2x1 sr *
but more delay due to muxes
t6 3-state schedule
sl 2x1
i s
smaller (only 1 *)
4-state schedule
t1
t4
delay
Think over it?
Tasks of scheduling, allocation, and binding are all interdependent Modern tools may combine the tasks somewhat, and/or may iterate among the tasks several times, in search of good designs.
Operator Scheduling Example: Smaller FIR Filter

3-tap FIR filter design : Only one state datapath computes new Y every cycle
Used 3 multipliers and 2 adders; can we reduce the designs size?
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

Inputs: X (N bits) Outputs: Y (N bits) Local registers: xt0, xt1, xt2 (N bits) S1 xt0 = X xt1 = xt0 xt2 = xt1 Y = xt0*c0 + xt1*c1 + xt2*c2
CL Ca1 Ca0 C x(t) X clk xt0 c0 x(t-1) xt1 c1 x(t-2) xt2 c2 3 2x4 2 1 0 e 3-tap FIR filter
* +
* +
*
yreg Y

Reduce the designs size by re-scheduling the operations
Do only one multiplication operation per state
Inputs: X (N bits) Outputs: Y (N bits) Local registers: xt0, xt1, xt2 (N bits) S1 xt0 = X xt1 = xt0 xt2 = xt1 Y = xt0*c0 + xt1*c1 + xt2*c2 (a) Inputs: X (N bits) Outputs: Y (N bits) Local registers: xt0, xt1, xt2, sum (N bits) sum = 0 xt0 = N S1 xt1 = xt0 xt2 = xt1 S2 sum = sum + xt0 * c0
S3
sum = sum +xt1 * c1
y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

S4 sum = sum + xt2 * c2
S5
Y = sum (b)

Reduce the designs size by re-scheduling the operations
Do only one multiplication (*) operation per state, along with sum (+)
Inputs: X (N bits) Outputs: Y (N bits) Local registers: xt0, xt1, xt2, sum (N bits) sum = 0 xt0 = X S1 xt1 = xt0 xt2 = xt1 S2 sum = sum + xt0 * c0
X clk x_ld
xt0
c0
xt1
c1
xt2
c2
mul_s1 3x 1 mul_s0
S3 sum = sum + xt1 * c1
yreg 3x 1
*
y_ld MAC
S4
sum = sum + xt2 * c2
+
sum
S5
Y = sum
Multiplyaccumulate: a common datapath component

Many other options exist between fully-concurrent and fully-serialized
e.g., for 3-tap FIR, can use 1, 2, or 3 multipliers Can also choose fast array-style multipliers (which are concurrent internally) or slower shift-andadd multipliers (which are serialized internally) Each options represents compromises
concurrent FIR size compromises
serial FIR delay
More on Optimizations and Tradeoffs

Serial vs. concurrent computation has been a common tradeoff theme at all levels of design
Serial: Perform tasks one at a time Concurrent: Perform multiple tasks simultaneously
Combinational logic tradeoffs

Concurrent: Two-level logic (fast but big) Serial: Multi-level logic (smaller but slower)
abc + abd + ef (ab)(c+d) + ef essentially computes ab first (serialized)
Datapath component tradeoffs

Serial: Carry-ripple adder (small but slow) Concurrent: Carry-lookahead adder (faster but bigger)
Computes the carry-in bits concurrently
Also multiplier: concurrent (array-style) vs. serial (shift-and-add)
RTL design tradeoffs

Concurrent: Schedule multiple operations in one state Serial: Schedule one operation per state
Higher vs. Lower Levels of Design

Optimizations and tradeoffs at higher levels typically have greater impact than those at lower levels
RTL decisions impact size/delay more than gate-level decisions
Spotlight analogy: The lower you are, the less solution landscape is illuminated (meaning possible)
high-level changes
size
delay (a)
land (b)
Algorithm Selection
Chosen algorithm can have big impact
e.g., which filtering algorithm?
FIR is one type, but others require less computation at expense of lower-quality filtering
Linear search
0x00000000 0x00000001 0x0000000F 0x000000FF 64
Example: Quickly find items address in 256-word memory

One use: data compression. Many others. Algorithm 1: Linear search
Compare item with M[0], then M[1], M[2], ... 256 comparisons worst case
0: 1: 2: 3:
96: 128:
0x00000F0A 0x0000FFAA
96
128
Algorithm 2: Binary search (sort memory first)

Start considering entire memory range
If M[mid]>item, consider lower half of M If M[mid]<item, consider upper half of M Repeat on new smaller range Dividing range by 2 each step; at most 8 such divisions
Binary search
255:
0xFFFF0000 256x32 memory
Only 8 comparisons in worst case
Choice of algorithm has tremendous impact

Far more impact than say choice of comparator type
Power Optimization
energy (1=value in 2001)
Until now, weve focused on size and delay Power is another important design criteria
Measured in Watts (energy/second)
Rate at which energy is consumed
8 energy demand 4 battery energy density
Increasingly important as more transistors fit on a chip

Power not scaling down at same rate as size
Means more heat per unit area cooling is difficult Coupled with batterys not improving at same rate
Means battery cant supply chips power for as long
2 1 2001 03 05
07
09
CMOS technology: Switching a wire from 0 to 1 consumes power (known as dynamic power)
P = k * CV2f
k: constant; C: capacitance of wires; V: voltage; f: switching frequency
Power reduction methods

Reduce voltage: But slower, and theres a limit What else?
Power Optimization using Clock Gating

P = k * CV f
2
X xt0 c0 xt1 c1 xt2 c2
Much of a chips switching f (>30%) due to clock signals

After all, clock goes to every register Portion of FIR filter shown on right
Notice clock signals n1, n2, n3, n4
x_ld yreg clk n1 n2 n3 n4
y_ld clk n1, n2, n3 n4
Solution: Disable clock switching to registers unused in a particular state

Achieve using AND gates FSM only sets 2nd input to AND gate to 1 in those states during which register gets loaded
X
Much switchin g on clock wires

c0 xt1 c1 xt2 c2
xt0
x_ld s1 clk s5 y_ld clk yreg n1 n2 n3 n4
Note: Advanced method, usually done by tools, not designers

Putting gates on clock wires creates variations in clock signal (clock skew); must be done with great care
Greatly reduced n1, n2, n3 switching less power n4
Power Optimization using Low-Power Gates on Non-Critical Paths

size
Another method: Use low-power gates

Multiple versions of gates may exist
Fast/high-power, and slow/low-power, versions
high-power gates low-power gates on nonc ritical path low-power gates delay
e r
Use slow/low-power gates on non-critical paths

Reduces power, without increasing delay
a b c d e f g 1/1 nanowatts 1/1 nanoseconds f g 2/0.5 26 transistors 3 ns delay 5 nanowatts power 1/1 1/1 F1 a b c d e 2/0.5 26 transistors 3 ns delay 4 nanowatts power 1/1 1/1 F1
1/1
1/1
The End
Lecture-30
A.Amalin Prince
19-10-07
Objective : MEMORY COMPONENTS
Memory Components
Register-transfer level design instantiates datapath components to create datapath, controlled by a controller
A few more components are often used outside the controller and datapath
MxN memory
M words, N bits wide each
M words
N-bits wide each MN memory
Several varieties of memory, which we now introduce

Random Access Memory (RAM)

RAM Readable and writable memory
Random access memory
Strange name Created several decades ago to contrast with sequentially-accessed storage like tape drives
32 W_data 4 W_addr W_en 1632 register file R_data R_addr R_en 4 32
Logically same as register file Memory with address inputs, data inputs/outputs, and control
RAM usually just one port; register file usually two or more
Register file
RAM vs. register file

RAM typically larger than roughly 512 or 1024 words RAM typically stores bits using a bit storage approach that is more efficient than a flip flop RAM typically implemented on a chip in a square rather than rectangular shape keeps longest wires (hence delay) short
32 10
data addr rw en 1024 32 R AM
RAM block symbol
RAM Internal Structure

32 10 data addr rw en 1024x32 RAM
Let A = log2M
d0 addr0 addr1
r d a
wdata(N-1) wdata(N-2) wdata0 word enable

bit storage block (aka cell) word
addr(A-1)
clk
a0 a1 AxM d1 decoder a(A-1)
data cell word word enable enable rw data
d(M-1) to all cells
en rw
rdata(N-1) rdata(N-2) rdata0
RAM cell
Similar internal structure as register file

Decoder enables appropriate word based on address inputs rw controls whether cell is written or read
Dynamic RAM (DRAM)

32 10 data addr
addr
Let A = log2 M d0
wdata(N-1)
word enable
wdata(N-2) wdata0
bit storage block ,, (aka cell ) word ,,
rw en
1024x32 RAM
addr0 addr1
addr(A-1) clk en rw
a0 a1 A M d1 decoder a(A-1) e d(M-1) to all cells
data cell word word enable enable rw data
Dynamic RAM cell
rdata(N-1)
rdata(N-2)
rdata0
Relies on large capacitor to store bit

Write: Transistor conducts, data voltage level gets stored on top plate of capacitor Read: Just look at value of d Problem: Capacitor discharges over time
Must refresh regularly, by reading d and then writing it right back
Internal circuit of memory is beyond the scope of this course. You will do in later courses courses
Comparing Memory Types

Register file
Fastest But biggest size
MxN Memory implemented as a: register file SRAM DRAM
SRAM
Fast More compact than register file
DRAM
Slowest
And refreshing takes time
But very compact
Use register file for small items, SRAM for large items, and DRAM for huge items
Note: DRAMs big capacitor requires a special chip design process, so DRAM is often a separate chip
Size comparison for same number of bits (not to scale)
Reading and Writing a RAM

clk 1 addr data rw en RAM[9] RAM[13] now equals 500 now equals 999 9 500 13 999 Z 2 9 500 3 clk addr data rw valid setup time valid hold time setup time
500
1 means write
access time (b)
Writing
Put address on addr lines, data on data lines, set rw=1, en=1
Reading
Set addr and en lines, but put nothing (Z) on data lines, set rw=0 Data will appear on data lines
Dont forget to obey setup and hold times

In short keep inputs stable before and after a clock edge
RAM Example: Digital Sound Recorder

4096 16 RAM
data
addr
rw
wire microphone analog-todigital converter
16 ad_buf ad_ld 12
en
Ra Rrw Ren
da_ld
digital-toanalog converter
wire
processor
Behavior
Well use a 4096x16 RAM (12-bit wide RAM not common)
speaker
Record: Digitize sound, store as series of 4096 12-bit digital values in RAM Play back later Common behavior in telephone answering machine, toys, voice recorders
To record, processor should read a-to-d, store read values into successive RAM words
To play, processor should read successive RAM words and enable d-to-a

RTL design of processor
Create high-level state machine Begin with the record behavior Keep local register a
Stores current address, ranges from 0 to 4095 (thus need 12 bits)
16 analog-todigital converter ad_buf ad_ld 12 Ra Rw Ren da_ld digital-toanalog converter 4096x16 RAM
processor
Record behavior
Local register: a (12 bits) a<4095 S a=0 T ad_ld=1 ad_buf=1 Ra=a Rrw=1 Ren=1
Create state machine that counts from 0 to 4095 using a

For each a
Read analog-to-digital conv. ad_ld=1, ad_buf=1 Write to RAM at address a Ra=a, Rrw=1, Ren=1
U a=a+1 a=4095

Now create play behavior Use local register a again, create state machine that counts from 0 to 4095 again
For each a
Read RAM Write to digital-to-analog conv.
4096x16 RAM
data bus
16 analog-todigital converter ad_buf ad_ld 12 Ra Rw Ren da_ld digital-toanalog converter
processor
Note: Must write d-to-a one cycle after reading RAM, when the read data is available on the data bus
Play behavior
Local register: a (12 bits) a<4095 V a=0 W ad_buf=0 Ra=a Rrw=0 Ren=1
The record and play state machines would be parts of a larger state machine controlled by signals that determine when to record or play
X da_ld=1 a=a+1
a=4095
Read-Only Memory ROM

Memory that can only be read from, not written to
Data lines are output only No need for rw input
32 10 data addr rw en 1024 32 R AM
Advantages over RAM

Compact: May be smaller Nonvolatile: Saves bits even if power supply is turned off Speed: May be faster (especially than DRAM) Low power: Doesnt need power supply to save bits, so can extend battery life
RAM block symbol
32 10
data addr 1024x32 ROM en
Choose ROM over RAM if stored data wont change (or wont change often)
For example, a table of Celsius to Fahrenheit conversions in a digital thermometer
ROM block symbol
Read-Only Memory ROM

32 10 data addr en 1024x32 ROM
Let A = log2M
d0 addr0 addr1
r d a
word enable
ROM block symbol
bit storage block (aka cell) word
addr(A-1)
clk
a0 a1 AxM d1 decoder a(A-1)
data word word enable enable data
e en
d(M-1)
rdata(N-1) rdata(N-2) rdata0
ROM cell
Internal logical structure similar to RAM, without the data input lines
ROM Types
addr
addr0 addr1 addr(A-1) a0 a1 A M d1 decoder a(A-1) e d(M-1) word ,,
If a ROM can only be read, how are the stored bits stored in the first place?
Storing bits in a ROM known as programming Several methods
Let A = log2 M d0 word enable
bit storage block ,, (a cell )
en
cell word word enable enable data
data
data(N-1)
data(N-2)
data0
Mask-programmed ROM
Bits are hardwired as 0s or 1s during chip manufacturing
2-bit word on right stores 10 word enable (from decoder) simply passes the hardwired value through transistor
word enable
data line cell
data line cell
Notice how compact, and fast, this memory would be

ROM Types
addr
addr0 addr1
Each cell has a fuse A special device, known as a programmer, blows certain fuses (using higher-than-normal voltage)
Those cells will be read as 0s (involving some special electronics) Cells with unblown fuses will be read as 1s 2-bit word on right stores 10
addr(A-1)
a0 a1 A M d1 decoder a(A-1) e d(M-1)
word
en
data(N-1)
data(N-2)
data0
data line cell
1 cell
word enable fuse blown fuse
Also known as One-Time Programmable (OTP) ROM
,,
Fuse-Based Programmable ROM
data
data line
ROM Types
Uses floating-gate transistor in each cell Special programmer device uses higherthan-normal voltage to cause electrons to tunnel into the gate
Electrons become trapped in the gate Only done for cells that should store 0 Other cells (without electrons trapped in gate) will be 1
2-bit word on right stores 10
addr
addr0 addr1 addr(A-1) a0 a1 A M d1 decoder a(A-1) e en d(M-1) word ,,
Erasable Programmable ROM (EPROM)
data
data(N-1)
data(N-2)
data0
floating-gate transistor
data line cell 1
data line cell 0 ee
o r
word enable
n t i g a r t e t a g
Details beyond our scope just general idea is necessary here
trapped electrons
To erase, shine ultraviolet light onto chip

Gives trapped electrons energy to escape Requires chip package to have window
ROM Types
Electronically-Erasable Programmable ROM (EEPROM)
Similar to EPROM
Uses floating-gate transistor, electronic programming to trap electrons in certain cells
But erasing done electronically, not using UV light Erasing done one word at a time
Flash memory
Like EEPROM, but all words (or large blocks of words) can be erased simultaneously Become common relatively recently (late 1990s)
o r t n t i g a r t e
32 10
data addr en write busy 1024x32 EEPROM
Both types are in-system programmable
Can be programmed with new stored bits while in the system in which the ROM operates
Requires bi-directional data lines, and write control input Also need busy output to indicate that erasing is in progress erasing takes some time
ROM Example: Talking Doll

4096x16 ROM
Hello there! audio divided into 4096 samples, stored in ROM
speaker
Hello there!
Hello there!
16
digital-toanalog
Ra Ren
vibration sensor
converter da_ld v
processor
Doll plays prerecorded message, trigger by vibration

Message must be stored without power supply because ROM is nonvolatile Use a ROM, not a RAM,
And because message will never change, use a mask-programmed ROM or OTP ROM
Processor should wait for vibration (v=1), then read words 0 to 4095 from the ROM, writing each to the d-to-a
ROM Example: Talking Doll

Local register: a (12 bits) 4096x16 ROM a=0
a d
v S T Ra=a Ren=1 v a=4095 v
a<4095
16
Ra Ren
digital-toanalog converter da_ld
U da_ld=1 a=a+1
processor
High-level state machine

Create state machine that waits for v=1, and then counts from 0 to 4095 using a local register a For each a, read ROM, write to digital-to-analog converter
ROM Example: Digital Telephone Answering Machine

Using a Flash Memory
Want to record the outgoing announcement
When rec=1, record digitized sound in locations 0 to 4095 When play=1, play those stored sounds to digital-toanalog converter
b u y s
4096x16 Flash
Were not home.
What type of memory?

Should store without power supply ROM, not RAM Should be in-system programmable EEPROM or Flash, not EPROM, OTP ROM, or mask-programmed ROM Will always erase entire memory when reprogramming Flash better than EEPROM
analog-todigital converter
16 ad_buf ad_ld 12 Ra Rrw Ren er bu da_ld digital-toanalog converter
processor rec play speaker
record microphone
ROM Example: Digital Telephone Answering Machine

Using a Flash Memory
High-level state machine
Once rec=1, begin erasing flash by setting er=1 Wait for flash to finish erasing by waiting for bu=0 Execute loop that sets local register a from 0 to 4095, reading analog-todigital converter and writing to flash for each a
a w d r e n
4096x16 Flash
analog-todigital converter
16 ad_buf ad_ld 12 Ra Rrw Ren er bu da_ld digital-toanalog converter
processor rec record play speaker
microphone
S a=0 er=1 rec
Local register: a (13 bits) bu a<4096 T bu U er=0 ad_ld=1 ad_buf=1 Ra=a Rrw=1 Ren=1 a=a+1
V a=4096
Blurring of Distinction Between ROM and RAM

We said that
RAM is readable and writable ROM is read-only
ROM
Flash
RAM
EEPROM
NVRAM
But some ROMs act almost like RAMs

EEPROM and Flash are in-system programmable
Essentially means that writes are slow
Also, number of writes may be limited (perhaps a few million times)
And, some RAMs act almost like ROMs

Non-volatile RAMs: Can save their data without the power supply
One type: Built-in battery, may work for up to 10 years Another type: Includes ROM backup for RAM controller writes RAM contents to ROM before turning off
New memory technologies evolving that merge RAM and ROM benefits
e.g., MRAM
Bottom line
Lot of choices available to designer, must find best fit with design goals
Queues
A queue is another component sometimes used during RTL design Queue: A list written to at the back, from read from the front
Like a list of waiting restaurant customers
write items
to the back of the queue
back
front
read (and
remove) items from front of the queue
Writing called a push, reading called a pop Because first item written into a queue will be the first item read out, also called a FIFO (first-infirst-out)
Queues
7 6 5 4 3 2 1 0
Queue has addresses, and two pointers: rear and front

Initially both point to 0
Push (write)
Item written to address pointed to by rear rear incremented
A
rf 0 A
Pop (read)
Item read from address pointed to by front front incremented
7 B r 2 6 5 4 3 2
r 1 B
f 0 A f 0 A
If front or rear reaches 7, next (incremented) value should be 0 (for a queue with addresses 0 to 7)
1 B
Queues
Treat memory as a circle
If front or rear reaches 7, next (incremented) value should be 0 rather than 8 (for a queue with addresses 0 to 7)
7 6 5 4 3 2 1 B r f 0 A
Two conditions of interest

Full queue no room for more items
In 8-entry queue, means 8 items present No further pushes allowed until a pop occurs Causes front=rear 1 B
f
0 7
Empty queue no items

No pops allowed until a push occurs Causes front=rear 2
r
r
Both conditions have front=rear

To detect whether front=rear means full or empty, need state machine that detects if previous operation was push or pop, sets full or empty output signal (respectively)
3 4
Queue Implementation
Can use register file for item storage Implement rear and front using up counters
rear used as register files write address, front as read address
wdata 16 3 8 16 register file wdata waddr wr wr rd clr inc rdata raddr rd 3 16 rdata
clr inc 3-bit up counter front
Simple controller would set control lines for pushes and pops, and also detect full and empty situations
FSM for controller not shown
reset
Controller
3-bit up counter rear
eq
=
full empty 8-word 16-bit queue
Common Uses of a Queue

Computer keyboard
Pushes pressed keys onto queue, meanwhile pops and sends to computer
Digital video recorder

Pushes captured frames, meanwhile pops frames, compresses them, and stores them
Computer network routers

Pushes incoming packets onto queue, meanwhile pops packets, processes destination information, and forwards each packet out over appropriate port
Queue Usage Example

7 6 5 4 3 2 1 0
Example series of pushes and pops

Note how rear and front pointers move Note that popping doesnt really remove the data from the queue, but that data is no longer accessible Note how rear (and front) wraps around from address 7 to 0
Initially empty queue 7 1. After pushing 9, 5, 8, 5, 7, 2, 3 r 7 2. After popping r 7 3. After pushing 6 6 6 3 5 2 4 7 3 5 2 8 1 5 rf 0 9 f 0 9 data: 9
6 3
5 2
4 7
3 5
2 8
1 5 f 1 5 f 1 5 rf
6 3
5 2
4 7
3 5
2 8
0 9 r 0 3 full
Note: pushing a full queue is an error

As is popping an empty queue
7 4. After pushing 3 6
6 3
5 2
4 7
3 5
2 8
5. After pushing 4
ER ROR Pushing a full queue ! results in unknown state
The End
Lecture-31
A.Amalin Prince
22-10-07
Objective : Programmable Logic Devices (PLDs)
Digital Logic Devices
Cost of Digital Logic
Field Programmable Logic Devices (FPLD)
Implementation Options for Digital Logic

Assembly of SSI and MSI parts on PC boards.
mostly obsolete; still useful when just a few parts needed
Programmable Logic Devices (PLD)

variety of types, with different size and performance characteristics; largest have over 106 gate equivalents CAD tools enable simulation and automate device programming
Application Specific Integrated Circuits (ASIC)

design methods similar to PLDs
HDLs and simulation with synthesis using standard cell library plus physical design - placement of logic components and routing
can augment with custom design of critical components higher performance, greater logic density custom IC fabrication -- suitable for high production volumes
Programmable Logic Devices

Simple logic arrays
implement 2 level logic circuits (AND/OR) based on regular array structure several types
Read Only Memories (ROMs and PROMs) Programmable Logic Array (PLA) Programmable Array Logic (PAL)
Field Programmable Gate Arrays (FPGA)

many copies of common building block each block can be configured for different logic functions and typically includes a flip flop and a 4 input function generator programmable interconnect often includes SRAM blocks largest FPGAs have about 100K flip flops, 100K function generators and 10 Mb of SRAM
Read Only Memory (ROM)

Permanent binary information is stored Non-volatile memory
Power off does not erase information stored
K-bit address lines

K
ROM
2k words N-bit per work
N-bit Data Output

N
32x8 ROM
5
0 1 2 3
32x8 ROM
A4 A3 A2 Decoder A1 A0 Fuse can be implemented as a diode or a pass transistor 5-to-32
Each represents 32 wires
28 29 30 31
D7
D6
D5
D4
D3
D2
D1
D0
Programming the 32x8 ROM

A4 0 0 0 1 1 1 A3 0 0 0 1 1 1 A2 0 0 0 1 1 1 0 1 2 A1 0 0 1 0 1 1 A0 0 1 0 1 0 1 D7 1 1 1 0 0 1 D6 1 0 0 0 1 1 D5 0 0 1 0 0 1 D4 0 0 1 1 1 0 D3 0 1 0 0 0 0 D2 1 0 0 0 1 0 D1 0 1 0 0 1 0 D0 1 1 0 0 0 1
A4 A3 A2 A1 A0 Decoder 5-to-32
29 30 31
D7 D6 D5 D4 D3 D2 D1 D0
Example: Lookup Table

Design a square lookup table for F(X) = X2 using ROM
X 0 1 2 3 4 5 6 7
F(X)=X2 0 1 4 9 16 25 36 49
X 000 001 010 011 100 101 110 111
F(X)=X2 000000 000001 000100 001001 010000 011001 100100 110001
Square Lookup Table using ROM

0 X 000 001 010 011 100 101 110 111 F(X)=X2 000000 000001 000100 001001 010000 011001 100100 110001 1
X2 X1 X0
3-to-8 Decoder
2 3 4 5 6 7
F5
F4
F3
F2
F1
F0

0 X 000 001 010 011 100 101 110 111 F(X)=X2 000000 000001 000100 001001 010000 011001 100100 110001 1
X2 X1 X0
3-to-8 Decoder
2 3 4 5 6 7
F5
F4
F3
F2
F1
F0 = X0
Not Used

0 1 X 000 001 010 011 100 101 110 111 F(X)=X
2
X2 X1 X0
3-to-8 Decoder
2 3 4 5 6 7
000000 000001 000100 001001 010000 011001 100100 110001
F5
F4
F3
F2
F1
F0
Classifying Three Basic PLDs

INPUT Fixed AND plane (decoder) Programmable Connections Programmable OR plane OUTPUT
(Programmable) Read-Only Memory (ROM) Programmable Connections
INPUT
Programmable AND plane
Programmable OR plane
OUTPUT
Programmable Logic Array (PLA)
INPUT
Programmable AND plane
Fixed OR plane
F/F OUTPUT
Programmable Array Logic (PAL) Devices

A.Amalin Prince EEE/INSTR Group expect CS GC391/EEE GC391/INSTR GC391 Digital Electronics and Computer Organization BITS-Pilani Goa Campus
PAL: trademark of AMD, use PAL as an adjective or to receive a letter from AMDs lawyers AMD
Programmable Logic Array (PLA)

A B C Programmable OR Plane
Programmable AND Plane C C B B A A
F2
Regular k-map minimization
PLA minimization
PLA Example
Example using PLA

F1(A, B, C) = F2(A,
m(0,1,2,4) B, C) = m(0,5,6,7)
F1 = AB + AC + BC F1 = AB + AC + BC F2 = AB + AC + ABC
Example using PLA

A B C AB AC BC ABC C C B B A A
F1 = AB + AC + BC F2 = AB + AC + A B C
F1
F2
PAL Device
A Programmable AND Plane A A B B IO1 IO2 IO1 IO1 IO1
IO2
B Fixed OR Plane
PAL Device Design Example

A A B B C C D D IO1 IO1 IO1
Not programmed
IO2
IO1 = ABC + A BCD

IO2 = ABC + A BCD + ACD + A BCD
Example
Example (cont.)
Example (cont.)
Example (cont.)
The End
Lecture-32
A.Amalin Prince
24-10-07
Sequential Programmable Devices

SPLD (Sequential or Simple Programmable Logic Device) CPLD (Complex Programmable Logic Device) FPGA (Field Programmable Logic Device)
SPLD
I1 I2 I3
Simple Programmable Logic Devices (SPLDs)

Developed 1970s (thus, pre-dates FPGAs) Prefabricated IC with large ANDOR structure Connections can be "programmed" to create custom circuit
Circuit shown can implement any 3-input function of up to 3 terms
e.g., F = abc + a'c'
PLD IC programmable nodes
O1
Programmable Nodes in an SPLD

I1 I2 I3
Fuse based "blown" fuse removes connection Memory based 1 creates connection
programmable node
Fuse based
O1
(a) Fuse "unblown" fuse "blown" fuse
Memory based
PLD IC programmable nodes
mem 1 (b)
mem 0
Example: Seat Belt Warning Light System

Design circuit for warning light Sensors
s=1: seat belt fastened k=1: key inserted p=1: person in seat
Capture Boolean equation

person in seat, and seat belt not fastened, and key inserted
w = p AND NOT(s) AND k

k p BeltWarn w
Convert equation to circuit Notice

Boolean algebra enables easy capture as equation and conversion to circuit
How design with switches? Of course, logic gates are built from switches, but we think at level of logic gates, not switches
PLD Drawings and PLD Implementation Example

Common way of drawing PLD connections:
Uses one wire to represent all inputs of an AND Uses "x" to represent connection
Crossing wires are not connected unless "x" is present
I1 I2 I3 wired AND
I3I2'
O1
PLD IC
k p s
Example: Seat belt warning light using SPLD

k p BeltWarn w
kps'
0 PLD IC
Two ways to generate a 0 term
PLD Extensions
I1 I2 I3
O1
O2
PLD IC (a)
Two-output PLD
Sequential Programmable Logic Device
Basic Macrocell Logic

I1 I2 I3 programmable bit O1
2
FF
Macrocell
2
O2
FF PLD IC (b) clk
PLD with programmable registered outputs

Basic Macrocell Logic
More on PLDs
Originally (1970s) known as Programmable Logic Array PLA
Had programmable AND and OR arrays
AMD created "Programmable Array Logic" "PAL" (trademark)

Only AND array was programmable (fuse based)
Lattice Semiconductor Corp. created "Generic Array Logic "GAL"

(trademark)
Memory based
As IC capacities increased, companies put multiple PLD structures on one chip, interconnecting them
Become known as Complex PLDs (CPLD), and older PLDs became known as Simple PLDs (SPLD)
GENERALLY SPEAKING, difference of SPLDs vs. CPLDs vs. FPGAs:

SPLD: tens to hundreds of gates, and usually non-volatile (saves bits without power) CPLD: thousands of gates, and usually non-volatile FPGA: tens of thousands of gates and more, and usually volatile (but no reason why couldn't be non-volatile)
General CPLD
CPLD structure
Logic block I/O block PLD PLD PLD PLD
Interconnects
PLD
PLD
PLD
PLD
Field Programmable Gate Arrays

FPGAs can be used to construct more complex circuits. Chip contains a large number (tens of thousands) of configurable logic building blocks.
typically each block includes a 4 input function generator, a flip flop and some glue logic CAD tools map high level circuit to basic blocks, configuring function generators & other configurable elements as needed
Programmable interconnect used to wire logic blocks.

wire segments connected to logic blocks and to other wire segments by configurable switches CAD tools determine switch configuration needed to provide right connectivity
CAD tools perform mapping, placement, routing.

routing information used in timing analysis & simulation
Programmable IC Technology FPGA

Manufactured IC technologies require weeks to months to fabricate
And have large (hundred thousand to million dollar) initial costs
Programmable ICs are pre-manufactured

Can implement circuit today Just download bits into device Slower/bigger/more-power than manufactured ICs
But get it today, and no fabrication costs
Popular programmable IC FPGA

"Field-programmable gate array"
Developed late 1980s Though no "gate array" inside
Named when gate arrays were very popular in the 1980s
Programmable in seconds
FPGA Internals: Lookup Tables (LUTs)

Basic idea: Memory can implement combinational logic
e.g., 2-address memory can implement 2-input logic 1-bit wide memory 1 function; 2-bits wide 2 functions
Such memory in FPGA known as Lookup Table (LUT)

F = x'y' + xy 4x1 Mem. x 0 0 1 1 y 0 1 0 1 F 1 0 0 1 1 rd 0 1 2 3 D F (a) (b) (c) 1 0 0 1 1 rd 0 1 2 3 D F=1 (d) F G (e) 1 0 0 1 4x1 Mem. F = x'y' + xy G = xy' x y F G 1 0 0 0 0 1 1 0 x y 1 4x2 Mem. rd 0 10 1 00 2 01 3 10 a1 a0 D1 D0
0 0 0 1 1 0 1 1
x y
a1 a0
x=0 y=0
a1 a0
Circuit for 2 input LUT

x1 0/1 0/1 0/1 0/1 x2
(a) Circuit for a two-input LUT
x1 x2 0 0 1 1 0 1 0 1
f1 1 0 0 1
(b) f 1 = x 1 x 2 + x 1 x 2
x1 1 0 0 1
f1
x2
(c) Storage cell contents in the LUT

Example: Seat-belt warning light (again)
k p BeltWarn w k 0 0 0 0 1 1 1 1 p 0 0 1 1 0 0 1 1 s 0 1 0 1 0 1 0 1 w 0 0 0 0 0 0 1 0
s (a) 8x1 Mem. 0 0 1 0 2 0 3 0 a2 0 a1 4 0 a0 5 6 1 7 0 IC D w

(b)
k p s
Programming (seconds)
Fab 1-3 months
(c)

Lookup tables become inefficient for more inputs
3 inputs 8 inputs only 8 words 256 words; 16 inputs 65,536 words!
FPGAs thus have numerous small (3, 4, 5, or even 6-input) LUTs

If circuit has more inputs, must partition circuit among LUTs Example: Extended seat-belt warning light system:
Sub-circuits have only 3-inputs each
k p s t d (a) BeltWarn w k p s t d 3 inputs 1 output x=kps' (b) 3 inputs 1 output w=x+t+d k p s BeltWarn x w
kps'
x+ t+ d
t d
8x1 Mem. 0 0 1 0 2 0 3 0 a2 0 a1 4 0 a0 5 6 1 7 0 D
8x1 Mem. 0 0 1 1 2 1 3 1 a2 1 a1 4 1 a0 5 6 1 7 1 D w
5-input circuit, but 3input LUTs available

Partition circuit into 3-input sub-circuits
(c)
Map to 3-input LUTs

Partitioning among smaller LUTs is more size efficient
Example: 9-input circuit
a b c d e f g h i (a) a b c d e f g h i 512x1 Mem.
3x1 3x1 3x1 (b) 3x1 F
8x1 Mem.
(c)
Original 9-input circuit
Partitioned among 3x1 LUTs
Requires only 4 3-input LUTs (8x1 memories) much smaller than a 9-input LUT (512x1 memory)

LUT typically has 2 (or more) outputs, not just one Example: Partitioning a circuit among 3-input 2-output lookup tables
a b c d e a b c d e (b) 1 2 3 (a) t a b c F 3 d e (c) 8x2 Mem. 0 F 1 2 3 a2 a1 4 a0 5 6 7 00 00 00 00 00 00 00 01 t F 8x2 Mem. 0 1 2 3 a2 a1 4 a0 5 6 7 00 10 00 10 00 10 10 10
1 2
D1 D0
D1 D0
(Note: decomposed one 4input AND input two smaller ANDs to enable partitioning into 3-input sub-circuits)
First column unused; second column implements AND
Second column unused; first column implements AND/OR sub-circuit

Example: Mapping a 2x4 decoder to 3-input 2-output LUTs
out put s
d0 d1 d2 d3 0 i1 i0 8x2 Mem. 0 10 1 01 2 00 3 00 a2 a1 4 00 a0 5 00 6 00 7 00 D1 D0 d0 d1 8x2 Mem. 0 00 1 00 2 10 3 01 a2 a1 4 00 a0 5 00 6 00 7 00 D1 D0 d2 d3
uit
h as
2 in
put
s, 2
S ub
-cir c
i1
i0
(a)
Su in b-c pu i r ts, cui 2o th ut a s 2 pu ts
(b)
The End
Lecture-33
A.Amalin Prince
26-10-07
Programmable IC Technology FPGA

Manufactured IC technologies require weeks to months to fabricate
And have large (hundred thousand to million dollar) initial costs
Programmable ICs are pre-manufactured

Can implement circuit today Just download bits into device Slower/bigger/more-power than manufactured ICs
But get it today, and no fabrication costs
Popular programmable IC FPGA

"Field-programmable gate array"
Developed late 1980s Though no "gate array" inside
Named when gate arrays were very popular in the 1980s
Programmable in seconds

Basic idea: Memory can implement combinational logic
e.g., 2-address memory can implement 2-input logic 1-bit wide memory 1 function; 2-bits wide 2 functions
Such memory in FPGA known as Lookup Table (LUT)

F = x'y' + xy 4x1 Mem. x 0 0 1 1 y 0 1 0 1 F 1 0 0 1 1 rd 0 1 2 3 D F (a) (b) (c) 1 0 0 1 1 rd 0 1 2 3 D F=1 (d) F G (e) 1 0 0 1 4x1 Mem. F = x'y' + xy G = xy' x y F G 1 0 0 0 0 1 1 0 x y 1 4x2 Mem. rd 0 10 1 00 2 01 3 10 a1 a0 D1 D0
0 0 0 1 1 0 1 1
x y
a1 a0
x=0 y=0
a1 a0
Circuit for 2 input LUT

x1 0/1 0/1 0/1 0/1 x2
(a) Circuit for a two-input LUT
x1 x2 0 0 1 1 0 1 0 1
f1 1 0 0 1
(b) f 1 = x 1 x 2 + x 1 x 2
x1 1 0 0 1
f1
x2
(c) Storage cell contents in the LUT

Example: Seat-belt warning light (again)
k p BeltWarn w k 0 0 0 0 1 1 1 1 p 0 0 1 1 0 0 1 1 s 0 1 0 1 0 1 0 1 w 0 0 0 0 0 0 1 0
s (a) 8x1 Mem. 0 0 1 0 2 0 3 0 a2 0 a1 4 0 a0 5 6 1 7 0 IC D w

(b)
k p s
Programming (seconds)
Fab 1-3 months
(c)

Lookup tables become inefficient for more inputs
3 inputs 8 inputs only 8 words 256 words; 16 inputs 65,536 words!
FPGAs thus have numerous small (3, 4, 5, or even 6-input) LUTs

If circuit has more inputs, must partition circuit among LUTs Example: Extended seat-belt warning light system:
Sub-circuits have only 3-inputs each
k p s t d (a) BeltWarn w k p s t d 3 inputs 1 output x=kps' (b) k p s BeltWarn x w
kps'
5-input circuit, but 3input LUTs available

x+ 3 inputs t+ d 1 output
w=x+t+d t d
8x1 Mem. 0 0 1 0 2 0 3 0 a2 0 a1 4 0 a0 5 6 1 7 0 D
8x1 Mem. 0 0 1 1 2 1 3 1 a2 1 a1 4 1 a0 5 6 1 7 1 D w
Partition circuit into 3-input sub-circuits
(c)
Map to 3-input LUTs

Partitioning among smaller LUTs is more size efficient
Example: 9-input circuit
a b c d e f g h i (a) a b c d e f g h i 512x1 Mem.
3x1 3x1 3x1 (b) 3x1 F
8x1 Mem.
(c)
Original 9-input circuit
Partitioned among 3x1 LUTs
Requires only 4 3-input LUTs (8x1 memories) much smaller than a 9-input LUT (512x1 memory)

LUT typically has 2 (or more) outputs, not just one Example: Partitioning a circuit among 3-input 2-output lookup tables
a b c d e a b c d e (b) 1 2 3 (a) t a b c F 3 d e (c) 8x2 Mem. 0 F 1 2 3 a2 a1 4 a0 5 6 7 00 00 00 00 00 00 00 01 t F 8x2 Mem. 0 1 2 3 a2 a1 4 a0 5 6 7 00 10 00 10 00 10 10 10
1 2
D1 D0
D1 D0
(Note: decomposed one 4input AND input two smaller ANDs to enable partitioning into 3-input sub-circuits)
First column unused; second column implements AND
Second column unused; first column implements AND/OR sub-circuit

Example: Mapping a 2x4 decoder to 3-input 2-output LUTs
out put s
d0 d1 d2 d3 0 i1 i0 8x2 Mem. 0 10 1 01 2 00 3 00 a2 a1 4 00 a0 5 00 6 00 7 00 D1 D0 d0 d1 8x2 Mem. 0 00 1 00 2 10 3 01 a2 a1 4 00 a0 5 00 6 00 7 00 D1 D0 d2 d3
uit
h as
2 in
put
s, 2
S ub
-cir c
i1
i0
(a)
Su in b-c pu i r ts, cui 2o th ut a s 2 pu ts
(b)
FPGA Internals: Switch Matrices

Previous slides had hardwired connections between LUTs Instead, want to program the connections too Use switch matrices (also known as programmable interconnect)
Simple mux-based version each output can be set to any of the four inputs just by programming its 2-bit configuration memory
FPGA (partial) 8x2 Mem. 0 00 1 00 2 00 3 00 a2 a1 4 00 a0 5 00 6 00 7 00 D1 D0 8x2 Mem. 0 00 1 00 2 00 3 00 a2 a1 4 00 a0 5 00 6 00 7 00 D1 D0 P8 P9 Switch matrix 2-bit memory m0 m1 m2 m3 s1 s0 i0 o0 i1 4x1 i2 mux d i3 2-bit memory s1 s0 i0 o1 i1 4x1 i2 mux d i3 (b)
P0 P1 P2 P3
P6 P7
o0 o1 m0 m1 m2 m3 Switch matrix
P4 P5
(a)

Mapping a 2x4 decoder onto an FPGA with a switch matrix
These bits establish the desired connections
FPGA (partial) 8x2 Mem. 0 1 2 3 a2 a1 4 a0 5 6 7 10 01 00 00 00 00 00 00 8x2 Mem. 0 1 2 3 a2 a1 4 a0 5 6 7 00 00 10 01 00 00 00 00 Switch matrix 10 s1 s0 i0 o0 i1 4x1 d i2 mux i3 11 s1 s0 i0 o1 i1 4x1 i2 mux d i3 (b)
0 0 i1 i0
d3 d2
D1 D0
10 o0 m0 11 o1 m1 m2 m3 Switch matrix
m0 m1 m2 m3
D1 D0 d1 d0
i1 i0 (a)

Mapping the extended seatbelt warning light onto an FPGA with a switch matrix
Recall earlier example (let's ignore d input for simplicity)
FPGA (partial) 8x2 Mem. 0 00 1 00 2 00 3 00 a2 a1 4 00 a0 5 00 6 01 7 00 D1 D0 8x2 Mem. 0 00 1 01 2 01 3 01 a2 a1 4 00 a0 5 00 6 00 7 00 D1 D0
k p s t d
BeltWarn x w
Switch matrix 00 s1 s0 i0 o0 i1 4x1 d i2 mux i3 10 s1 s0 i0 o1 i1 4x1 d i2 mux i3 (b)
0 k p s
m0 m1 m2 m3
t 0 (a)
FPGA Internals: Configurable Logic Blocks (CLBs)

LUTs can only implement combinational logic Need flip-flops to implement sequential logic Add flip-flop to each LUT output
Configurable Logic Block (CLB)
LUT + flip-flops
FPGA CLB 8x2 Mem. 0 1 2 3 a2 a1 4 a0 5 6 7 D1 00 00 00 00 00 00 00 00 D0 CLB 8x2 Mem. 0 1 2 3 a2 a1 4 a0 5 6 7 D1 00 00 00 00 00 00 00 00 D0
P0 P1 P2 P3
CLB output flip-flop
Can program CLB outputs to come from flip-flops or from LUTs directly
1-bit CLB output configuration memory P4 P5
10
2x1 0
10
2x1
10
2x1 0
10
2x1 P6 P7 P8 P9
FPGA Internals: Sequential Circuit Example using CLBs

a b c d CLB 8x2 Mem. 0 1 2 3 a2 4 a1 a0 5 6 7 D1 11 10 01 00 00 00 00 00 D0 FPGA CLB 8x2 Mem. 0 1 2 3 a2 4 a1 a0 5 6 7 D1 00 01 10 11 00 00 00 00 D0
x (a)
0 0 a b
Left lookup table a2 0 0 0 0 0 a1 a 0 0 1 1 a0 b 0 1 0 1 D1 1 1 0 0 D0 1 0 1 0 c d 1
w=a' x=b' 2 x1 1
10 10
2 x1
2 x1 1
10
10
2 x1 z y x w
below unused (b)
(c)
FPGA Internals: Overall Architecture

Consists of hundreds or thousands of CLBs and switch matrices (SMs) arranged in regular pattern on a chip
Represents channel with tens of wires Connections for just one CLB shown, but all CLBs are obviously connected to channels
CLB SM CLB SM CLB CLB CLB SM CLB SM CLB CLB
CLB
FPGA Internals: Configuration memory

The storage elements for the lookup table, the CLB output configuration, and the switch matrices, are collectively known as an FPGAs configuration memory, although that memory is comprised of numerous smaller memories and even registers or flip-flops.
Programming an FPGA
FPGA Internals: Programming an FPGA

All configuration memory bits are connected as one big shift register
Known as scan chain
(a) FPGA CLB 8x2 Mem. 0 11 1 10 2 01 3 01 a2 4 00 a1 a0 5 00 6 00 7 00 D1 D0 CLB 8x2 Mem. 0 01 1 00 2 11 3 10 a2 4 00 a1 a0 5 00 6 00 7 00 D1 D0 Pin Pclk 0 0 a b
Shift in "bit file" of desired circuit

c d
2 x1 1
2x1
2 x1 1
2 x1 z y x w
(b) Pin
Pclk (c) Bit file contents for desired circuit: 1101101000000000111101100011010000000011

Conceptual view of configuration bit scan chain is that of a 40-bit shift register
This isn't wrong. Although the bits appear as "10" above, note that the scan chain passes through those bits from right to left so "01" is correct here.
FPGA Structure
Logic block
I/O block
Interconnects
Xilinx FPGA Organization

switch matrix wire segments
configurable logic blocks (CLB)
IO blocks (IOB)
CLBs can be connected to passing wires. Wire segments connected by switch matrix. Long wire segments used to connect distant CLBs. Configuration information stored in SRAM bits that are loaded when power turns on.
FPGA Programmability
Floating gate transistor
Used in EPROM and EEPROM
SRAM-controlled switch Control

Pass transistors Multiplexers (to determine how to route inputs)
Antifuse
Similar to fuse Originally an Open-Circuit One-Time Programmable (OTP)
Xilinx Configurable Logic Block

Main Function Generators
G1 G2 G3 G4
Clock Edge Select CLK EC S/R

Y
S/R C
LUT4
D >
EC CLR PRE
Set/Reset Control
YQ
DIN H1 LUT3 1
F1 F2 F3 F4
Clock Enable Control

D
PRE
LUT4
>
EC CLR
XQ
Main Function Generators

Flip Flop
1
S/R C
Implementing Serial Adder in CLB

Sum Function
A B 0
CLK
EC
S/R Sum
01101001 01101101
LUT4
ABCarry
S/R C D
0
PRE
DIN
01
>
EC CLR
Carry
H1
LUT3 1
1
State Flip Flop
D EN
00000000 00010111
PRE
LUT4
(AB+ACarry +BCarry)EN 1
>
EC CLR
XQ
Carry Function
S/R C
Second flip flop still available and LUT3 partially available.
How many gates does an FPGA Implement?

A common method of indicating design size for a circuit approximate the number of 2-input NAND gates that would be required to implement the circuit. FPGA have lookup tables and switch matrices inside, not gates. FPGA size are therefore typically reported by considering how large of a circuit made up of 2-input NAND gates could be implemented using the FPGA architecture. FPGA vendors may report FPGA size by saying a particular FPGA has
Density of 100,000 system gates But approximate 100,000 typical gates
FPGA versus ASICs and Microprocessors

FPGAs are less efficient than ASICs in terms of delay, size and power Despite the performance, size, and power overhead compared to ASICs, FPGAs are still much faster than software on a microprocessor for many tasks, in part FPGAs can effectively implement concurrency, pipelining, and bit-level operations. Thus FPGAs posses the programming flexibility of software on a microprocessor, yet approach the performance of an ASIC, representing an excellent implementation option for many design.
The End
Company headquarters in Hillsboro. Xilinx San Jose HQ Building at 2100 Logic Drive Altera headquarters in San Jose
Mountain View, CA 94043-4655, USA
Lecture-34
A.Amalin Prince
29-10-07
Objective : Algorithmic State Machines (ASM Chart)
The Algorithmic State Machine
Partitioning of a digital system.
The Algorithmic State Machine
Model of an algorithmic state machine
Algorithmic State Machine

Algorithmic State Machine representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables.
Timing of an algorithmic State Machine
Elements used in ASM charts: The state box
Elements used in ASM charts: The state box

State box represents a state. Equivalent to a node in a state diagram or a row in a state table. Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be useful to write an action to be taken, e.g., Count = Count + 1, and only later translate it to asserting a control signal that causes a given action to take place.
Elements used in ASM charts: The decision box
(a) Symbol
(b) Alternate symbol
Elements used in ASM charts: The decision box

Decision box indicates that a given condition is to be tested and the exit path is to be chosen accordingly The condition expression consists of one or more inputs to the FSM.
Elements used in ASM charts: The conditional Output box
Elements used in ASM charts: The conditional Output box

Conditional output box denotes output signals that are of the Mealy type. The condition that determines whether such outputs are generated is specified in the decision box.
Example of an ASM block and its link paths

Link path L1 = x1 x2 L2 = x1 x2 x3 L3 = x1 x3 L4 = x1 x2 x3 L5 = x1 x3
Two equivalent ASM blocks
a) Using a single decision box

(b) Using several decision boxes
(a) Parallel decision boxes
(b) Serial decision boxes
Invalid ASM block having nonunique next states

Two rules Rule-1
For any valid combination of values to the decision - box variables, all simultaneously selected link path must lead to the same exit path.
Looping
Rule-2
(a) Incorrect
(b) Correct
There is no closed loop that do not contain at least one state box.
ASM Chart for a mod-8 binary counter
ASM Chart for a mod-3 binary updown counter
Relationship between state diagrams and ASM charts
Moore sequential network. (a) State diagram. (b) ASM chart.
Mealy sequential network. (a) State diagram. (b) ASM chart.
Register Transfer Level (RTL) Design using ASM chart
The End
Lecture-35
A.Amalin Prince
07-11-07
Objective : Algorithmic State Machines (ASM Chart)
Moore sequential network. (a) State diagram. (b) ASM chart.
Mealy sequential network. (a) State diagram. (b) ASM chart.
Sequence recognizer (01, 01, 11, 00)
An ASM chart Binary multiplication
(a) Pencil-and-paper approach

(b) Add-shift approach
Architecture for a binary multiplier
ASM Chart for a Binary multiplier
State Assignment
ASM Transition table
Assigned ASM transition table
Algebraic Representation of assigned Transition Tables
Algebraic Representation of assigned Transition Tables
ASM Realizations using discrete gates with clocked D Flip-Flop
ASM Realizations using Multiplexers with clocked D Flip-Flop
Register Transfer Level (RTL) Design using ASM chart
The End
DECO
OBJECTIVE
Multiplication Division
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MULTIPLICATION
More complicated than addition Accomplished via shifting and addition Multiplication of two N- bit binary integers results in a product of up to 2N bits in length
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MULTIPLICATION OF UNSIGNED BINARY INTEGERS
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MULTIPLICATION OF SIGNED BINARY INTEGERS Booth Algorithm

Generates a 2N bit product Negative number is represented as in 2s complement form Sign bit is used to represent both the positive and negative numbers Multiplier is scanned from right to left
If there is a bit change from 0 to 1 then -1 times the shifted multiplicand is selected If there is a bit change from 1 to 0 then +1 times the shifted multiplicand is selected
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DIVISION
Accomplished via shifting and addition / subtraction More complicated
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Two methods
Restoration method Non-Restoration method
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HARDWARE IMPLEMENTATION
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RESTORATION METHOD
Steps
1. 2. 3. 4.
Set A to zero Shift A and Q left one binary position Subtract M from A and place the answer back in A If MSB of A is 1, set Q0 to 0 and add M back to A (restore A); otherwise set Q0 to 1
5.
Repeat steps 2,3 & 4 for N times
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Example:
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NON-RESTORATION METHOD
Steps
1. 2.
Set A to zero If MSB of A is 0, Shift A and Q left one binary position and Subtract M from A ;otherwise, shift A and Q left and add M to A
3.
Now, if MSB of A is 0 , set Q0 to 1 ; otherwise set Q0 to 0 Repeat steps 2 & 3 for N times If MSB of A is 1, add M to A
4. 5.
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Lecture-37
A.Amalin Prince
14-11-07
Objective : Asynchronous Sequential Logic
Introduction
Block Diagram of an Asynchronous Sequential Circuit
Fundamental mode
?
Analysis Procedure
Determine all feedback loops in the circuit Designate the output of each feedback loop with variable Yi, and its corresponding input with yi for i=1,2,,km where k is the number of feedback loops in the circuit. Derive the Boolean functions of all Ys as a function of the external inputs and the ys. Plot each Y function in a map, using the y variable for the rows and the external inputs for the columns. Combine all the maps into one table showing the value of Y=Y1Y2Yk inside each square. Circle those values of Y in each square that are equal to the value of y=y1y2yk in the same row.
Example1: Asynchronous Sequential Circuit
Y1 = xy1 + x ' y2
Y2 = xy '1 + x ' y2
Example1: Maps and Transition Table
Total state=internal state + inputs
Example 1: State Table

Present State 0 0 0 1 1 0 1 1 Next State x=0 x=1 0 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0
Example1:Flow table
Primitive flow table It has only one stable state in each row.
Example 2: Implementation using Gates Flow Table
Example 2:Transition table and Output map
Example 2: Logic diagram
Circuits with Latches
Circuits with Latches
Analysis with latches

Label each latch output with Yi and its external feedback path (if any) with yi for i=1,2,,k. Derive the Boolean function for the Si and Ri inputs in each latch. Check whether SR=0 for each NOR latch or whether SR=0 for each NAND latch. If this condition is not satisfied, there is a possibility that the circuit may not operate properly. Evaluate Y=S+Ry for each NOR latch or Y=S+Ry for each NAND latch. Construct a map with the ys representing the rows and the x inputs representing the columns. Plot the value of Y=Y1Y2,Yk in the map. Circle all stable states where Y=y. The resulting map is then the transition table.
Example 3: Circuit with SR NOR Latch

S1 = x1 y2 R1 = x '1 y '2 S 2 = x1 x2 R2 = x '1 x2
check whether the condition SR = 0

S1 R1 = x1 y2 x '1 y '2 S 2 R2 = x1 x2 x '1 x2
The result is 0
Example 2: Excitation function
Y = S + R' y
Y = S1 + R'1 y1 = x1y2 + (x1 + x2 ) y1 = x1y2 + x1y1 + x2 y1 1 Y2 = S2 + R'2 y2 = x1x2 + (x2 + y '1) y2 = x1x2 + x2 y2 + y '1 y2
Example 3: Transition table
Flow Table ?
Implementation Procedure
Given a transition table that specifies the excitation function Y=Y1Y2,Yk, derive a pair of maps for Si and Ri for each i=1,2,,k. Derive the simplified Boolean functions for each Si and Ri. Care must be taken not to make Si and Ri equal to 1 in the same minterm square. Draw the logic diagram using k latches together with the gates required to generate the S and R Boolean functions. For NOR latches, use the S and R Boolean functions obtained in step 2. For NAND latches, use the complemented values of those obtained in step-2
Example 4: Implementation using SR Latch Flow table
Example 4: Transition Table and Map
Example 4: Circuit with NOR Latch
Example 4: Circuit with NAND Latch
The End
Lecture-38
A.Amalin Prince
16-11-07
Reduction of State and Flow Tables

State table to be reduced
Present State a b c d e f
Next Output State x=0 x=1 x=0 x=1 d e g a a c a b a f d d b e 0 0 0 1 1 0 1 0 0 1 0 0 0 0
Implication Table
Present State a c d f Next State d d a c a f d a Output
x=0 x=1 x=0 x=1 0 0 1 0 0 1 0 0
Merging of the Flow Table

Incompletely specified function
Determine all compatible pairs by using the implication table. Find the maximal compatibles using merger diagram. Find a minimal collection of compatibles that covers all the states and is closed.
Step1: Compatible Pairs
Compatible pairs are

(a, b) (a, c) (a, d ) (b, e) (b, f ) (c, d ) (e, f )
Step2:Maximal Compatibles (Merger Diagram)
Example1: Step3:Closed Covering Condition

A closed set of compatibles that covers all the state is called a closed covering. Consider the previous example
If we remove (a,b), we are left with a set of two compatibles: (a,c,d) (b,e,f) All six states from the flow table are included in this set. This satisfies the covering condition. There are no implied states for (a,c); (a,d); (c,d); (b,e); (b,e); (b,f); and (e,f). So the closure condition is also satisfied.
Example2: Step3:Closed Covering Condition
The End
Lecture-39
A.Amalin Prince
19-11-07
Race Conditions
A race is said to exist in an asynchronous sequential circuit when two or more binary state variables change value in response to a change in an input variable. Race may cause the state variables to change in an unpredictable manner. If the final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called a noncritical race. If it is possible to end in two or more different stable states, depending on the order in which the state variable change, then it is a critical race. For proper operation, critical race must be avoided.
Examples of Noncritical Races
Examples of Critical Races
Examples of Cycles
When a circuit goes through a unique sequence of unstable states, it is said to have a cycle
Stability Considerations
Y = ( x1 y ) ' x2 = ( x '1 + y ') x2 = x '1 x2 + x2 y '
Race-Free State Assignment

Shared-Row Assignment

Shared-Row Assignment

Multiple-Row Assignment
Reduce The Primitive Flow table
Exercise
The End
Lecture-40
A.Amalin Prince
21-11-07
Design Procedure
Obtain the primitive flow tale from the given design specifications. Reduce the flow table by merging rows in the primitive floe table. Assign binary state variables to each row of the reduced flow table to obtain the transition table. Assign output values to the dashes associated with the unstable states to obtain the output maps. Simplify the Boolean functions of the excitation and output variables and draw the logic diagram. The logic diagram can be drawn using S R latches.
Design Example1
Design a gated latch circuit with two inputs, G (gate) and D (data), and one output, Q. Binary information present at the D input is transformed to the Q output when G is equal to 1. The Q output will follow the D input as long as G=1. When G goes to 0, the information that was present at the D input at the time the transition occurred is retained at the Q output. The gated latch is a memory element that accept the value of D when G=1 and retains this values after G goes to 0. Once G=0, a change in D does not change the value of the output Q.
Example1:Primitive Flow Table
Example1:Reduction of the Primitive Flow Table
Example1:Transition Table and Output Map
Example1: Circuit with SR NAND Latch
Assigning Outputs to Unstable States
Assigning Outputs to Unstable States

Assign a 0 to an output variable associated with an unstable state that is a transient state between two stable states that have a 0 in the corresponding output variable. Assign a 1 to an output variable associated with an unstable state that is a transient state between two stable states that have a 0 in the corresponding output variable. Assign a don't-care to an output variable associated with an unstable state that is a transient state between two stable states that have different values (0 and 1 or 1 and 0) in the corresponding output variable.
Design Example2
Design a fundamental-mode asynchronous sequential network meeting the following requirement.
There are two inputs x1 and x2 and a single output z. The inputs x1 and x2 never change simultaneously. The output is always to be 0 when x1=0, independent of the value of x2. The output is to become 1 if x2 changes while x1=1 and is to remain 1 until x1 becomes 0 again.
Design Example3
Design a fundamental-mode asynchronous sequential network meeting the following requirements:
There are two inputs x1 and x2 and a single output z. The inputs x1 and x2 never change or are 1 simultaneously. An output of z=1 is to occur only during the input state x1x2=01 is preceded by the input sequence x1x2=01,00,10,00,10,00.
The End
Lecture-41
A.Amalin Prince
23-11-07
Hazards
Hazards are unwanted switching transients that may appear at the output of a circuit because different path exhibit different propagation delays. Hazards in Combinational circuit may cause a temporary false-output value. Hazards in asynchronous circuits may result in a transition to a wrong stable state. Hazards
Static Hazards
Static 0 Hazard Static 1 Hazard
Dynamic Hazards
Hazards In Combinational Circuits
Illustration of Static 1-Hazards
Illustration of Static 0-Hazards
Hazard-Free Circuit
Hazard-Free Circuit
Illustration of Dynamic Hazard
Consider inputs x1x2x3=000 and 100 Assume Delay of G1<G2<G4 and G3=G5=0
Hazards in Sequential Circuits
Essential Hazards
An essential Hazard is caused by unequal delays along two or more paths that originate from the same input.
The End
Von Neumann architecture Single bank of memory which processor accesses through a single set of address and data lines.
Processor core
Address bus Data bus
Memory
Harvard Architecture The Processor is connected to two independent memory banks via two independent set of buses. Program bank and Data bank With modifications in Harvard Program bank will hold program instructions and data and other bank with data only.
Lots of devices on one bus leads to:

Propagation delays
Long data paths mean that co-ordination of bus use can adversely affect performance
Most systems use multiple buses to overcome these problems
Complex Instruction Set Computer

Intel x86 DEC VAX, PDP11 Motorola 68k IBM 360, 370
Complex instructions bring the hardware closer to high-level languages
A CISC PROCESSOR
Larger instructions with variable formats (16-64 bits/ instruction) Larger Addressing Modes (12- 24) Few Registers Most Microcoded with control Memory
Instruction Set Architecture

Memory-to-register Load indexed
x = y[i];
x86 MOV AX,[BX] MOV AX,[BP+SI]
Load indexed, post-increment

LODSW y = y[i++]; 68k: Load indexed, pre-decrement MOV.L D0,-(A2) y = y[--i];
Memory-to-memory
a=b
MOVSB REP MOVSB
Block copy
memcpy(d,s,n);
Instruction count Usually more than 256 Maximum number of 8-bit opcodes Powerful instructions Many microcode steps Added some complexity to interrupt handling, page faulting, etc Variable length, multiple formats 1 to 10 bytes
Reduced Instruction Set Computer LOAD- STORE Architecture Fewer Addressing Modes Fixed Length Instructions More Registers Designed for Pipeline Efficiency Hardwired Control Unit
Two steps:
Fetch Execute
Steps in Execution of an Instruction

CPU fetches instruction from Main Memory CPU Decodes the Instruction Op-code Depending on Op-code - Fetches another operand - Execute instruction via register to register transfer - Write the results in M - Write the results in I/O Repeats the steps
Instruction and Address Formats: Opcode + Operands First Generation Computers

Opcode A0 A1 A2 A3
- Because
of sequential nature A3 not required
Two address Format OPCODE A0 A1
ADD AX, BX
(8086)
One Address Format OPCODE ADD B A0 (8085)
Zero address Machines:

(Stack Machines)
ADD Ex: X = A*B + C*D
3-adr m/c ADD SUB MUL DIV HLT
2-adr m/c MOVE ADD SUB MUL DIV HLT
1-adr m/c LOAD STORE ADD SUB MUL DIV HLT
0-adr m/c PUSH POP ADD SUB MUL DIV HLT
General Instructions available
3-ADR M/C MUL T,A,B MUL X,C,D ADD X,X,T HLT 2 ADR M/C MOVE T,A MUL T,B MOVE X,C MUL X,D ADD X,T HLT
1 ADR M/C LOAD A MUL B STORE T LOAD C MUL D ADD T STORE X HLT
0 ADR M/C PUSH A PUSH B MUL PUSH C PUSH D MUL ADD POP X HLT
A CISC PROCESSOR
Larger instructions with variable formats (16-64 bits/ instruction) Larger Addressing Modes (12- 24) Few Registers Most Microcoded with control Memory
Designing a Processor
Given an instruction set how does one go about designing the processor, how to arrive at different architectural blocks like execution unit controller etc.,
Microprocessor (Computer s central Processing Unit) Ex: Pentium, 68000 etc. has two parts Control part says what to do Data part does it
ALU REG SET
CLU
CENTRAL PROCESSING UNIT
Clock Generator
Bus Controller
Control Part
Processor Controller
Execution Unit
Data Part
A SINGLE CHIP MICROPROCESSOR
EXECUTION UNIT
Programmers Register set Additional registers ( IR, PC , Temp Reg) ALU and any special function units Internal Data paths All connected through a interconnect network Usually comprised of one/more buses
Register Set:
Program Counter PC PC + 1, PC
Address part of the branch Instruction
Instruction Register IR M [PC]
General Purpose Registers
ARITHMETIC LOGIC UNIT

A B
CONTROL LINES F1 F2
MUX SEL LINES R
CONTROL PART A Bus Controller to run the external bus cycles to fetch instructions (or) operands from memory and to write results back to memory
A Controller that goes through control steps
A clock generator to generate timing signals to decide the time durations of individual control steps
CONTROL LOGIC UNIT

-Directs all hardware activity inside -Controls Fetch, Decode, Execute Cycle
Macro/Micro Instructions
Instruction set Summary

Instruction Formats Operations Addressing Modes Programmers Registers
A TYPICAL INSTRUCTION - ADD R1, D2(B2) (R1, B2 - Registers ), D2- displacement (R1) + (Memory) (R1) ; (B2) + D2 Memory
5A
0
R1
B2
15 16
D2
31
Steps for executing instruction

- Fetch the first instruction half-word - Find ADD control sequence - Fetch the remaining instruction half-word - Calculate the operand address - Fetch the operand - Add - Store the result
CPU Operations
Fetch a word from Memory Store a word into memory Reg Transfers Performing an ALU function
Instruction Decoder IR PC Address Bus Data Bus MAR MDR R0
Rn-1 Clear Y Control Lines A Y ALU Z B
Example Microinstructions:
Open/Close a gate from Reg to a bus Transfer data along a bus Send timing signals Test bits within a register
Fetching a word from memory:
i. MAR
(R1)
ii. Read Signal iii. Wait for Memory-function-complete (MFC) signal iv. R2 (MDR)
Storing a word into Memory:
i. MAR ii. MDR
(R1) (R2)
iii. Memory write signal iv. Wait for MFC
Register Transfers: R2 R1
To enable data transfer between various Blocks connected to common bus provide Input output gating.
Rin
Rout
Yin
ALU
Zin Z Zout
Performing an Arithmetic or Logic Operation:

i. R1out, Yin ii. R2out, Add, Zin iii. Zout, R3in
Ex: Add contents of a memory location to register R1

Step T1 RTL MAR PC; PC PC+1 Control Sequence PCout, MARin, Clear Y, Set Carryin of ALU, ADD, Zin, READ
T2 T3
Wait IR MDR
Zout, PCin, Wait for MFC MDRout, IRin
- Instruction Fetch
Ex: Add contents of a memory location to register R1

Step T4 MAR IR RTL Control Sequence Addr-field of IRout, MARin, READ R1out, Yin, Wait for MFC MDRout, ADD, Zin Zout, R1in, END
T5 T6 T7
Y Z R1
R1 Y + M[MAR] Z
Ex: Branch by an offset x

Step T1 RTL MAR PC; PC PC+1 Control Sequence PCout, MARin, Clear Y, Set Carryin of ALU, ADD, Zin, READ
T2 T3
Wait IR MDR
Zout, PCin, Wait for MFC MDRout, IRin
Ex: Branch by an offset x

Step RTL Control Sequence
T4
PC
PCout, Yin
T5
Y + [x of IR]
ADD, Zin Addr-field of IRout
T6
PC
Zout, PCin, END
Ex: CALL absolute address -Address fetched along with instruction
Ex: CALL absolute address
Step T1
RTL MAR PC; PC
Control Sequence PC+1 PCout, MARin, Clear Y, Set Carryin of ALU, ADD, Zin, READ Zout, PCin, Wait for MFC
T2 T3 T4 T5 T6 T7
Wait IR Z SP MDR SP-1 Z, MAR Z
MDRout, IRin Set Y, SPout, ADD, Zin Zout, ,MARin,,SPin MDRint, PCout, WRITE PCin, Addr-field of IRout, Wait for MFC, END
MDR PC PC IR
Design of CLU - Hard wired design - Microprogrammed design
HARDWIRED CONTROL UNIT
Hard-wired Control Unit

-The
opcode field of IR. This field is decoded to provide the encoder information about instruction being decoded from status and condition
-Signals
-Control
step information ( Step generator for T1, T2,
.)
-External
signals such as start, MFC, interrupts etc.
Control signal generator generates Individual control signals.
Ex: Zin = T1 + T6.ADD + T5. BR + .
- IMPLEMENTED
AS A COMBINATIONAL CIRCUIT.
Combinational design could be using PLDs. Hard wired logic difficult to implement changes Provides faster execution.
-Another approach Microprogrammed control unit
Microprogrammed Unit
-Sequence of microinstructions corresponding to each instruction is stored in ROM called Control Memory -Called Microprogram -Provides flexibility of implementation -Less hardware
Micro instruction word is the word whose bits represent control signals Ex: Y Z R1 R1 ; R1out, Yin, Wait for MFC
Y + MDR ; MDRout, ADD, Zin Z ; Zout, R1in, END
Step :R1in R1out Yin Zin Zout MDRout ADD WMFC END
Microprogramming Types Horizontal Microprogramming Vertical Microprogramming
Horizontal Approach -1 bit per control signal -Many control signals generated concurrently -Permitting very fast operation -Requires large control memory area
Vertical Approach - Most Micro instructions are mutually exclusive and never invoked simultaneously - Possible to divide into groups and use few bits to represent each group - A Decoder then used to select a particular Microoperation to be invoked
Micro instruction
.........
Decoder
Control Lines
-Control Memory size reduced -Additional hardware required -Slows down the process
Nanomemory -Third memory unit beside main memory and control memory -Appropriate when many microinstructions occur several time
Example:
Microprogram with k t-bit micro instructions To store this k x t size control memory required
Assume only n distinct microinstructions are used where n k
Store these instructions in n-word, t-bit nanomemory Original program replaced by address of nanomemory word Reduction in memory size For ex: 16, 384 x 128 is the original size But has only 256 different microinstructions Nanomemory size is 256 x 128 Control ROM size is 16,384 x 8
Size saved = (16,384 x 128)-(16,384x8) = 1,933,312
(256 x 128)
Speed reduced because two levels of memory
CPU Memory Architectures & Organization

Sunil Nanda
Agenda
Memory Architecture Concepts
Caches Virtual Memory TLBs & Page Tables
MP Memory Organization
MP Classification Cache Coherence Memory Consistency
Memory Architecture Concepts
Caches Principle of locality

Temporal locality
If an item is referenced, it will tend to be referenced again soon
Spatial locality
If an item is referenced, nearby items will tend to be referenced soon
Cache Performance
Multiple level caches are the norm
Upper caches are smaller and faster than lower caches Inclusion principle is typically followed
Miss rate is misleading

Avg mem access time = Hit time + (Miss rate * Miss penalty) Even better is the actual program execution time
Cache Block size

Minimum unit of data that can either be present or not present in a cache
Typical range 8 128 bytes Typically fixed for a design though variable size designs have been done
Miss penalty
Miss rate
Block size
Block size
Cache Associativity
0 1 2 3 4 5 6 7 Block number 0 1 2 3 4 5 6 7 Block number 01234567
Set 0 Set 1 Set 2 Set 3
Fully associative Block 12 can go anywhere
Direct Mapped Block 12 can go only into block 4 12 mod 8
2-way set associative Block 12 can go anywhere into set 0 12 mod 4
Block Frame Address Tag

Tag used to check all blocks in a set
Index
Index used to select the set
Block Offset
Block offset is the address of the desired data within the block
Portions of an address
Example Cache Design

8KB cache, 2-way associative, 8 byte blocks
Tag <20> Index <9> Block Offset <3>
V <1>
Tag <20>
Data <64>
...
=?
To CPU 2:1 MUX

=?
...
Major Cache Design Issues

Split/Unified Size & Number of levels Associativity Block size/sub-blocks Writeback v/s writethru Write-allocate Virtual or Physical tags Coherence Protocol Write buffers Victim caches
Virtual Memory Motivation

Allow multiple processes to keep independent use of entire virtual address space Allow multiple processes to share same physical memory Allow processes which need more memory than available physical memory Prevent one process from accessing code or data of another process (unless explicitly allowed)
Virtual Memory basics

Main memory acts as a cache for disk data Each process on each processor issues only virtual addresses Each process has a unique context number or process id The kernel sets up tables to map a [context, virtual-address] pair to a physical address. This mapping may not be unique for special cases. There is usually some hardware assist to do a fast lookup for the VA->PA mapping (e.g. TLB) IO devices usually work with physical addresses
Segmentation v/s Paging

Paging
Words per address Programmer visible Replacing a block One Invisible to application programmer Trivial all blocks are same size Internal fragmentation unused portion of a page Yes page size adjusted to balance access time and transfer time
Segmentation
Two Segment & offset May be visible to aplication programmer Hard must find contiguos, variable size unused portion of main memory External fragmentation unused portions of main memory Not always small segments may transfer only a few bytes
Memory use efficiency
Efficient disk traffic
Virtual v/s Physical address

Physical address is the address in main memory
Size depends on size of main memory e.g. 256MB needs 28-bits of physical address
Virtual address is the address issued by the processor.

Independent of the size of main memory typically 32 bits
Virtual address needs to be translated to physical address for every main memory access
Process called address translation
Page size is common between virtual and physical addresses

Typically ranges from 4KB to 16KB Some systems allow for a finite number of page sizes
Example VA/PA formats

1GB Main memory, 4K page size, 32-bit VA
Virtual Page Number <20> Context ID Page Offset <12> VA 32 bits
Address Translation
Physical Page Number <18>
Page Offset <12>
PA 30 bits
Page Tables
Mapping for VA->PA organized in Page Tables
A collection of Page Table Entries (PTEs) Mapping of PA->VA organized in Inverted Page Tables
PTE holds info for one page at a time

Primarily holds translation from one vritual-page-number to a physical-page-number
Typically holds additional info

Whether page is in memory, disk or unallocated Protection information (executable, read-only etc.) Whether page has been referenced or modified Kernel v/s User Page
Hierarchical Page Tables

Motivation
Page tables can become pretty large They may need to be paged themselves Some architectures support multiple page sizes
Introduce a Page Table Pointer (PTP)

Points to the base address of the next level of page table
ContextD
<16>
VA
<10>
<10>
Page offset <12>
PTP
PTP
PTE
Base Address
Translation Lookaside Buffers (TLB)

TLB is nothing but a cache for PTEs
Could be direct mapped, set associative or fully associative Takes VA and context-id as input and returns PA and protection information
A TLB-miss causes a Page Table search to find the approriate PTE

Called a Table Walk lot of care taken in table organization to facilitate a walk Much more expensive than a cache miss Could be done in SW or HW Replacement strategies similar to caches
If new PTE indicates that the page is on disk a Page-Fault occurs

OS must retrieve the page from disk OS must allocate a physical page for it OS must fix the PTE bits to indicate that it is now in memory
If new PTE indicates that the page is unallocated (invalid)

OS must allocate a physical page for it OS must fix the PTE bits to indicate that it is now allocated
TLB coherence issues exist for MPs jus like cache coherence
Primary issue occurs when demapping a page Stale entries may exist in other TLBs need to be flushed
MP Memory Organization
Flynn Processor Classification

SISD Single Instruction Single Data
Classic uniprocessor Von-neumann architecture
SIMD Single Instruction Multiple Data

Array and Vector Processors Same Operation performed at one time on multiple data
MISD Multiple Instruction Single Data

Systolic Processors
MIMD Multiple Instruction Multiple Data

Conventional MP architectures Each processor executes different program with its own data
SISD Processors
IS IS DS
Control Unit
Processing Unit
Memory Unit
IS Instruction Stream DS Data Stream
SIMD Processors
Processing Unit IS IS DS Memory Unit DS
Control Unit
Processing Unit
DS
Memory Unit
DS
Processing Unit
DS
Memory Unit
DS
MISD Processors
Memory Unit IS IS IS DS
Control Unit IS Processing Unit
Control Unit IS
Control Unit IS DS
DS Processing Unit
DS Processing Unit
MIMD Processors
IS IS DS Control Unit Processing Unit IS IS DS
Control Unit
Processing Unit IS
Memory Unit
Control Unit
IS
Processing Unit
DS
MIMD Parallel Processors

Parallel Processors
SIMD Shared Memory MIMD Message Passing MISD
Classic MP MIMD Architectures

Shared Memory
More natural transition from uniprocessors Easier on data partitioning & load balancing UMA, NUMA, COMA (Cache-only) Tightly coupled
Message Passing
Scalable beyond shared-memory Loosely coupled message passing for IPC
Symmetric v/s Asymmetric MPs

Asymmetric
Master/slave configuration Master monitors status & assigns work to slaves Slaves are a pool of resources to the master Master can be a bottleneck
Symmetric
All processors are autonomous treated equal One copy of the kernel executed concurrently across all processors Synchronized access to shared data structures
Multithreaded kernel
SMP Classification
Parallel Processors
SIMD MIMD Shared Memory UMA NUMA MISD Message Passing COMA
UMA Uniform Memory Architecture

P1 P2 Pn
Interconnect Network (bus, xbar etc.)
SM1
SM2
SMn
IO
Single address space visible to all CPUs Memory access latency uniform for all processors Interconnect network could be a bus or a crossbar or switch Typically 8-16 nodes
NUMA Non-Uniform Memory Architecture

P1 LM1 Single address space visible to all CPUs Interconnect Network (bus, xbar etc.) Remote memory access slower than local memory Compilers and OS need to be careful about data placement Interconnect network could be a bus or a crossbar or switch Theoretically scales better than UMA
P2
LM2
Pn
LMn
COMA Cache-only Memory Architecture

P1 C1 D1 P2 C2 D2 Pn Cn Dn
Interconnect Network (bus, xbar etc.) Single address space visible to all CPUs If collective cache size is big enough dispense with main memory Memory access latency is not uniform
Cache coherency Problem

Time Event 0 1 2 3 Proc1 reads X Proc2 reads X Proc1 stores 0 to X 1 1 0 1 1 Proc1 cache Proc2 Mem cache location X 1 1 1 0
Coherence v/s Consistency

Coherence
What values are returned by a read operation
Consistency
When will a written value be returned by a read
A memory system is coherent if a read of an item returns the most recently written value of that item. The system behaves as if there were no caches.
UMA MP Classification
Parallel Processors
SIMD MIMD Shared Memory UMA Snoopy Directory based NUMA MISD Message Passing COMA
Coherence Protocols
Directory Based
Sharing information about a cache block is kept in just one location the directory in main memory Requests sent only to relevant processors
Snooping Based
No centralized state information. Individual caches keep sharing information on their cache blocks. Bandwidth hungry doesnt scale well
Snooping Protocol Types

Parallel Processors
SIMD MIMD Shared Memory UMA Snoopy Write-Invalidate NUMA Directory based Write-Update MISD Message Passing COMA
Snooping Protocols
Write Invalidate
On a write, all cached copies of the cache block are invalidated except that of the writing processor. Writing Processor gains exclusive access to the cache block.
Write Update (Write Broadcast)

All cached copies of the block are updated when any processor writes to a location.
Coherence Invalidation Protocol

Processor activity Bus activity Proc1 cache Proc2 cache Mem location X 1 Proc1 reads X Cache miss for cache1 Proc2 reads X Cache miss for cache2 Proc1 writes 0 Invalidation cycle for X to X Proc2 reads X Cache miss for cache2 1 1 0 0 0 1 1 1 0 0
Invalidation Protocol cache miss

On a P1 cache miss, the required block may be in another cache (P2) rather than memory P2 cancels P1s read. P2 supplies the cache block to P1 The cache block is also written to memory at the same time.
Coherence Update Protocol

Processor activity Bus activity Proc1 cache Proc2 cache Mem location X 1 Proc1 reads X Cache miss for cache1 Proc2 reads X Cache miss for cache2 Proc1 writes 0 Write broadcast for X to X Proc2 reads X Cache hit for cache2 1 1 0 0 1 0 0 1 1 0 0
Coherence Invalidate v/s Update

Multiple writes to the same word without an intermediate read
Invalidate : Only one invalidate cycle Update : Multiple update cycles
Multiword cache blocks

Invalidate : Only first write to any word within the cache block generates invalidate cycle Update : All writes to any word within cache block generate update cycles
Common Snoop Protocols

Parallel Processors
SIMD MIMD Shared Memory UMA Snoopy Write-Invalidate MSI MESI MEI MISD Message Passing NUMA Directory based Write-Update MOESI COMA
Mainstream Processor Examples PowerPC755 : MEI protocol

Pentium class: MESI protocol UltraSPARC: MOESI protocol AMD64 class: MOESI protocol
MESI Coherence Protocol

MESI States
M (Modified)
Description
Block is valid in this cache and only this cache. The block is modified w.r.t. the main memory it is dirty and has not been written back. This state may also be referred to as DirtyExclusive. Block is valid in this cache only. It is also consistent w.r.t the main memory it is not dirty. This state may also be referred to as Clean-Exclusive. Block is valid in this cache and at least one other cache. It is consistent w.r.t. the main memory. Shared blocks are never dirty. Block is invalid in this cache. It is not resident in this cache.
E (Exclusive) S (Shared) I (Invalid)
MESI States contd.

Cache A M I Cache B E Cache A I Cache B
Valid data Invld data Valid data Invld data
Invld data
Valid data
Memory Cache A S S Cache B I

Valid data
Memory Cache A Cache B
Valid data
Invld data
Dont care
Invld data
Dont care
Memory
Memory
MESI State changes

Cache blocks change state on memory access events Event may be
Due to local processor activity Due to bus activity snooping
Each cache block changes its state only if its address matches the event address
MESI State transitions

Modified/Exclusive/Shared/Invalid Upon loading, a line is marked E, subsequent read OK, write marks M If another's load is seen, mark S Write to an S, send I to all, mark M If another reads an M line, write it back, mark it S Read/write to an I misses
MESI State Diagram
RH = Read Hit RMS = Read Miss, Shared RME = Read Miss, Exclusive WH = Write Hit WM = Write Miss SHR = Snoop Hit, Read Operation SHW = Snoop Hit, Write Operation
MESI Local Read Hit

Line must be in one of MES This must be correct local value (if M it must have been modified locally) Simply return value No state change
MESI Local Read Miss (1)

No other copy in caches
Processor makes bus request to memory Value read to local cache, marked E
One cache has E copy

Processor makes bus request to memory Snooping cache puts copy value on the bus Memory access is abandoned Local processor caches value Both lines set to S

Several caches have S copy
Processor makes bus request to memory One cache puts copy value on the bus (arbitrated) Memory access is abandoned Local processor caches value Local copy set to S Other copies remain S

One cache has M copy
Processor makes bus request to memory Snooping cache puts copy value on the bus Memory access is abandoned Local processor caches value Local copy tagged S Source (M) value copied back to memory Source value M -> S
MESI Local Write Hit (1)

Line must be one of MES M
line is exclusive and already dirty Update local cache value no state change
E
Update local cache value State E -> M
MESI Local Write Hit (2)

S
Processor broadcasts an invalidate on bus Snooping processors with S copy change S->I Local cache value is updated Local state change S->M
MESI Local Write Miss (1)

Detailed action depends on copies in other processors No other copies
Value read from memory to local cache Value updated Local copy state set to M

Other copies, either one in state E or more in state S
Value read from memory to local cache - bus transaction marked RWITM (read with intent to modify) Snooping processors see this and set their copy state to I Local copy updated & state set to M

Another copy in state M Processor issues bus transaction marked RWITM Snooping processor sees this
Blocks RWITM request Takes control of bus Writes back its copy to memory Sets its copy state to I

Another copy in state M (continued) Original local processor re-issues RWITM request Is now simple no-copy case
Value read from memory to local cache Local copy value updated Local copy state set to M
MOESI Protocol
MESI does not distinguish between SharedClean and Shared-Modified MOESI adds an Owned (O) state to signify Shared-Modified while the S state gets redefined as Shared-Clean Caches with O state update each others blocks but do not write back to main memory
Memory consistency problem

P1: A = 0; A = 1; L1: if (B == 0) ... P2: B = 0; B = 1; L2: if (A == 0) ...
Processes running on different processors A and B cached in both processors with initial value of 0 If memory always consistent impossible for both L1 and L2 to be TRUE What if write invalidates have some delay? Possible that both P1 and P2 have not seen invalidations for A & B How consistent a picture of memory must both processors see?
Another Memory Consistency Example

P1: A = data1; B = data2; flag = 1 ... P2: while (flag==0) ; varA = A; varB = B;
Processes running on different processors Flag is cached in both processors with initial value of 0 Expectation is that P2 will see data1 and data2 for A and B respectively after it gets through the wait loop on flag
Memory Consistency Models

Strict Consistency
Read always see the value of last write
Sequential Consistency
Interleaving of different processors in strict program order
Processor Consistency
Each Processors writes in program order but different processors writes may not be
Weak Consistency
Use of explict synchronization instructions to enforce sequential consistency
Release Consistency Weak consistency with two sync operators Release and Acquire
Sequential consistency
Result of any execution is the same as if
The accesses of each processor were kept in order and The accesses among different processors were arbitrarily interleaved
Implies that a processor delay any memory access till all invalidations required by previous writes are completed Presents a simple programming paradigm Reduces potential performance
Speculative execution w/ repair is a problem Write buffers are potential problems Reordered memory operations is another issue
Weak (Relaxed) consistency

Observation : Sequential consistency not always needed in MPs. A special barrier or fence instruction explicitly serializes memory operations when it matters
Stop all instructions from executing till all previous ones have completed Empty write buffers into memory
Potentially higher performance but the burden of synchronization shifted to the programmer Used in IA-32 architecture
Orientation
A.Amalin Prince
1
03-08-07
Objective : Orientation
AAP
Instructor-in-charge:
Mr. A.AMALIN PRINCE
AAP
Team of Instructors:
Prof. Jagmohan Singh Dr.Iven Jose Mr.M.T.Abhilash Mr.D.B.Singh Mr.Abhihjeet Khadke Ms.Sushmita Wils.K Mr.Nitin Sharma Mrs.Chaya Devi
Consultation Hours
Instructor A.Amalin Prince M.T.Abhilash Sushmita Wils.K Iven Jose Nitin Sharma Jagmohan Singh D.B.Singh Abhihjeet Khadke Chaya Devi
AAP
Day Thursday Tuesday Thursday Tuesday Monday Wednesday Saturday Saturday Tuesday
Time 11.00 to 12.00 11.00 to 12.00 04.00 to 05.00 10.00 to11.00 10.00 to 11.00 12.00 to 01.00 10.00 to 11.00 10.00 to 11.00 10.00 to 11.00
Course Description:
This course covers the topics on logic circuits and minimization, Combinational and sequential logic circuits, Programmable Logic devices, State table and state diagrams, Digital ICs, Arithmetic operations and algorithms, Introduction to Computer organization, Algorithmic State Machines and Verilog HDL.
AAP
Scope and Objective:

The objective of the course is to impart knowledge of the basic tools for the design of digital circuits and to provide methods and procedures suitable for a variety of digital design applications. The course also introduces fundamental concepts of computer organization. The course also provides laboratory practice using MSI devices, Xilinx ISE software tools and FPGA
Text Books
AAP
T1:
M.Moris Mano, Digital Design, PHI, 3rd Edition, 2002
AAP
T2:
G Raghurama, TSB Sudharshan , Introduction to Computer Organization, EDD notes 1997
AAP
T3: Laboratory References

Digital Electronics and Computer Organization course team , Laboratory Manual, EDD notes BITSPilani Goa Campus 2007.
Data Books available in the laboratory

AAP
R1:
Palnitkar.S , Verilog HDL Pearson Education Pvt. Ltd., 2004
AAP
R2:
Donald D. Givone , Digital Principles and Design TMH, 2003
AAP
R3:
Robert K.Dueck , Digital Design with CPLD Applications and VHDL , Thomson, 2002.
AAP
Course Plan:
Lect. No. 1 Learning Objectives Introduction to Digital Systems and Characteristics of Digital ICs. Boolean algebra and logic gates, Codes number systems Simplification of Boolean functions Simulation and synthesis basics Combinational Logic, Arithmetic circuits MSI Components Topics to be covered Digital Systems, Digital ICs Reference to Text Book 1.1; 1.9; 2.3, 10.1,2
2.
Boolean functions Canonical forms, number systems and codes K-Maps (4,5 variables), QM Method Hardware Description Language Adders, Subtracters Multipliers Comparators, Decoders, Encoders, MUXs, DEMUXs
1.2-7, 2.4-2.8;
3-5
3.1 to 3.3, 3.5 to 3.8
6 7-9 10-11
3.9 4.1 - 4-6 4.7 to 4.10
AAP
Lect. No. 12
Learning Objectives
Topics to be covered
Reference to Text Book 4.11
Simulation of Combinational Logic Functions. Digital Integrated Circuits
HDL for Combinational Logic
13-15
TTL, MOS Logic families and their characteristics RAM, ROM, PLA, PAL Flip-Flops & Characteristic tables, Latches. Analysis of clocked sequential circuits, state diagram and reduction Shift registers, Synchronous & Asynchronous counters
10.3, 10.5, 10.7 to 10.10 7.1, 7.5 to 7.7 5.1 to 5.3 5.4, 5.6
16-18 19-20 21-22
Memory and PLDs Sequential Logic Clocked Sequential Circuits Registers & Counters
23-24
6.1 to 6.5
AAP
Lect. No. 25 26-27 28-31 32-34 35-38 39-40
Learning Objectives Simulation of Sequential Logic Functions. Analysis of arithmetic units
Topics to be covered HDL for Sequential Logic, HDL for registers and counters Multiplication & Division algorithms
Reference to Text Book 5.5, 6.6 T2: Appendix A 8.1,8.2, 8.4 to 8.7 R2. Chapter 8 9.1 9.7 T2: Ch 6
Modular approach for CPU RTL, HDL description Design Design of Digital Systems Design of Asynchronous Circuits. Memory Organization Algorithmic State Machines Asynchronous Sequential Logic Memory Hierarchy & different types of memories
AAP
Evaluation Scheme:
Component Test I Test II Comprehensive Examination Practicals: Regularity, Lab reports & Assignment Lab test & Viva Duration 60 Min 60 Min 3 Hrs _____ Maximum Marks 50 50 120 40 Date 20-09-07 01-11-07 01-12-07 (AN) Regularly Remarks CB OB CB OB
To be announced
40
To be announced
CB
AAP
Practical (From T3)

Ex. No: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
AAP
Name of the experiment Familiarization Of Bench Equipments Implementation Of Boolean Functions Using Logic Gates Adders And Subtractors Decoders, Multiplexers And Encoders Comparators & Arithmetic Logic Unit Implementation Of Combinational Logic In FPGA Latches & Flip-flops Operation Of 4 Bit Counter Implementation Of Sequential Logic In FPGA Shift Registers Sequential Circuits Implementation Of Mealy And Moore Machine In FPGA
Cycle I
II
III
IV
Assignment: To be announced in the class Notices: will be displayed on FTP & EEE/INSTR notice board Only Make-up Policy: -Prior Permission of the Instructor-in-Charge is required to take a make-up for a test/lab. - Make-up applications must be given to the Instructor-in-charge personally. - A make-up test/lab shall be granted only in genuine cases where - in the Instructors judgment the student would be physically unable to appear for the test.
AAP
How to get good Score???
AAP
The End
AAP

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Lecture-1

Digital Electronics and Computer Organization (DECO)

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Digital and Analog Quantities

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

The Digital Advantage

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

An Analog Electronic System

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

A system using Digital and Analog Methods

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Advantages of Digital Techniques

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Applications of Digital Circuits

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Characteristics of Digital ICs

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Voltage ranges of logic inputs for positive logic.

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Calculated from the ratio:

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Propagation delay times

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Smaller of these will be the noise margin

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Basic Arithmetic Operations

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Signed numbers and Complements

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Weighted decimal codes

BCD Arithmetic Why Weighted?

Other BCD Codes

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Non-weighted decimal codes

2-out-of-5-code 11000 00011 00101 00110

01001 01010 01100 10001 10010 10100

* Except for 0, it is a weighted code having the weights 74210

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Binary 0000 0001 0010 0011 0100 0101 0110 0111

Binary 1000 1001 1010 1011 1100 1101 1110 1111

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

Error detecting codes

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus

CS GC391/EEE GC391/INSTR GC391 BITS-Pilani Goa Campus