Scribd Logo
Hochladen

Willkommen bei Scribd!

  • 74HC595 PDF, 74HC595

    Hochgeladen von

    park991018
    121 Ansichten9 Seiten
    daf

    Originaltitel

    74HC595 pdf, 74HC595

    Copyright

    © © All Rights Reserved

    Verfügbare Formate

    PDF oder online auf Scribd lesen

    Stufen Sie dieses Dokument als nützlich ein?

    Sind diese Inhalte unangemessen?

    Dieses Dokument melden
    daf

    Copyright:

    © All Rights Reserved
    Als PDF herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    121 Ansichten9 Seiten

    74HC595 PDF, 74HC595

    Hochgeladen von

    park991018
    daf

    Copyright:

    © All Rights Reserved
    Als PDF herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 9
    High Speed CMOS Logic — 74HC595 ' ; 5 Rev 1.2 8-bit shift registers with 3-state output latches in bare die form aot Description Features: The 74HC5QS is an &-bit serial-in to parallel-out shit * Output Drive Capability: 15 LSTTL Loads register which drives an 8-bit D-type latch with 3-state . outputs. Both register and latch have independent positive triggered clock inputs. All registers capture data on rising edge and change output on the falling . ‘edge. If both clocks are connected together the input shift register is always one clock cycle ahead of the ‘output register. The shift register also features asynchronous reset. Device inputs are compatible with, standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. Low Input Current: 1HA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V (CMOS High Noise Immunity Function compatible with 74LS595. Ordering Information Die Dimensions in ym (mils) ‘The following part suffixes apply: 1030 (41) + No suffix - MIL-STD-883 /2010B Visual Inspection g For High Reliability versions ofthis product please see g S4HC5O5 . Supply Formats: Mechanical Specification * Default — Die in Waffle Pack (400 per tray capacity) Die Size (Unsawn) tosox770 | am + Sawn Wafer on Tape ~ On request a x um + Unsawn Wafer ~ On request Minimum Bond Pad Size 9.76 x2.76 | mils 280 (210) “um * Div Thickness <> 280pm(11 Mis) On request + Assembled into Ceramic Package ~ On request ‘Top Metal Composition Die Thickness Back Metal Composition NIA Bare $i Page 1of 9 www sliconsupplies.com © High Speed CMOS Logic — 74HC595 Rev 1.2 22112121 Pad Layout and Functions COORDINATES (um a ama PAD FUNCTION (vm) 15] 10) x Me z 1 Qs ~o1e | -102 é 3 2 Qe “4018 | 246 3 ‘6 3 Qs 278 & oa e : 5 4 Qe 8 5 Oe =) pee = 6 Qs 32] EE 7 Qu 8 nD | 9 a | 1030)m (40.55 mils) 10 RCIR +1 SRCLK 42) RCLK 13 OE S44 14 SER 233.2 Logic Diagram 15 aq | 4018 237.6 16 Vos | 4018 | 46 SERIAL) 16 CONNECT CHIP BACK TO Vec OR FLOAT vata { ser 1! on INPUT top 2 O Bg, | PARALLEL SHIFT 4 DATA RORISTER atch Far | ourpurs Lo, £ as Zo SEK { src OY yo 5 7 SERIAL reser { SROIR. Oy: } DATA ure nou ourpuT RCLK cca Voc= PAD 16 oureur { @¢48__________] Giip=paos Page 2of 9 www sliconsupplies.com © High Speed CMOS Logic — 74HC595 Rev 1.2 Function Table" zein2iea [ INPUTS (OUTPUTS FUNCTION SRCLK RCLK | OE SRCLR | SER | QH Qn x x u Lt [ X [ L | NC | LoWievel on SRCUR only affects the shit reaisters x 7 v tT [> [LL [empty sifsregister oaded into storage register x x DL x ob Pg) Siereistercler Parse! oupus in righ- impedance OFF- state Lagi Figh evel shifted into shit register stage 0. Content of t x L H H | Qs | NC | allshif register stages sifted through, eg. previous state of stage 6 (internal Qs) appears on serial utput{ Qs) “Contents of shift register stages (intemal On) transfers to the storage register and parallel ouiput stages | Shift register contents shified trough. Previous shift register 1 t t B X | Qs | Qn’ content transfers to storage register & paralle! output stages. 1. HEHIGH voltage lave, L=LOW voliage lave: 7 =LOVA4e-HIGH transtton, Z=high-impedance OFF-stale; NC=no change: X=dont care x 1 L H xX | NC | an Absolute Maximum Ratings® [ PARAMETER ‘SYMBOL VALUE | UNIT | Dé Supply Voltage (Referenced to GND) Veo O5t0+70 | Vv | DC Input Voltage (Referenced to GND) Viv “0.5 toVex +05 | Vv | DC Output Voltage Vout 05 toVor +05 | Vv [DC Input Current, per pad I 220 [ mA DC Output Current, per pad Tour 235 I mA | DC Voc or GND Current hee 375, [ mA | Power Dissipation in Still Air Po 750 I mW | Storage Temperature Range Tare 8510150 | °c 2. Operation above the absolute maximum reting may cause device faire. Operation atthe absclute maximum ratings, for extended periods, may ‘educe dovico reliably. 3. Measurodin plastic DIP packaoo, resus in dio form aro dependent on do attach and assembly method. Recommended Operating Conditions® (vottaces referenced to GND) [ PARAMETER _ SYMBOL | MIN MAX | UNITS | [DC Suppiy Voitage [ Ve | 2 @ [| Vv [De Input or Output Voltage [VaNor [0 Ves | V | Operating Temperature Range it | 40 +85 | °C Vee = 2.0V [0 1000 | ns Input Rise or Fall Times [ Voc= 4.5V tute 70 500 | ns Voc=6.0V lo 400 [ns 4. Tis davies contains protection creultry to guard against damage due to nigh state voltages ar elecie Neds. However, pracautons must be taken to avaid applications of any voltage higher than maxmum rated votages to this highimpedance circu. For proper operation, Va and Voir should be constrained tothe range GND (Vw oF Voir) Vec. Unused inputs must always be ted to an appropriate logic votage level (e.g. ether GND or Vee), Unused outputs must be lef open Page 3 of 9 www sliconsupplies.com © High Speed CMOS Logic — 74HC595 Rev 1.2 ; eti 22/12/24 DC Electrical Characteristics (voltages Referenced to GND) PARAMETER SYMBOL Yo | CONDTIONS wits Towne (25°C | 85°C FULL RANGE" [20v [15 [15 15, Minimum High-Level soy | Ver=OWVor (94 24 24 Input Voltage Ve veo oy v [48V tour s2oua | 3.15 | 315 3.15 [6ov (420) 42 42 [2o0v [05 [-05 08 Maximum Low-Level v 3,0V Vor 5 Vv or 09 09 O98 v input Votage Faav eee ta 1858 | 135 1.35 | 6.0v C18] 18 18 (BO y, 18 | 18 19 fas WS vee (4a [aa 44 v ov 39 | 89 Minimum High-Level Vw =Vn or Va Cite tee Vou | 30V.) YAM iNR | 248 | 234 - On 45v fet nove | 398 | 384 3.84 v 6.0v 548. | 5.34 [BO ov, ot | On faav YRe Vigne oto v Teov_ (ot [ot Maximum Low-Level Vin = Vin OF Va Gu oa vo | Sov) N= Neive | oe | 033 0.33 45v test nove | 026 | 038 0.33 v 6.0v 026 | 033 0.33 BV wy, 1 | 18 19 Lae [our] = 20nA a a 3 v Minimum High-Level Vin= Vn or Vi Output tage Vow | 30V) fiefszamaA | 248 | 234 288 asv TRU oma | 398 384 3.84 v cov | fREMNNK | 648 | 834 5.34 5. 40C

    Das könnte Ihnen auch gefallen