Date: 17-08-2011

Issue Number: 1

Revision: 0

B.E ELECTRONICS & INSTRUMENTATION ENGINEERING SEMESTER - VII

EI 2405 VLSI LAB MANUAL

Prepared by

Mr. ASHOKRAM.S Asst. Professer

Vel Tech Dr. RR & Dr. SR Technical University

EI 2405 - VLSI LAB MANUAL

SYLLABUS
1. Study of Synthesis tools Half and full adder. Decoder 2 x 4, 3 x 8 Priority encoder. Ripple adder. 4 Bit ripple counter. Code conversion. All the above synthesis in three modeling styles - data flow, structural and behavioral 2. Study of Simulation using tools Half adder. Multiplexer 2 x 1, 4 x 1 Demultiplexer 1 x 2, 1 x 4 All the above synthesis in three modeling styles - data flow, structural and behavioral 3. Study of Simulation using tools Flipflop D, T Priority encoder. Ripple adder. 4 Bit ripple counter. All the above synthesis in three modeling styles - data flow, structural and behavioral 4. Study of development tool for FPGAs for schematic entry and verilog Full adder, half adder. Demultiplexer 1 x 2, 1 x 4. 5. Design and simulation of pipelined serial and parallel adder to add/ subtract 8 number of size, 12 bits each in 2's complement. 6. Place and Root and Back annotation for FPGAs 7. Design and simulation of back annotated verilog files for multiplying two signed, 8 bit numbers in 2's complement. 8. Study of FPGA board and testing on board LEDs and switches using verilog code. 9. Design a Realtime Clock (2 digits, 7 segments LED displays each for HRS., MTS, and SECS.) and demonstrate its working on the FPGA board. To display binary number on the FPGA. 10. Design of traffic light controller using verilog tools . Movement of vehicles in any direction or pedestrian in any direction.

LIST OF EXPERIMENTS 1. Study of Synthesis tools a. Half and full adder. b. Decoder 2 x 4 c. Priority encoder. d. Ripple adder. e. 4 Bit ripple counter. f. Code conversion. 2. Study of Simulation using tools a. Half adder. b. Multiplexer 2 x 1, 4 x 1 c. Demultiplexer 1 x 2, 1 x 4 3. Study of Simulation using tools a. Flipflop D, T b. Priority encoder. c. Ripple adder. d. 4 Bit ripple counter. 4. Study of development tool for FPGAs for schematic entry and verilog a. Full adder, half adder. b. Demultiplexer 1 x 2, 1 x 4. 5. Design and simulation of pipelined serial and parallel adders. 6. Study of Placing,Rooting and Back annotation for FPGAs 7. Design and simulation of back annotated verilog files for multiplying two signed, 8 bit numbers in 2's complement. 8. Study of FPGA board and testing on board LEDs and switches using verilog code. 9. Design a Realtime Clock (2 digits, 7 segments LED displays each for HRS., MTS, and SECS.) a. Demonstrate its working on the FPGA board. b. To display binary number on the FPGA. 10. Design of traffic light controller using verilog tools . a. Movement of vehicles in any direction or pedestrian in any direction.
3

CYCLE-1
1) Study Of Synthesis Tools-Gate realization 2) Half Adder and Full Adder 3) Decoder 4) Priority Encoder 5) Ripple Adder 6) 4-bit Ripple counter 7) Code conversion 8) Study Of Simulation Using Tools for Half adder, Multiplex, De-multiplexer, 9) D&T-Flip flop 10) Study Of Development Tool For FPGA-Full and Half adder, De-multiplexer

CYCLE-2
11.)Design and Simulation of pipelined serial and parallel adder to add/subtract 8 number of size,12 bits each in 2s complement 12.)Study of place and root and back annotation for FPGAs. 13.) Design and Simulation of back annotated verilog files for multiplying two signed 8 bit numbers in 2s complement
14.)Design And Testing Onboard Switches And LEDS In FPGA

15.)Design and Implementation of real time clock 16.) Design of traffic light controller using Verilog tool

ASIC DESIGN FLOW

Steps to work in XILINX

Step 1: Open Xilinx software Step 2: Select File New Project.

Step 3: In the New Project window enter project name and project location.

Step 4: Select the corresponding entries for the property names.

Step 5: Click New Source.

Step 6: Enter the file name and then select Verilog module.

Step 7: Define the input and output port names ,then click Next for all successive windows.

Step 8: The Verilog file will be created under .ise file.

Step 9: Double click the Verilog file and enter the logic details and save the file.

Step 10: Double click Synthesize XST for checking the syntax .

Step 11: Right click the halfadd.v file and select new source ,then click Implementation Constraints File and enter the filename.

10

Step 12:.ucf file will be created

Step13: Open the .ucf file and enter the pin location and save the file

11

Step14: Goto Generate programming file and select Generate PROM,ACE or JTAG file in the processes window.

Step 15: In Slave Serial mode ,right click and select Add Xilinx Device.

12

Step 16: In the Add Device window select the .bit file to add the device.

Step 17: Connect the RS232 cable between computer and kit. Connect the SMPS to kit and switch on the kit. Step 18: Right click the device and select Program to transfer the file to kit. Step 19: After successful transmission of file Programming Succeeded will be displayed. Step 20 : Verify the Results in Kit Using Function/Truth Table.

13

Ex No: 1

STUDY OF SYNTHESIS TOOLS

AIM: To study the Synthesis tools. THEORY: Now that you have created the source files, verified the designs behavior with simulation, and added constraints, you are ready to synthesize and implement the design. IMPLEMENTING THE DESIGN: 1. Select the counter source file in the Sources in Project window. 2. In the Processes for Source window, click the + sign next to Implement Design. The Translate, Map, and Place & Route processes are displayed. Expand those processes as well by clicking on the + sign. You can see that there are many subprocesses and options that can be run during design implementation. 3. Double-click the top level Implement Design process.ISE determines the current state of your design and runs the processes needed to pull your design through implementation. In this case, ISE runs the Translate, Map and PAR processes. Your design is now pulled through to a placed-and-routed state. This feature is called the pull through model. 4. After the processes have finished running, notice the status markers in the Processes for Source window. You should see green checkmarks next to several of the processes, indicating that they ran successfully. If there are any yellow exclamation points, check the warnings in the Console tab or the Warnings tab within the Transcript window. If a red X appears next to a process, you must locate and fix the error before you can continue. VERIFICATION OF SYNTHESIS: Your synthesized design can be viewed as a schematic in the Register Transfer Level (RTL) Viewer. The schematic view shows gates and elements independent of the targeted Xilinx device. 1. In the Processes for Source window, double-click View RTL Schematic found in the Synthesize - XST process group. The top level schematic representation of your synthesized design opens in the workspace.

14

2. Right-click on the symbol and select Push Into the Selected Instance to view the schematic in detail. The Design tab appears in the Sources in Project window, enabling you to view the design hierarchy. In the schematic, you can see the design components you created in the HDL source, and you can push into symbols to view increasing levels of detail. 3. Close the schematic window.

Fig-1:FLOORPLANNER VIEW - DETAILED VIEW

Fig-2: DESIGN SUMMARY VIEW

RESULT: Thus the synthesis tool was studied.

15

Ex No: 1. (a)

AND GATE REALISATION

AIM: Realize the AND gate using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: AND Gate is a circuit which performs, one of the basic logical or switching operation, namely AND operation. It has N inputs (N 2) and one output. Digital signals are applied at the input terminals A, B, CN. The output is obtained at the output terminal marked Y and it is also a digital signal. The AND operation is defined as: the output of an AND gate is 1 if and only if all the inputs are 1. Mathematically, it is written as Y = A AND B AND C AND N = A.B.C N = ABCN where A, B, C N are the input variables and Y is the output variable. The variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1. The binary variables are also referred to as logical variable. The mathematical equation is known as the Boolean equation or the logical equation of the AND gate. The term gate is used because of the similarity between the operation of a digital circuit and a gate. For example, for an AND operation the gate opens (Y = 1) only, when all the inputs are present.

PROCEDURE: 1. The Verilog Module Source for the AND Gate is written. 2. It is implemented in Model Sim and Simulated. 3. Signals are provided and Output Waveforms are viewed.

16

TRUTH TABLE AND GATE

INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT QN+1 0 0 0 1

LOGIC DIAGRAM:

AND GATE BEHAVIOR LEVEL DESIGN IN VERILOG

//*** AND Gate Behavior Level Design module my_andbehavirvlog (y,a,b); output y; input a,b; reg y; always @ (a or b) begin if (a == 1) begin if (b == 1) y = 1'b 1; else y = 1'b 0; end else y = 1 'b 0; end endmodule ***//

17

AND GATE IN GATE LEVEL DESIGN IN VERILOG

//*** AND Gate in Gate Level Design module my_andgatevlog (y,a,b); output y; input a,b; and (y,a,b); endmodule ***//

WAVEFORM:

CONCLUSION: Thus the AND Gate is designed Verilog HDL and the output is verified
18

Ex No: 1. (b)

OR GATE REALISATION

AIM: Realize the OR gate using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: OR Gate is a circuit which performs, one of the basic logical or switching operation, namely the OR operation. It has N inputs (N 2) and one output. Digital signals are applied at the input terminals A, B, CN. The output is obtained at the output terminal marked Y and it is also a digital signal. The OR operation is defined as: the output of an OR gate is 0 if and only if all the inputs are 0. Mathematically, it is written as Y = A OR B OR C OR N = A+B+C +N where A, B, C N are the input variables and Y is the output variable. The variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1. The binary variables are also referred to as logical variable. The mathematical equation is known as the Boolean equation or the logical equation of the OR gate. The term gate is used because of the similarity between the operation of a digital circuit and a gate. For example, for an OR operation the gate closes (Y = 0) only, when all the inputs are absent.

PROCEDURE: 1. The Verilog Module Source for the OR Gate is written. 2. It is implemented in Model Sim and Simulated. 3. Signals are provided and Output Waveforms are viewed.

19

OR GATE: TRUTH
INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT QN+1 0 1 1 1

TABLE:

LOGIC DIAGRAM:

PROGRAM: OR GATE BEHAVIOR LEVEL DESIGN IN VERILOG

// *** OR Gate Behavior Level module my_orbehaviorvlog (y,a,b); output y; input a,b; reg y; always @ (a or b) begin if (a == 0) begin if (b == 0) y = 1 'b 0; else y = 1 'b 1; end else y = 1 'b1; end endmodule *** //

20

OR GATE IN GATE LEVEL DESIGN IN VERILOG

// *** OR Gate in Verilog module my_orgatevlog (y,a,b); output y; input a,b; or (y,a,b); endmodule *** //

WAVEFORM:

CONCLUSION: Thus the OR Gate is designed Verilog HDL and the output is verified.

21

Ex No: 1. (c)

NOT GATE REALISATION

AIM: Realize the NOT gate using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: NOT Gate is a circuit which performs, the one of the basic logic or Boolean operation, namely the NOT operation. It has one input and one output. Digital signal is applied at the input terminal A. The output is obtained at the output terminal marked Y and it is also a digital signal. The NOT operation is referred to as Inversion or Complementation. Mathematically, it is written as
Y = NOT A. = A

where A is the input variable and Y is the output variable. The variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1. The binary variables are also referred to as logical variable. The mathematical equation is known as the Boolean equation or the logical equation of the NOT gate. This is to be read as Y equals NOT A or Y equals complement of A.

PROCEDURE: 1. The Verilog Module Source for the NOT Gate is written. 2. It is implemented in Model Sim and Simulated. 3. Signals are provided and Output Waveforms are viewed. TRUTH TABLE: NOT

INPUT a 0 1

OUTPUT y 1 0

22

LOGIC DIAGRAM:

PROGRAM: NOT GATE BEHAVIOR LEVEL DESIGN IN VERILOG

// *** NOT Gate Behavior Leve module my_notbehaviorvlog (y,a); output y; input a; reg y; always @ (a) begin if (a == 0) y = 1 'b 1; else y = 1 'b 0; end endmodule // *** NOT Gate in Gate Level Design module my_notgate (y,a); output y; input a; not(y,a); endmodule *** //

NOT GATE IN GATE LEVEL DESIGN IN VERILOG

*** //

WAVEFORM:

CONCLUSION: Thus the NOT Gate is designed in Verilog HDL and the output is verified.
23

Ex No: 1. (d)

NAND GATE REALISATION

AIM: Realize the NAND gate using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: NAND Gate is a circuit which performs, the logic or Boolean operation derived from the basic logic operations NOT and AND, namely the NAND operation. It has N inputs (N 2) and one output. Digital signals are applied at the input terminals A, B, CN. The output is obtained at the output terminal marked Y and it is also a digital signal. The NAND operation is defined as: the output of an NAND gate is 0 if and only if all the inputs are 1. It is the inverse of the AND operation. The NAND gate is known to be one of the Universal gates. Mathematically, it is written as
Y=ABN

where A, B, C N are the input variables and Y is the output variable. The variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1. The binary variables are also referred to as logical variable. The mathematical equation is known as the Boolean equation or the logical equation of the NAND gate. The term gate is used because of the similarity between the operation of a digital circuit and a gate. For example, for an NAND operation the gate closes (Y = 0) only, when all the inputs are present. PROCEDURE: 1. The Verilog Module Source for the NAND Gate is written. 2. It is implemented in Model Sim and Simulated. 3. Signals are provided and Output Waveforms are viewed.

24

TRUTH TABLE: NAND

INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y 1 1 1 0

LOGIC DIAGRAM:

PROGRAM: NAND GATE BEHAVIOR LEVEL DESIGN IN VERILOG

// *** NAND Gate Behavior Level module my_nandbehaviorvlog (y,a,b); output y; input a,b; reg y; always @ (a or b) begin if ( a==1) begin if (b==1) y = 1 'b 0; else y = 1 'b 1; end else y = 1 'b1; end endmodule *** //

25

NAND GATE IN GATE LEVEL DESIGN IN VERILOG

// *** NAND gate in Gate Level module my_nandgatevlog (y,a,b); output y; input a,b; nand (y,a,b); endmodule *** //

WAVEFORM:

CONCLUSION: Thus the NAND Gate is designed in Verilog HDL and the output is verified.

26

Ex No: 1. (e)

NOR GATE REALISATION

AIM: Realize the NOR gate using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: NOR Gate is a circuit which performs, the logic or Boolean operation derived from the basic logic operations NOT and OR, namely the NOR operation. It has N inputs (N 2) and one output. Digital signals are applied at the input terminals A, B, CN. The output is obtained at the output terminal marked Y and it is also a digital signal. The NOR operation is defined as: the output of an NOR gate is 1 if and only if all the inputs are 0. It is the inverse of the OR operation. The NOR gate is known to be one of the Universal gates. Mathematically, it is written as
Y = A +B+ +N

where A, B, C N are the input variables and Y is the output variable. The variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1. The binary variables are also referred to as logical variable. The mathematical equation is known as the Boolean equation or the logical equation of the NOR gate. The term gate is used because of the similarity between the operation of a digital circuit and a gate. For example, for an NOR operation the gate opens (Y = 1) only, when all the inputs are absent.

PROCEDURE: 1. The Verilog Module Source for the NOR Gate is written. 2. It is implemented in Model Sim and Simulated. 3. Signals are provided and Output Waveforms are viewed.

27

TRUTH TABLE: NOR:

INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y 1 0 0 0

LOGIC DIAGRAM:

PROGRAM: NOR GATE BEHAVIOR LEVEL DESIGN IN VERILOG

// *** NOR Gate Behavior Level module my_norbehaviorvlog (y,a,b); output y; input a,b; reg y; always @ (a or b) begin if (a == 0) begin if (b == 0) y = 1 'b 1; else y = 1 'b 0; end else y = 1 'b 0; end endmodule *** //

28

NOR GATE IN GATE LEVEL DESIGN IN VERILOG

// *** NOR Gate in verilog module my_norgatevlog (y,a,b); output y; input a,b; nor (y,a,b); endmodule *** //

WAVEFORM

CONCLUSION: Thus the NOR Gate is designed Verilog HDL and the output is verified.

29

Ex No: 1. (f)

XNOR GATE REALISATION

AIM: Realize the XNOR gate using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: XNOR Gate or EX-NOR Gate or Exclusive-NOR Gate is a circuit which performs, the logic or Boolean operation derived from the basic logic operations AND, OR and NOT or the Universal gates NAND or NOR, namely the XNOR operation. It has N inputs (N 2) and one output. Digital signals are applied at the input terminals A, B, CN. The output is obtained at the output terminal marked Y and it is also a digital signal. The XNOR operation is defined as: the output of an XNOR gate is 1 if all the inputs are same, whereas the output is 0, if the inputs are not the same. It is the inverse of the NOR gate. Mathematically, it is written as Y = A EX-NOR B =A
X

where A, B, C N are the input variables and Y is the output variable. The variables are binary, i.e. each variable can assume only one of the possible values, 0 or 1. The binary variables are also referred to as logical variable. The mathematical equation is known as the Boolean equation or the logical equation of the XNOR gate. The term gate is used because of the similarity between the operation of a digital circuit and a gate. For example, for an XNOR operation the gate opens (Y = 1) only, when all the inputs are not same. PROCEDURE: 1. The Verilog Module Source for the XNOR Gate is written. 2. It is implemented in Model Sim and Simulated. 3. Signals are provided and Output Waveforms are viewed.

30

TRUTH TABLE: XNOR

INPUT A 0 0 1 1 B 0 1 0 1

OUTPUT Y 1 0 0 1

LOGIC DIAGRAM:

PROGRAM: XNOR GATE BEHAVIOR LEVEL DESIGN IN VERILOG

// *** XNOR Gate Behavior Level module my_xnorbehaviorvlog (y,a,b); output y; input a,b; reg y; always @ (a or b) begin if (a === b) y = 1 'b 1; else y = 1 'b 0; end endmodule *** //

31

NOR GATE IN GATE LEVEL DESIGN IN VERILOG

// *** XNOR Gate in Gate Level Design module my_xnorgatevlog (y,a,b); output y; input a,b; xnor (y,a,b); endmodule *** //

WAVEFORM:

CONCLUSION: Thus the XNOR Gate is designed in Verilog HDL and the output is verified.

32

Ex No: 2. (a)

HALF ADDER REALISATION

AIM: Realize the half adder using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: A combinational circuit that performs the addition of two bits is called a halfadder. This circuit needs two binary inputs and produces two binary outputs. One of the input variables designates the augend and other designates the addend. The output variables produce the sum and the carry. The simplified Boolean functions of the two outputs can be obtained as below: Sum S = xy + xy Carry C = xy Where x and y are the two input variables. PROCEDURE: 1. The half-adder circuit is designed and the Boolean function is found out. 2. The Verilog Module Source for the circuit is written. 3. It is implemented in Model Sim and Simulated. 4. Signals are provided and Output Waveforms are viewed. TRUTH TABLE: HALF ADDER
INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT SUM 0 1 1 0 CARRY 0 0 0 1

33

LOGIC DIAGRAM:

PROGRAM: HALF ADDER DESIGN IN VERILOG

// *** Half Adder module my_halfadrvlog (s,c,x,y); output s,c; input x,y; xor (s,x,y); and (c,x,y); endmodule module half_adder(S, C, A, B); output S, C; input A, B; wire S, C, A, B; assign S = A ^ B; assign C = A & B; endmodule *** //

HALF ADDER DESIGN IN VERILOG(Behavioral model)

WAVEFORM:

CONCLUSION: Thus the Half Adder is designed in Verilog HDL and the output is verified.
34

Ex No: 2. (b)

FULL ADDER REALISATION

AIM: Realize the full adder using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: A combinational circuit that performs the addition of three bits is called a half-adder. This circuit needs three binary inputs and produces two binary outputs. One of the input variables designates the augend and other designates the addend. Mostly, the third input represents the carry from the previous lower significant position. The output variables produce the sum and the carry. The simplified Boolean functions of the two outputs can be obtained as below: Sum S = x
+ +

Carry C = xy + xz + yz Where x, y & z are the two input variables. PROCEDURE:

1. 2. 3. 4. The full-adder circuit is designed and the Boolean function is found out. The Verilog Module Source for the circuit is written. It is implemented in Model Sim and Simulated. Signals are provided and Output Waveforms are viewed.

TRUTH TABLE: FULL ADDER

INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CIN 0 1 0 1 0 1 0 1 OUTPUT SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

35

LOGIC DIAGRAM:

PROGRAM: FULL ADDER DESIGN IN VERILOG

// *** Full Adder *** // module my_fuladrvlog (s,c,x,y,z); output s,c; input x,y,z; xor (s,x,y,z); assign c = ((x & y) | (y & z) | (z & x)); endmodule

WAVEFORM:

CONCLUSION:
Thus the Full Adder is designed Verilog HDL and the output is verified. 36

Ex No: 3.

IMPLEMENTATION OF 2 x 4 and 3 x 8 DECODER

To implement 2 x 4 and 3 x 8 Decoder Verilog HDL.

AIM:

TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator PROCEDURE: 1. Write and draw the Digital logic system. 2. Write the Verilog code for above system. 3. Enter the Verilog code in Xilinx software. 4. Check the syntax and simulate the above verilog code (using ModelSim or Xilinx) and verify the output waveform as obtained. LOGIC DIAGRAM: 2 to 4 Decoder:

PROGRAM: 2 TO 4DECODER DESIGN IN VERILOG

// Module Name: Decd2to4 module Decd2to4(i0, i1, out0, out1, out2, out3); input i0; input i1; output out0; output out1; output out2; output out3; reg out0,out1,out2,out3; always@(i0,i1) case({i0,i1}) 2'b00: {out0,out1,out2,out3}=4'b1000; 2'b01: {out0,out1,out2,out3}=4'b0100; 2'b10: {out0,out1,out2,out3}=4'b0010; 37

2'b11: {out0,out1,out2,out3}=4'b0001; default: $display("Invalid"); endcase endmodule

Output: 2to4 Decoder

INPUT OUTPUT

00 01 10 11

1000 0100 0010 0001

WAVEFORM:

3 TO 8 DECODER REALIZATION IN VERILOG THEORY: A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. It performs the reverse operation of the encoder. If the n-bit decoded information has unused or dont-care combinations, the decoder output will have fewer than 2n outputs. The decoders are represented as n-to-m line decoders, where m 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables. The name decoder is also used in conjunction with some code converters such as BCD-to-seven-segment decoders. Most, if not all, IC decoders include one or more enable inputs to control the circuit operation. A decoder with an enable input can function as a de-multiplexer.

38

PROCEDURE: 1. The decoder circuit is designed and the Boolean function is found out. 2. The Verilog Module Source for the circuit is written. 3. It is implemented in Model Sim and Simulated. 4. Signals are provided and Output Waveforms are viewed.
-------INPUT-------C 0 B 0 A 0 ------------------------ DECIMAL (OUTPUT)--------------------i1 1 i2 0 i3 0 i4 i5 0 i6 0 i7 0 i8 0 0

39

3 to 8 DECODER DESIGN IN VERILOG:

module my_decodr(d,x); output [0:7] d; input [0:2] x; wire [0:2] temp; not n1(temp[0],x[0]); not n2(temp[1],x[1]); not n3(temp[2],x[2]); and a0(d[0],temp[0],temp[1],temp[2]); and a1(d[1],temp[0],temp[1],x[2]); and a2(d[2],temp[0],x[1],temp[2]); and a3(d[3],temp[0],x[1],x[2]); and a4(d[4],x[0],temp[1],temp[2]); and a5(d[5],x[0],temp[1],x[2]); and a6(d[6],x[0],x[1],temp[2]); and a7(d[7],x[0],x[1],x[2]); endmodule

CONCLUSION: Thus the logic circuit for the 2 to 4 Decoder and 3 to 8 decoder are designed in Verilog HDL and the outputs are verified.

40

Ex No: 4

4 TO 2 ENCODER REALIZATION IN VERILOG

AIM: Realize the 4 to 2 Encoder in Verilog TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator; THEORY: An encoder has 2n (or fewer) input lines and n output lines. The output lines generate the binary code corresponding to the input value. In encoders, it is assumed that only one input has a value of 1 at any given time. The encoders are specified as m-ton encoders where m 2n. PROCEDURE: 1. 2. 3. 4. The encoder circuit is designed and the Boolean function is found out. The Verilog Module Source for the circuit is written. It is implemented in Model Sim and Simulated. Signals are provided and Output Waveforms are viewed.

LOGIC DIAGRAM:

41

TRUTH TABLE:
I/P 0 1 I/P1 0 I/P 2 0 I/P3 0 O/P0 0 O/P1 0

0 0

1 0

0 1

0 0

0 1

1 0

4 TO 2 ENCODER DESIGN IN VERILOG

// *** 4x2 Encoder Behavior Level Realisation module my_encodr2 (y,x); output [0:3] y; input [0:3] x; reg [0:1] y; always @ (x) case (x) 4'b0001: y = 11; 4'b0010: y = 10; 4'b0100: y = 01; 4'b1000: y = 00; default : $display ("Invalid Input"); endcase endmodule *** //

42

WAVEFORM:

CONCLUSION: Thus the logic circuit for the 4 to 2 encoder is designed in Verilog HDL and the output is verified.

43

Ex No: 5

RIPPLE ADDER REALIZATION IN VERILOG

AIM: To Design Ripple Adder using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: The n-bit adder built from n one bit full adders is known as ripple carry adder because of the carry is computed. The addition is not complete until n-1th adder has computed its Sn-1 output; that results depends upon ci input, n and so on down the line, so the critical delay path goes from the 0-bit inputs up through cis to the n-1 bit.(We can find the critical path through the n-bit adder without knowing the exact logic in the full adder because the delay through the n-bit adder without knowing the exact logic in the full adder because the delay through the n-bit carry chain is so much longer than the delay from a and b to s). The ripple-carry adder is area efficient and easy to design but it is when n is large.It can also be called as cascaded full adder. The simplified Boolean functions of the two outputs can be obtained as below: Sum si = ai xor bi xor ci Carry ci+1 = aibi +bi ci +ai ci Where x, y & z are the two input variables. PROCEDURE: 1. The ripple carry generator circuit is designed and the Boolean function is found out. 2. The full-adder circuit is designed and the Boolean function is found out. 3. The Verilog Module Source for the circuit is written. 4. It is implemented in Model Sim and Simulated. 5. Signals are provided and Output Waveforms are viewed.

44

VERILOG PROGRAM FOR RIPPLE CARRY ADDER:

module ripplecarry_adder(s,cout,a,b,cin); //port list output [5:0] s; output cout; // port declaration input [5:0] a,b; input cin; wire c0,c1,c2,c3,c4; // instantiating 1b-ti full adders fulladder_1bit fulladder_1bit_f1(s[0],c0,a[0],b[0],cin); fulladder_1bit fulladder_1bit_f2(s[1],c1,a[1],b[1],c0); fulladder_1bit fulladder_1bit_f3(s[2],c2,a[2],b[2],c1); fulladder_1bit fulladder_1bit_f4(s[3],c3,a[3],b[3],c2); fulladder_1bit fulladder_1bit_f5(s[4],c4,a[4],b[4],c3); fulladder_1bit fulladder_1bit_f6(s[5],cout,a[5],b[5],c4); endmodule module fulladder_1bit(sum,cout,in1,in2,cin); output cout; output sum; input in1,in2,cin; assign {cout,sum}= in1 + in2 + cin; // through data flow modeling. Endmodule

LOGIC DIAGRAM:

45

WAVE FORM:

CONCLUSION: Thus the logic circuit for the ripple carry adder is designed in Verilog HDL and the output is verified.

46

Ex No: 6(a)

4 BIT ASYNCHRONOUS RIPPLE COUNTER REALIZATION IN VERILOG

AIM: To realize an asynchronous ripple counter in Verilog . TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator

THEORY: In a ripple counter, the flip-flop output transition serves as a source for triggering other flip-flops. In other words, the Clock Pulse inputs of all flip-flops (except the first) are triggered not by the incoming pulses, but rather by the transition that occurs in other flip-flops. A binary ripple counter consists of a series connection of complementing flip-flops (JK or T type), with the output of each flip-flop connected to the Clock Pulse input of the next higher-order flip-flop. The flip-flop holding the LSB receives the incoming count pulses. All J and K inputs are equal to 1. The small circle in the Clock Pulse /Count Pulse indicates that the flip-flop complements during a negativegoing transition or when the output to which it is connected goes from 1 to 0. The flipflops change one at a time in rapid succession, and the signal propagates through the counter in a ripple fashion. A binary counter with reverse count is called a binary downcounter. In binary down-counter, the binary count is decremented by 1 with every input count pulse.

PROCEDURE: 1. 2. 3. 4. The 4 bit asynchronous ripple counter circuit is designed. The Verilog Module Source for the circuit is written. It is implemented in Model Sim and Simulated. Signals are provided and Output Waveforms are viewed.

47

LOGIC DIAGRAM:

STATE TABLE:

TRUTH TABLE FOR JK FLIP-FLOP:

J 0 0 1 1 K 0 1 0 1 Qn+1 Qn 0 1 Qn

4-BIT ASYNCHRONOUS RIPPLE COUNTER DESIGN IN VERILOG

module my_asyncbincnt (q,qbar,clk,reset); output [0 : 3] q; output [0 : 3] qbar; input clk,reset; wire [0 : 1] temp; reg high; initial high = 1'b1; my_jkffbehaviorvlog ff1 (q[0],qbar[0],high,high,clk,reset); my_jkffbehaviorvlog ff2 (q[1],qbar[1],high,high,q[0],reset); 48

my_jkffbehaviorvlog ff3 (q[2],qbar[2],high,high,q[1],reset); my_jkffbehaviorvlog ff4 (q[3],qbar[3],high,high,q[2],reset); endmodule module my_jkffbehaviorvlog (q,qbar,j,k,clk,reset); output q,qbar; input j,k,clk,reset; reg q,qbar; always @ (negedge clk or reset) if (~reset) begin q = 1'b0; qbar = 1'b1; end else if (reset) begin if (j==0 && k ==0) begin q = q; qbar = qbar; end else if ( j== 0 && k ==1) begin q = 1'b0; qbar = 1'b1; end else if (j==1 && k == 0) begin q = 1'b1; qbar = 1'b0; end else if (j ==1 && k ==1) begin q = ~q; qbar = ~qbar; end else begin q = 1'bz; qbar = 1'bz; end end endmodule;

49

WAVEFORMS: IN BINARY

IN DECIMAL

CONCLUSION: Thus the asynchronous ripple counter is designed in Verilog HDL and the output is verified.

50

Ex No:6 (b)
AIM:

4 BIT SYNCHRONOUS RIPPLE COUNTER REALIZATION IN VERILOG

To realize a synchronous ripple counter in Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: Synchronous counters are distinguished from asynchronous counters in that clock pulses are applied to the CP inputs of all flip-flops. The common pulse triggers all the flip-flops simultaneously, rather than one at a time in succession as in asynchronous counter. The decision whether a flip-flop is to be complemented or not is determined from the values of the J and K inputs at the time of the pulse. If J = K = 0, the flip-flop remains unchanged. If J = K = 1, the flip-flop complements. In a synchronous binary ripple counter, the flip-flop in the lowest-order position is complemented with very pulse. This means that its J and K inputs must be maintained at logic-1. A flip-flop in any other position is complemented with a pulse provided all the bits in the lower-order positions are equal to 1, because the lower-order bits (when all 1s) will change to 0s on the next count pulse. The binary count dictates the next higher-order bit is complemented. Synchronous binary counters have a regular pattern and can easily be constructed with complementing flip-flops ( J K or T Type) and gates. PROCEDURE: 1. The 4 bit synchronous ripple counter circuit is designed. 2. The Verilog Module Source for the circuit is written.

3. It is implemented in Model Sim and Simulated. 4. Signals are provided and Output Waveforms are viewed.

51

LOGIC DIAGRAM:

STATE TABLE:

TRUTH TABLE FOR JK FLIP-FLOP:

J 0 0 1 1

K 0 1 0 1

Qn+1 Qn 0 1 Qn

52

4-BIT SYNCHRONOUS RIPPLE COUNTER DESIGN IN VERILOG

module my_syncbincnt (q,qbar,load,clk,reset); output [0 : 3] q; output [0 : 3] qbar; input load,clk,reset; wire [0 : 1] temp; my_jkffbehaviorvlog ff1 (q[0],qbar[0],load,load,clk,reset); my_jkffbehaviorvlog ff2 (q[1],qbar[1],q[0],q[0],clk,reset); and (temp[0],q[0],q[1]); my_jkffbehaviorvlog ff3 (q[2],qbar[2],temp[0],temp[0],clk,reset); and (temp[1],q[2],q[0],q[1]); my_jkffbehaviorvlog ff4 (q[3],qbar[3],temp[1],temp[1],clk,reset); endmodule module my_jkffbehaviorvlog (q,qbar,j,k,clk,reset); output q,qbar; input j,k,clk,reset; reg q,qbar; always @ (negedge clk or reset) if (~reset) begin q = 1'b0; qbar = 1'b1; end else if (reset) begin if (~clk) begin if (j==0 && k ==0) begin q = q; qbar = qbar; end else if ( j== 0 && k ==1) begin q = 1'b0; qbar = 1'b1; end else if (j==1 && k == 0) begin q = 1'b1; qbar = 1'b0; end else if (j ==1 && k ==1) begin q = ~q; qbar = ~qbar; end else 53

begin q = 1'bz; qbar = 1'bz; end end end endmodule;

WAVEFORMS:

CONCLUSION: Thus the synchronous ripple counter is designed in Verilog HDL and the output is verified.
54

Ex No: 7(a)

CODE CONVERSION

BCD TO DECIMAL DECODER REALIZATION IN VERILOG AIM: Realize the BCD to Decimal decoder in Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator; THEORY: A BCD to decimal decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. It performs the reverse operation of the encoder. If the n-bit decoded information has unused or dontcare combinations, the decoder output will have fewer than 2n outputs. The decoders are represented as n-to-m line decoders, where m 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables. The name decoder is also used in conjunction with some code converters such as BCD-to-seven-segment decoders. Most, if not all, IC decoders include one or more enable inputs to control the circuit operation. A decoder with an enable input can function as a de-multiplexer.

PROCEDURE: 1. The BCD to decimal decoder circuit is designed . 2. The Verilog Module Source for the circuit is written. 3. It is implemented in Model Sim and Simulated. 4. Signals are provided and Output Waveforms are viewed.

55

TRUTH TABLE:
-------INPUT-------X3 0 0 X2 0 X1 0 X0 0 ------------------------ DECIMAL (OUTPUT)--------------------D0 0 D1 0 0 D2 0 D3 0 D4 0 D5 0 D6 0 D7 0 D8

56

LOGIC DIAGRAM:
X3 X2 X1 X0

PROGRAM:
module bcd(x, d); output[0:9] d; input[0:3] x; wire [0:3]temp; not n1 (temp[0],x[0]); not n2 (temp[1],x[1]); not n3 (temp[2],x[2]); not n4 (temp[3],x[3]); and a0 (d[0],temp[0],temp[1],temp[2],temp[3]); and a1 (d[1],temp[0],temp[1],temp[2],x[3]); and a2 (d[2],temp[0],temp[1],x[2],temp[3]); and a3 (d[3],temp[0],temp[1],x[2],x[3]); and a4 (d[4],temp[0],x[1],temp[2],temp[3]); and a5 (d[5],temp[0],x[1],temp[2],x[3]); and a6 (d[6],temp[0],x[1],x[2],temp[3]); and a7 (d[7],temp[0],x[1],x[2],x[3]); and a8 (d[8],x[0],temp[1],temp[2],temp[3]); and a9 (d[9],x[0],temp[1],temp[2],x[3]); endmodule

57

WAVE FORM:

CONCLUSION: Thus the logic circuit for the BCD to decimal decoder is designed in Verilog HDL and the output is verified.

58

Ex No: 7(b)

DECIMAL TO BCD ENCODER REALIZATION IN VERILOG

AIM: Realize the Decimal to BCD encoder in Verilog.

TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator

THEORY: An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder 2^n input lines and n output lines. In encoder the output lines generate the binary code corresponding to the input lines the decimal to BCD encoder, it has ten

input lines and four output lines. Both input and output lines are asserted active low. It is important to note that there is no input line for decimal zero.

PROCEDURE: 1. The decimal to BCD encoder is designed. 2. The verilog HDL program source code for the circuit is written. 3. It is implemented in Model sim and simulated. 4. Signals are provided and output waveforms are viewed.

59

TABLE TRUTH
------------------------ DECIMAL (INPUT)--------------------i1 i2 i3 i4 i5 i6 i7 i8 i9 -------OUTPUT-----D C B A

60

LOGIC DIAGRAM:

PROGRAM:
module encod(i1,i2,i3,i4,i5,i6,i7,i8,i9, a,b,c,d); input i1,i2,i3,i4,i5,i6,i7,i8,i9; output a,b,c,d; or (a,i1,i3,i5,i7,i9); or (b,i2,i3,i6,i7); or (c,i4,i5,i6,i7); or (d,i8,i9); endmodule

CONCLUSION: Thus the logic circuit for the decimal to BCD encoder is designed in Verilog HDL and the output is verified.

61

Ex No: 7. (c)

UNIVERSAL CODE CONVERTER REALIZATION IN VERILOG

AIM: Realize the universal code converter in Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator.
THEORY:

The availability of a large variety of codes for the same discrete elements of information results in the use of different codes by different digital system. It is sometimes necessary to use the output of one system as the input to another. A conversion circuit must be inserted between the two systems if each uses different codes for the same information. Thus, a code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B. A combinational circuit which performs this transformation by means of logic gates, is known to be Code Converter. PROCEDURE: 1. The various code converter circuits are designed and their Boolean functions are found out. 2. The Verilog Module Sources for the circuits are written. 3. They are implemented in Model Sim and Simulated. 4. Signals are provided and Output Waveforms are viewed.

62

LOGIC DIAGRAMS: BINARY TO BCD CONVERTER

BCD TO BINARY CONVERTER

63

BCD TO XS3 CONVERTER

XS3 TO BCD CONVERTER

64

BINARY TO GRAY CONVERTER

GRAY TO BINARY CONVERTER :

65

TRUTH TABLES: BINARY TO BCD CONVERTER

BINARY CODE D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BCD CODE B4 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 B1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

BCD TO BINARY CONVERTER

BCD CODE B4 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 B1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BINARY CODE F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 E 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

66

BCD to XS3 Converter

BCD CODE B3 B2 B1 B0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 EXCESS 3 CODE E3 E2 E1 E0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0

XS3 to BCD Converter

EXCESS 3 BCD CODE CODE E3 E2 E1 E0 B3 B2 B1 B0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1

BINARY TO GRAY CONVERTER CONVERTER

GRAY TO BINARY

BINARY CODE B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

GRAY CODE G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

GRAY CODE G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

BINARY CODE B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

67

CODE CONVERTERS DESIGN IN VERILOG:

// *** Code Converterts Design *** // module my_codeconvertrvlog (op,ip); output [4 : 0] op; input [4 : 0] ip; reg [4 : 0] op; integer choice; initial choice = 1'd0; always @ (choice or ip) begin case (choice) 0: begin $display ("Enter UR Choice "); $display (" 1'd1 For Binary to BCD"); $display (" 1'd2 For BCD to Binary"); $display (" 1'd3 For BCD to Excess 3"); $display (" 1'd4 For Excess3 to BCD"); $display (" 1'd5 For Binary to Gray"); $display (" 1'd6 For Gray to Binary"); end 1: begin op[0] = op[1] = op[2] = op[3] = op[4] = end 2: begin op[0] = ip[0]; op[1] = ip[1] ^ ip[4]; op[2] = ((~ip[4]) & ip[2]) | (ip[2] & (~ip[1])) | (ip[4] & (~ip[2]) & ip[1]); op[3] = ((~(ip[4]) & ip[3]) | (ip[4] & (~(ip[3])) & (~ (ip[2]))) | (ip[4] & (~(ip[3])) & (~ (ip[1])))); op[4] = ((ip[4] & ip[3]) | (ip[4] & ip[2] & ip[1])); end 3: begin op[0] = (~(ip[0])); op[1] = (~ (ip[0]^ip[1])); op[2] = ((ip[2])&(~ip[1])&(~ip[0])) | ((~(ip[2])&(ip[0]|ip[1]))); 68 ip[0]; (ip[3] & ip[2] & (~ip[1]) | ((~ip[3]) & ip[1])); ((~ip[3]) & ip[2]) | (ip[2] & ip[1]); ip[3] & (~ip[2]) & (~ip[1]); (ip[3] & ip[2]) | (ip[3] & ip[1]);

end 4: begin

op[3] = ip[3] | (ip[2] & ( ip[0] | ip[1])); op[4] = 1'b 0;

op[0] = ~(ip[0]); op[1] = (ip[0]^ip[1]); op[2] = (( ( (~(ip[2]))&(~(ip[1])))) | (ip[3] & ip[1] & (~(ip[0])))); end begin op[0] = op[1] = op[2] = op[3] = op[4] = (ip[1] ^ ip[0]); (ip[2] ^ ip[1]); (ip[3] ^ ip[2]); ip[3]; 1'b 0;

(ip[2]&ip[1]&ip[0]) |

op[3] = ( (ip[3]&ip[2]) | (ip[3]&ip[1]&ip[0])); op[4] = 1'b 0;

5:

end 6: begin

end default : begin end endcase end endmodule

op[0] = op[1] = op[2] = op[3] = op[4] =

((ip[3]^ip[2])^(ip[1]^ip[0])); ip[3]^ip[2]^ip[1]; ip[3]^ip[2]; ip[3]; 1'b 0;

$display ("Entered a Wrong Option"); $display ("To Know the choices Enter 1'd0");

69

WAVEFORMS: BINARY TO BCD CONVERTER

70

BCD TO BINARY CONVERTER

71

BCD TO XS3 CONVERTER

72

XS3 TO BCD CONVERTER

73

BINARY TO GRAY CONVERTER

74

GRAY TO BINARY CONVERTER

CONCLUSION:

Thus the logic circuit for the universal code converter is designed in Verilog HDL and the output is verified.

75

EX.NO : 8 AIM:

STUDY OF SIMULATION USING TOOLS

To study the Simulation tools. THEORY: CREATING A TEST BENCH FOR SIMULATION: In this section, you will create a test bench waveform containing input stimulus you can use to simulate the counter module. This test bench waveform is a graphical view of a test bench. It is used with a simulator to verify that the counter design meets both behavioral and timing design requirements. You will use the Waveform Editor to create a test bench waveform (TBW) file. 1. Select the counter HDL file in the Sources in Project window. 2. Create a new source by selecting Project _ New Source. 3. In the New Source window, select Test Bench Waveform as the source type, and type test bench in the File Name field. 4. Click Next. 5. The Source File dialog box shows that you are associating the test bench with the source file: counter. Click Next. 6. Click Finish. You need to set initial values for your test bench waveform in the Initialize Timing dialog box before the test bench waveform editing window opens. 7. Fill in the fields in the Initialize Timing dialog box using the information below: Clock Time High: 20 ns. Clock Time Low: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Initial Offset: 0 ns Global Signals: GSR (FPGA) Leave the remaining fields with their default values.

76

8. Click OK to open the waveform editor. The blue shaded areas are associated with each input signal and correspond to the Input Setup Time in the Initialize Timing dialog box. In this tutorial, the input transitions occur at the edge of the blue cells located under each rising edge of the CLOCK input.

Fig 2: Waveform Editor - Test Bench

Fig 3:Waveform Editor - Expected Results 9. In this design, the only stimulus that you will provide is on the DIRECTION port. Make the transitions as shown below for the DIRECTION port: Click on the blue cell at approximately the 300 ns clock transition. The signal switches to high at this point. Click on the blue cell at approximately the 900 ns clock transition. The signal switches back to low.

77

Click on the blue cell at approximately the 1400 ns clock transition. The signal switches to high again. 10. Select File _ Save to save the waveform. In the Sources in Project window, the TBW file is automatically added to your project. 11. Close the Waveform Editor window. ADDING EXPECTED RESULTS TO THE TEST BENCH WAVEFORM: In this step you will create a self-checking test bench with expected outputs that correspond to your inputs. The input setup and output delay numbers that were entered into the Initialize Timing dialog when you started the waveform editor are evaluated against actual results when the design is simulated. This can be useful in the Simulate Post- Place & Route HDL Model process, to verify that the design behaves as expected in the target device both in terms of functionality and timing. To create a self-checking test bench, you can edit output transitions manually, or you can run the Generate Expected Results process: 1. Select the testbench.tbw file in the Sources in Project window. 2. Double-click the Generate Expected Simulation Results process. This process converts the TBW into HDL and then simulates it in a background process. 3. The Expected Results dialog box will open. Select Yes to post the results in the waveform editor. 4. Click the + to expand the COUNT_OUT bus and view the transitions that correspond to the Output Valid Delay time (yellow cells) in the Initialize Timing dialog box. 5. Select File _ Save to save the waveform. 6. Close the Waveform Editor.Now that you have a test bench, you are ready to simulate your design. SIMULATING THE BEHAVIORAL MODEL (ISE SIMULATOR): If you are using ISE Base or Foundation, you can simulate your design with the ISE Simulator. If you wish to simulate your design with a ModelSim simulator, skip this section and proceed to the Simulating the Behavioral Model (ModelSim) section.

78

Fig 4:Simulator Processes for Test Bench

Fig 5:Behavioral Simulation in ISE Simulator To run the integrated simulation processes in ISE: 1. Select the test bench waveform in the Sources in Project window. You can see the Xilinx ISE Simulator processes in the Processes for Source window. 2. Double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench. 3. To see your simulation results, select the test bench tab and zoom in on the transitions. You can use the zoom icons in the waveform view, or right click and select a zoom command.The ISE window, including the waveform view. 4. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port.
79

5. Close the waveform view window. You have completed simulation of your design using the ISE Simulator. Skip past the ModelSim section below and proceed to the Creating and Editing Timing and Area Constraintssection. SIMULATING THE BEHAVIORAL MODEL (MODELSIM): If you have a ModelSim simulator installed, you can simulate your design using the integrated ModelSim flow. You can run processes from within ISE which launches the installed ModelSim simulator. To run the integrated simulation processes in ISE: 1.Select the test bench in the Sources in Project window. You can see ModelSim Simulator processes in the Processes for Source window in Fig 6.

Fig 6: Simulator Processes for Test Bench

80

Fig 7:Behavioral Simulation in ModelSim 2. Double-click the Simulate Behavioral Model process. The ModelSim simulator opens and runs your simulation to the end of the test bench. The ModelSim window, including the waveform, should look like Fig 7. To see your simulation results, view the Wave window. 1. Right-click in the Wave window and select a zoom command. 2. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port. 3. Close the ModelSim window.

81

Figure: RTL Viewer - Detailed View

RESULT: Thus the stimulation tool was studied.

82

Ex No:8(a)

HALF ADDER REALISATION

AIM: Realize the half adder using Verilog. TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: A combinational circuit that performs the addition of two bits is called a half-adder. This circuit needs two binary inputs and produces two binary outputs. One of the input variables designates the augend and other designates the addend. The output variables produce the sum and the carry. The simplified Boolean functions of the two outputs can be obtained as below: Sum S = xy + xy Carry C = xy Where x and y are the two input variables. PROCEDURE: 1. The half-adder circuit is designed and the Boolean function is found out. 2. The Verilog Module Source for the circuit is written. 3. It is implemented in Model Sim and Simulated.
4. Signals are provided and Output Waveforms are viewed.

83

TRUTH TABLE: HALF ADDER

INPUT A 0 0 1 1 OUTPUT SUM CARRY 0 0 1 1 0 0 0 1

B 0 1 0 1

LOGIC DIAGRAM:

PROGRAM: HALF ADDER DESIGN IN VERILOG

// *** Half Adder module my_halfadrvlog (s,c,x,y); output s,c; input x,y; xor (s,x,y); and (c,x,y); endmodule *** //

84

WAVEFORM:

CONCLUSION: Thus the Half Adder is designed in Verilog HDL and the output is verified.

85

Ex No:8(b) MULTIPLEXER REALISATION IN VERILOG

AIM: Design a 2 to 1 and 4 to 1 multiplexer circuit in Verilog. TOOLS REQUIRED: Simulation Tools: Verilog Xilinx Model Sim; THEORY: A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is selected. A multiplexer is also called a data selector, since it selects one of many inputs and steers the binary information to the output lines. Multiplexer ICs may have an enable input to control the operation of the unit. When the enable input is in a given binary state (the disable state), the outputs are disabled, and when it is in the other state (the enable state), the circuit functions as normal multiplexer. The enable input (sometimes called strobe) can be used to expand two or more multiplexer ICs to digital multiplexers with a larger number of inputs. The size of the multiplexer is specified by the number 2n of its input lines and the single output line. In general, a 2n to 1 line multiplexer is constructed from an n to 2n decoder by adding to it 2n input lines, one to each AND gate. The outputs of the AND gates are applied to a single OR gate to provide the 1 line output. PROCEDURE:
1.

The multiplexer circuit is designed and the Boolean function is found out. The Verilog Module Source for the circuit is written. It is implemented in Model Sim and Simulated. Signals are provided and Output Waveforms are viewed.
86

2. 3. 4.

LOGIC DIAGRAM:

4 TO 1 MULTIPLEXER DESIGN IN VERILOG

module my_4to1muxbehavirvlog (y,i,en,sel); output y; input [0 : 3] i; input [0 : 1] sel; input en; reg y; always @ (i or en or sel) begin if (en === 0) begin case (sel) 2'b00 : y = i[0]; 2'b01 : y = i[1]; 2'b10 : y = i[2]; 2'b11 : y = i[3]; default : y = 1'bX; endcase end else y = 1'bZ; end endmodule

87

2 TO 1 MULTIPLEXER DESIGN IN VERILOG

module mux_using_if( din_0 , // Mux first input din_1 , // Mux Second input sel , // Select input mux_out // Mux output ); //-----------Input Ports--------------input din_0, din_1, sel ; //-----------Output Ports--------------output mux_out; //------------Internal Variables-------reg mux_out; //-------------Code Starts Here--------always @ (sel or din_0 or din_1) begin : MUX if (sel == 1'b0) begin mux_out = din_0; end else begin mux_out = din_1 ; end end endmodule //End Of Module mux

2 TO 1 MULTIPLEXER DESIGN IN VERILOG

din_0 , // Mux first input din_1 , // Mux Second input sel , // Select input mux_out // Mux output ); //-----------Input Ports--------------input din_0, din_1, sel ; //-----------Output Ports--------------output mux_out; //------------Internal Variables-------reg mux_out; //-------------Code Starts Here--------always @ (sel or din_0 or din_1) begin : MUX case(sel ) 1'b0 : mux_out = din_0; 1'b1 : mux_out = din_1; endcase end endmodule //End Of Module mux 88

WAVEFORM:

CONCLUSION: Thus the logic circuit for the 4 to 1 multiplexer is designed in Verilog HDL and the output is verified.

89

Ex No:8(c) DE-MULTIPLEXER REALISATION IN VERILOG

AIM: Design a 4 to 1 de-multiplexer circuit in Verilog.

TOOLS REQUIRED: Simulation Tools: Verilog Xilinx Model Sim;

THEORY: The de-multiplexer performs the reverse operation of a multiplexer. It is a combinational circuit which accepts a single input and distributes it over several outputs. The number of output lines is n and the number of select lines is 2n lines. Demultiplexer ICs may have an enable input to control the operation of the unit. When the enable input is in a given binary state (the disable state), the outputs are disabled, and when it is in the other state (the enable state), the circuit functions as normal demultiplexer. The size of the de-multiplexer is specified by the single input line and the number 2n of its output lines.

PROCEDURE: 1. The de-multiplexer circuit is designed and the Boolean function is found out. 2. The Verilog Module Source for the circuit is written. 3. It is implemented in Model Sim and Simulated. 4. Signals are provided and Output Waveforms are viewed.

90

LOGIC DIAGRAM:

TRUTH TABLE:
INPUTS I 1 1 1 1 S0 0 0 1 1 S1 0 1 0 1 OUTPUTS Q0 1 0 0 0 Q1 0 1 0 0 Q2 0 0 1 0 Q3 0 0 0 1

1 TO 2 DE-MULTIPLEXER DESIGN IN VERILOG

module Demux1x2_DF(Out0,Out1,S,In); output Out0,Out1; input S,In; assign Out0=(~S)&In; assign Out1=S&In; endmodule

91

1 TO 4 DE-MULTIPLEXER DESIGN IN VERILOG

module my_1to4demuxgatevlog(y,i,en,s); output [0 :3] y; input i,en; input [0 : 1] s; and (y[0],~en,~s[1],~s[0],i); and (y[1],~en,~s[1],s[0],i); and (y[2],~en,s[1],~s[0],i); and (y[3],~en,s[1],s[0],i); endmodule or Verilog code for 1 to 4 demux module demux(din, s, dout); input din; input [1:0] s; output [3:0] dout; reg [3:0] dout; always @ (din or s) c 2b01: dout(1)=din; 2b10: dout(2)=din; 2b11: dout ase(s) 2b00: dout(0)=din; (3)=din; endcase endmodule

92

WAVEFORM:

CONCLUSION: Thus the logic circuit for the 1 to 4 de-multiplexer is designed in Verilog HDL and the output is verified.

93

Exno:9(a)

D FLIP-FLOP REALIZATION IN VERILOG

AIM: Realize the D Flip-Flop in Verilog TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch states. The basic flipflop has two outputs Q and Q. The outputs Q and Q are always complementary. The flip-flop has two stable states which are known as the 1 state and 0 state. In the 1 state, the output Q = 1 and hence called Set state. In the 0 state, the output Q = 0 and also called as Reset or Clear state. The basic flip-flop can be obtained by using NAND or NOR gates. The basic flip-flop circuit is also called latch, since the information is latched or locked in this circuit. The basic flip-flop is also called the basic binary memory cell, since it maintains a binary state as long as power is available. It is often required to set or reset the basic memory cell in synchronism with a train of pulses known as clock. Such a circuit is referred to as clocked set-reset (S-R) Flip-Flop. In a flip-flop, when the power is switched on, the state of the circuit is uncertain. It is desired to initially set or reset the flip-flop, i.e. the initial state of the flip-flop is to be assigned. This is accomplished by using the direct or asynchronous inputs, referred to as preset and clear inputs. The uncertainty in the state of an S-R Flip Flop when Sn = Rn = 1 can be eliminated by ensuring that the inputs S and R are never equal to 1 at the same time. This is done in the D Flip-Flop. This D Flip-Flop has only two inputs: D and Cp. The D input goes directly to the S input and its complement is applied to the R input. As long as the clock pulse input is 0, the D flip-flop cannot change the state regardless of the value of D. The D input is sampled when CP = 1. If D is 1, the Q output goes to 1, placing the FlipFlop in the set state. If D is 0, the output Q goes to 0 and the Flip-Flop switches to clear

94

or reset state. The D flip-flop is so called because of its ability to hold data into its internal storage. This type of flip-flop is sometimes called gated D- latch. PROCEDURE: 1. The D flip-flop circuit is designed and the Boolean function is found out. 2. The Verilog Module Source for the circuit is written. 3. It is implemented in Model Sim and Simulated. 4. Signals are provided and Output Waveforms are viewed.

D FLIP FLOP BEHAVIOR LEVEL DESIGN IN VERILOG

module my_dffbehaviorvlog(q,qbar,d,clk,clr); output q,qbar; input d,clk,clr; reg q,qbar; always @ (clr or posedge clk) begin if (~clr) begin q = 1'b0; qbar = 1'b1; end else begin q = d; assign qbar = ~q; end end endmodule

D FLIP FLOP GATE LEVEL DESIGN IN VERILOG

module my_dffgatevlog (q,qbar,d,clk,clr); output q,qbar; input d,clk,clr; wire temp1,temp2,temp3,temp4,high; assign high = 1'b1; nand na0 (temp1,d,clk); nand na1 (temp2,~d,clk); nand na2 (temp3,qbar,temp1); nand na3 (temp4,q,temp2); and a0 (q,temp3,clr); and a1 (qbar,temp4,high); endmodule 95

D FLIP FLOP STRUCTURE LEVEL DESIGN IN VERILOG

module my_dffstructvlog (q,qbar,d,clk,clr); output q,qbar; input d,clk,clr; my_srffbehaviorvlog sr1(q,qbar,d,~d,clk,clr); endmodule // *** SR Flip Flop Behavior Level Design module my_srffbehaviorvlog (q,qbar,s,r,clk,clr); output q,qbar; input s,r,clk,clr; reg q,qbar; always @ (posedge clk or clr) if (clr) begin if (clk) begin if (s ==0) begin if(r ==0) begin q = q; qbar = qbar; end else begin q = 0; qbar = 1; end end else begin if (r ==0) begin q = 1; qbar = 0; end else begin q = 1'bz;qbar = 1'bz; end end end end else begin q = 1'b0; qbar = 1'b1; end endmodule

*** //

96

EDGE TRIGGERED D FLIP FLOP DESIGN IN VERILOG

module my_dff (q,qbar,d,clk,reset); output q,qbar; input d,clk,reset; reg temp0,temp1,temp2,temp3,q,qbar; always @ (posedge clk or reset ) begin if (reset) begin assign temp0 = !(temp3 && temp1); assign temp1 = !(temp0 && ~clk); assign temp2 = !(temp1 && ~clk && temp3); assign temp3 = ! (temp2 && d); assign q = !(temp1 && qbar); assign qbar = !(temp2 && q); end else begin deassign q; deassign qbar; q = 1'b0; qbar = 1'b1; end end endmodule

TRUTH TABLE:
INPUT OUTPUT STATE RESET SET NO CHANGE

CLK D QN QN+1 0 0 1 X X X X 0 1 QN

LOGIC DIAGRAM:

97

WAVEFORMS:

CONCLUSION: Thus the D flip-flop is realized in Verilog HDL and the output is verified.

98

Exno:9(b)
AIM:

T FLIP-FLOP REALIZATION IN VERILOG

Realize the T Flip-Flop in Verilog TOOLS REQUIRED: Synthesis tool: Xilinx ISE. Simulation tool: ModelSim Simulator THEORY: A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch states. The basic flip-flop has two outputs Q and Q. The outputs Q and Q are always complementary. The flip-flop has two stable states which are known as the 1 state and 0 state. The basic flip-flop can be obtained by using NAND or NOR gates. The basic flipflop circuit is also called latch, since the information is latched or locked in this circuit. The basic flip-flop is also called the basic binary memory cell, since it maintains a binary state as long as power is available. It is often required to set or reset the basic memory cell in synchronism with a train of pulses known as clock. Such a circuit is referred to as clocked set-reset (S-R) Flip-Flop. In a flip-flop, when the power is switched on, the state of the circuit is uncertain. It is desired to initially set or reset the flip-flop, i.e. the initial state of the flip-flop is to be assigned. This is accomplished by using the direct or asynchronous inputs, referred to as preset and clear inputs. In a JK Flip Flop, if J = K, the resulting flip-flop obtained is referred to as a Ttype flip-flop. It has only one input, referred to as T-input. If T = 1, it acts as a toggle switch, i.e. for every clock pulse, the output Q changes. The designation T comes from the ability of the flip-flop to toggle, or complement, its state. PROCEDURE: 1. The T Flip-Flop circuit is designed and the Boolean function is found out. 2. The Verilog Module Source for the circuit is written. 3. It is implemented in Model Sim and Simulated. 4. Signals are provided and Output Waveforms are viewed.

99

TRUTH TABLE:
PREVIOUS STATE QN 0 0 1 1 INPUT T 0 1 0 1 OUTPUT Qn+1 0 1 1 1

LOGIC DIAGRAM:

T FLIP FLOP STRUCTURE LEVEL DESIGN IN VERILOG

module my_tffstruct (q,qbar,t,clk,reset); output q,qbar; input t,clk,reset; my_jkffbehaviorvlog jktot (q,qbar,t,t,clk,reset); endmodule module my_jkffbehaviorvlog (q,qbar,j,k,clk,reset); output q,qbar; input j,k,clk,reset; reg q,qbar; always @ (posedge clk or posedge reset) if (reset) begin q = 1'b0; qbar = 1'b1; end else begin if (j==0 && k ==0) begin q = q; qbar = qbar; end 100

else if ( j== 0 && k ==1) begin q = 1'b0; qbar = 1'b1; end else if (j==1 && k == 0) begin q = 1'b1; qbar = 1'b0; end else if (j ==1 && k ==1) begin q = ~q; qbar = ~qbar; end else begin q = 1'bz; qbar = 1'bz; end end endmodule

WAVEFORMS:

CONCLUSION: Thus the T flip-flop is realized in Verilog HDL and the output is verified

101

EX.No:10 AIM:

STUDY OF DEVELOPMENT TOOL FOR FPGA

To study the development tool for FPGA and simulate the adders and demux. TOOLS REQUIRED: FPGA Spartan 3E kit Xilinx software PROCEDURE: Step 1: Open Xilinx software Step 2: Select File New Project.

Step 3: In the New Project window enter project name and project location

102

Step 4: Select the corresponding entries for the property names.

Step 5: Click New Source

103

Step 6: Enter the file name and then select Verilog module

Step 7: Define the input and output port names, then click Next for all successive windows
104

Step 8: The Verilog file will be created under ISE file

Step 9: Double click the Verilog file and enter the logic details and save the file.
105

Step 10: Double click Synthesize XST for checking the syntax .

Step 11: Right click the half add.v file and select new source, then click implementation constraints file and enter the file name.
106

Step

12:.ucf

file

will

be

created

Step 13: open the .ucf file and enter the pin location and save the file

107

Step14: Goto Generate programming file and select Generate PROM,ACE or JTAG file in the processes window.

Step 15: In Slave Serial mode ,right click and select Add Xilinx Device

108

Step 16: In the Add Device window select the .bit file to add the device.

109

Step 17: Connect the RS232 cable between computer and kit. Connect the SMPS to kit and switch on the kit. Step 18: Right click the device and select Program to transfer the file to kit.

Step 19: after sucecessful transmission of the programming succeeded will be displayed

110

PROGRAM: HALF ADDER DESIGN IN VERILOG

// *** Half Adder module my_halfadrvlog (s,c,x,y); output s,c; input x,y; xor (s,x,y); and (c,x,y); endmodule // *** Full Adder *** // module my_fuladrvlog (s,c,x,y,z); output s,c; input x,y,z; xor (s,x,y,z); assign c = ((x & y) | (y & z) | (z & x)); endmodule *** //

PROGRAM: FULL ADDER DESIGN IN VERILOG

1 TO 4 DE-MULTIPLEXER DESIGN IN VERILOG

module my_1to4demuxgatevlog(y,i,en,s); output [0 :3] y; input i,en; input [0 : 1] s; and (y[0],~en,~s[1],~s[0],i); and (y[1],~en,~s[1],s[0],i); and (y[2],~en,s[1],~s[0],i); and (y[3],~en,s[1],s[0],i); endmodule

RESULT:Thus the development tool for FPGA for schematic entry and verilog was studied

111

EX NO: 11 DESIGN AND SIMULATION OF PIPELINED SERIAL AND PARALLEL ADDER TO ADD/SUBTRACT 8 NUMBER OF SIZE,12 BITS EACH IN 2S COMPLEMENT SERIAL ADDER: AIM: To design, synthesize, simulate pipelined serial and parallel adder to add 8 numbers of 12bit size each in 2s complement and to implement and program the same in FPGA. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i HARDWARE: XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card - I THEORY: SERIAL ADDER: Serial Adder uses a simple adder and constructs the sum sequentially. At a time t, the Sun is calculated and the carry is stored in a register. At time t+1, the sum uses carry[t] to calculate a new sum. Carry [ t + 1] = A [ t +1].B[ t + 1 ] . ( A [ t + 1 ] + B [ t + 1 ] ) Sum [ t + 1 ] = Carry [ t + 1 ] . ( A [ t + 1 ] + B [ t + 1 ] + c [ t ] ) +A[t+1].B[t+1].c[t] The two inputs to the adder are stored in a n-bit register. Sum bit is stored in a n-bit register. Addition is commenced by clearing the carry register. Then the operands are serially applied to the inputs of the adder. The sum and carry array are advantageous because these delays determine the fastest clock frequency at which the adder can operate. Bit serial architecture has been used widely for a variety of signal processing applications, especially with technologies in the 2-5 micro range. Reasons for using bit serial architecture include reduced signal routing, reduced module sizes and higher speed operation.

112

PARALLEL ADDER: An n-bit parallel adder may be constructed by cascading n 1-bit adders. This is called Ripple Carry Adder. The inputs are n bit A and B values. The carry signal of stage i is fed to the C signal of the stage i+1 and the sum signal forms the n bit output. The nth bit of the sum indicates whether overflow has occurred. Because the carry output signal is used in the generation of the sum, the sum will be delayed with respect to the carry. In case of n-bit parallel adder, the carry delay has to be minimized because the delay associated the adder is Tn = nTc Where Tn is the Total Add Time, n is the number of stages and Tc is the delay of one carry stage. To optimize the Carry delay, the inverter at the output of the carry gate can be omitted. In this case, every other stage operates on complement data. PROGRAM: Verilog code for serial adder
module serial_adder(clk,addr,load,clear,data_in,calc,result); input clk,clear,calc,load; input [2:0]addr; input [11:0]data_in; output reg [11:0]result; reg [11:0]ram[7:0]; reg [6:0]temp; always@(negedge clk) begin if(clk) temp[0] = ram[0] + ram[1]; temp[1] = (temp[0] + ram[2]); temp[2] = (temp[1] + ram[3]); temp[3] = (temp[2] + ram[4]); temp[4] = (temp[3] + ram[5]); temp[5] = (temp[4] + ram[6]); temp[6] = (temp[5] + ram[7]); end always@(posedge clk) begin if(~clear) begin ram[0]=12'b0; ram[1]=12'b0; ram[2]=12'b0; ram[3]=12'b0; ram[4]=12'b0; ram[5]=12'b0; ram[6]=12'b0; ram[7]=12'b0; 113

end else if(~load) begin result=data_in; ram[addr] = data_in; end else if(~calc) result = temp; else result = ram[addr]; end endmodule

Verilog code for parallel adder

module parallel_adder(clk,addr,load,clear,data_in,calc,result); input clk,clear,calc,load; input [2:0]addr; input [11:0]data_in; output reg [11:0]result; reg [11:0]ram[7:0]; wire [11:0]temp; always@(posedge clk) begin if(~clear) begin ram[0]=12'b0; ram[1]=12'b0; ram[2]=12'b0; ram[3]=12'b0; ram[4]=12'b0; ram[5]=12'b0; ram[6]=12'b0; ram[7]=12'b0; end else if(~load) ram[addr]=data_in; end assign temp=ram[0]+ram[1]+ram[2]+ram[3]+ram[4]+ram[5]+ram[6]+ram[7]; always@(posedge clk) begin if(~load) result=data_in; else if(~calc) result=temp; else result=ram[addr]; end endmodule 114

UCF file (User constraint file)

NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "addr<0>" LOC = "p80" ; "addr<1>" LOC = "p82" ; "addr<2>" LOC = "p78" ; "calc" LOC = "p130" ; "clear" LOC = "p137" ; "clk" LOC = "p52" ; "data_in<0>" LOC = "p92" ; "data_in<10>" LOC = "p89" ; "data_in<11>" LOC = "p90" ; "data_in<1>" LOC = "p96" ; "data_in<2>" LOC = "p74" ; "data_in<3>" LOC = "p76" ; "data_in<4>" LOC = "p77" ; "data_in<5>" LOC = "p79" ; "data_in<6>" LOC = "p84" ; "data_in<7>" LOC = "p85" ; "data_in<8>" LOC = "p86" ; "data_in<9>" LOC = "p87" ; "load" LOC = "p83" ; "result<7>" LOC = "p28" ; "result<10>" LOC = "p63" ; "result<11>" LOC = "p69" ; "result<6>" LOC = "p31" ; "result<5>" LOC = "p33" ; "result<4>" LOC = "p44" ; "result<3>" LOC = "p46" ; "result<2>" LOC = "p47" ; "result<1>" LOC = "p50" ; "result<0>" LOC = "p51" ; "result<8>" LOC = "p57" ; "result<9>" LOC = "p59" ;

PROCEDURE: Software part 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code, check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 3. Perform the functional simulation using ModelSim XE Verilog simulator. 4. Open a new UCF file and lock the pins of the design with FPGA I/O pins. 5. Implement the design by double clicking on the implementation tool selection. 6. Create programming file (i.e., bit file) for downloading into the device.

115

Hardware part Connect the power supply cable to the FPGA kit using power supply adapter. Connect the FPGA kit to the parallel port of the PC through the cable provided along with the kit. Connect FRC1 of main board to CN8 of AU card - I using FRC cable. Connect FRC2 of main board to CN7 of AU card - I using FRC cable. Connect FRC7 of main board to CN6 of AU card - I using FRC cable. Connect FRC6 of main board to CN5 of AU card - I using FRC cable. Connect FRC4 of main board to CN4 of AU card - I using FRC cable. Connect FRC5 of main board to CN1 of AU card - I using FRC cable. Working 1. Download the program into the FPGA and connect the FRC connectors as specified. 2. On AU card I, load the 12 bit data by using the specified switches (SW0-SW11) and selection of 8 numbers are made one by one by selecting the assigned lines A0, A1 and A2. 3. After selecting each 12 bit numbers by pressing the LOAD switch, the values are assigned to concerned memory locations. 4. After loading all values, keep pressing CALC switch in AU card I for verifying the result in LEDs on card I. SYNTHESIS REPORT: (FOR SERIAL ADDER) Device Utilization Summary (estimated values) Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs Used 142 120 221 31 1 Available 3584 7168 7168 97 8 Utilization 3% 1% 3% 31% 12%

116

RTL Schematic Representation Top Level

SIMULATION REPORT: (Using ModelSim)

117

SYNTHESIS REPORT: (FOR PARALLEL ADDER) Device Utilization Summary (estimated values) Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs Used 115 108 202 31 1 Available 3584 7168 7168 97 8 Utilization 3% 1% 2% 31% 12%

RTL Schematic Representation Top Level

118

SIMULATION REPORT: (Using ModelSim)

OBSERVATION: Location 000 001 010 011 12-bit Input Data 0000 0000 0000 0000 0000 0001 0000 0000 0010 0000 0000 0011 Location 100 101 110 111 12-bit Input Data 0000 0000 0100 0000 0000 0101 0000 0000 0110 0000 0000 0111

Result = 0000 0001 1100

RESULT:

Thus the serial adder and parallel adder were designed using Verilog HDL for 8 datas, each of 12 bit size and it was simulated, synthesized, implemented and programmed in the FPGA device.

119

EX. NO: 12

STUDY OF PLACE AND ROOT AND BACK ANNOTATION FOR FPGAS.

AIM: To study the Place and Root and Back annotation for FPGAs. THEORY: After implementation is complete, you can verify your design before downloading it to a device. VIEWING PLACEMENT: In this section, you will use the Floor planner to verify your pin outs and placement. Floor planner is also very useful for creating area groups for designs. 1. Select the counter source file in the Sources in Project window. 2. Click the + sign to expand the Place & Route group of processes. 3. Double-click the View/Edit Placed Design (Floorplanner) process. The Floorplanner view opens. 4. Select View _ Zoom _ ToBox and then use the mouse to draw a box around the counter instance, shown in green on the right side of the chip. 5. This Fig 1 shows where the entire design was placed. Click on any of the components listed in the Design Hierarchy window to see where each component is placed. 6. Zoom in to the right side of the chip even more, and place your mouse over the K13pad. You can see that your pinout constraint was applied - the DIRECTION pin is placed at K13. 7. Close the Floorplanner without saving. VIEWING RESOURCE UTILIZATION IN REPORTS: Many ISE processes produce summary reports which enable you to check information about your design after each process is run. Detailed reports are available from the Processes for Source window. You can also view summary information and access most often-utilized reports in the Design Summary. 1. Click on the Design Summary tab at the bottom of the window. If you closed the summary during this tutorial, you can reopen it by double-clicking the View Design Summary process.

120

FIGURE 3: TIMING ANALYZER - TIMING SUMMARY

FIGURE 4: FPGA EDITOR - DETAILED VIEW 2. In the Device Utilization Summary section, observe the number of Slice Flip Flops that were used during implementation. You should see 4 flip flops, since you implemented a 4-bit counter. 3. To see other reports, scroll to the bottom of the Design Summary. You can click on a report from here to view it in the ISE Text Editor. TIMING CLOSURE: In this section, you will run timing analysis on your design to verify that your timing constraints were met. Timing closure is the process of working on your design to ensure that it meets your necessary timing requirements. ISE provides several tools to assist with timing closure.

121

1. In the Processes for Source window, under the Place & Route group of processes, expand the Generate Post-Place & Route Static Timing group by clicking the +sign. 2. Double-click the Analyze Post-Place & Route Static Timing process. The Timing Analyzer opens. 3. To analyze the design, select Analyze Against Timing Constraints. The Analyze with Timing Constraints dialog box opens. 4. Click OK. When analysis is complete, the timing report opens. 5. Select Timing summary from the Timing Report Description tree in the left window. This displays the summary section of the timing report, where you can see that no timing errors were reported. 6. Close the Timing Analyzer without saving. VIEWING THE PLACED AND ROUTED DESIGN: In this section, you will use the FPGA Editor to view the design. You can view your design on the FPGA device, as well as edit the placement and routing with the FPGA Editor. 1. Double-click the View/Edit Routed Design (FPGA Editor) process found in the Place & Route group of processes. Your implemented design opens in the FPGA Editor. 2. Look in the List window to examine your design components. 3. Click on the COUNT_OUT K12 IOB in the List window to select the row. This is one of the outputs in your design. 4. With the COUNT_OUT K12 row selected, select View _ Zoom Selection. In the editor window, you can see the COUNT_OUT<0> IOB highlighted in red. 5. Push into (double-click) the red-highlighted COUNT_OUT K12 IOB. You should see Fig 4. 6. Enlarge the window and zoom in so you can see more detail. This view shows the inside of an FPGA at the lowest viewable level. The blue line shows the route that is used through the IOB. The red lines show the routes that are available.

122

FIGURE 5: SIMULATOR PROCESSES FOR TEST BENCH

FIGURE 6: TIMING SIMULATION IN ISE SIMULATOR 7. Verify that the signal goes to the pad as an output. 8. Close the FPGA Editor. TIMING SIMULATION (ISE SIMULATOR): You can verify that your design meets your timing requirements by running a timing simulation. You can use the same test bench waveform that was used earlier in the design flow for behavioral simulation. When running timing simulation, the ISE tools create a structural HDL file which includes timing information available after Place and Route is run. The simulator will run on a model that is created based on the design to be downloaded to the FPGA.
123

If you are using ISE Base or Foundation, you can simulate your design with the ISE Simulator. To simulate your design with ModelSim, skip to the Timing Simulation (ModelSim) section. To run the integrated simulation processes: 1. Select the test bench waveform in the Sources in Project window. You can see the ISE Simulator processes in the Processes for Source window. 2. Double-click the Simulate Post-Place & Route Model process. This process generates a timing-annotated netlist from the implemented design and simulates it. The resulting simulation is displayed in the Waveform Viewer. These results look different than those you saw in the behavioral simulation earlier in this tutorial. These results show timing delays. 3. To see your simulation results, zoom in on the transitions and view the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port. 4. Zoom in again to see the timing delay between a rising clock edge and an output transition. 5. Click the Measure Marker button and then click near the 300 ns mark. Drag the second marker to the point where the output becomes stable to see the time delay between the clock edge and the transition. 6. Close the waveform view window.You have completed timing simulation of your design using the ISE Simulator. Skip past the ModelSim section below, and proceed to the Creating Configuration Data section. TIMING SIMULATION (MODELSIM): If you have a ModelSim simulator installed, you can simulate your design using theintegrated ModelSim flow. You can run processes from within ISE which launches the installed ModelSim simulator. 1. To run the integrated simulation processes, select the test bench in the Sources in Project window. You can see the ModelSim Simulator processes in the Processes for Source window.

124

FIGURE 7: SIMULATOR PROCESSES FOR TEST BENCH

FIGURE 8: TIMING SIMULATION IN MODELSIM 2. Double-click the Simulate Post-Place & Route VHDL/Verilog Model process.

125

3. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port. 4. Zoom in on the rising clock edges to see that the output transitions occur slightly later due to the timing delay. 5. Close the ModelSim window.

RESULT: Thus Back annotation for FPGAs was studied.

126

EX.13 DESIGN AND SIMULATION OF BACKANNOTATED VERILOG FILES FOR MULTIPLYING TWO SIGNED 8 BIT NUMBERS IN 2S COMPLEMENT AIM: To design, synthesize, simulate pipelined multiplier to multiply two 8 bit signed numbers in 2s complement and to implement and program the same in FPGA. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i HARDWARE: XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card - I THEORY: MULTIPLIER: In many digital signal processing applications such as correlations, convolutions, filtering and frequency analysis, one needs to perform multiplication. Multiplication algorithms will be used to illustrate methods of designing different cells so they fit into a larger structure. In order to introduce these designs, simple serial and parallel multipliers will be introduced. The appropriate tests should be consulted for more definite system architecture. The most basic form of multiplication consists of forming the products of two positive binary numbers. This may be accomplished through the traditional technique of Successive Addition and shifts in which each additive is conditional on one of the multiplier bits. The multiplication process may be viewed to consist of the following steps: 1. Evaluation of Partial Products, 2. Accumulation of the shifted partial products It should be noted that binary multiplication is equal to partial AND operations. Thus evaluation of partial products consists of the logical AND of the Multiplicand and the relevant Multiplier bit. Each column of partial products must then be added and if necessary any carry values is passed to the next column. There are a number of techniques that may be used to perform multiplication. In general the choice is based on the factors such as speed, throughput, numerical accuracy and area. As a rule, multiplication may be classified by the format, in which the words are accessed namely, 1. Serial Form 2. Serial / Parallel Form 3. Parallel Form
127

PROGRAM: Verilog code for multiplier

module multiplier(clk,addr,load,clear,data_in,calc,result); input clk,clear,calc,load; input addr; input [7:0]data_in; output reg [15:0]result; reg [7:0]ram[1:0]; always@(posedge clk) begin if(~clear) begin ram[0]=8'b0; ram[1]=8'b0; end else if(~load) ram[addr]=data_in; end always@(posedge clk) begin if(~load) result={8'b0,data_in}; else if(~calc) result= multiply_8x8_2sC (ram[0],ram[1]); else result={8'b0,ram[addr]}; end function[15:0] multiply_8x8_2sC; input[7:0] a,b; reg[7:0] a_mag,b_mag; reg[14:0] y_mag; reg[14:0] y_neg; begin case (a[7]) 0: a_mag = a[6:0]; 1: a_mag = 128 - a[6:0]; // max(a_mag) = 128, thus 8 bits endcase case (b[7]) 0: b_mag = b[6:0]; 1: b_mag = 128 - b[6:0]; endcase y_mag = a_mag * b_mag; // max(y_mag) = 16384, thus 15 bits if ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zero begin // y_mag >=1, <= 16256, thus need only 14 bits y_neg = 32768 - y_mag[13:0]; // max(y_neg) = 32767, thus need 15 bits multiply_8x8_2sC = {1'b1,y_neg}; end 128

else multiply_8x8_2sC = y_mag; end endfunction endmodule

UCF file(User constraint file)

NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "addr" LOC = "p80" ; "calc" LOC = "p130" ; "clear" LOC = "p137" ; "clk" LOC = "p52" ; "data_in<0>" LOC = "p92" ; "data_in<1>" LOC = "p96" ; "data_in<2>" LOC = "p74" ; "data_in<3>" LOC = "p76" ; "data_in<4>" LOC = "p77" ; "data_in<5>" LOC = "p79" ; "data_in<6>" LOC = "p84" ; "data_in<7>" LOC = "p85" ; "load" LOC = "p83" ; "result<0>" LOC = "p51" ; "result<10>" LOC = "p63" ; "result<11>" LOC = "p69" ; "result<12>" LOC = "p68" ; "result<13>" LOC = "p73" ; "result<14>" LOC = "p70" ; "result<15>" LOC = "p20" ; "result<1>" LOC = "p50" ; "result<2>" LOC = "p47" ; "result<3>" LOC = "p46" ; "result<4>" LOC = "p44" ; "result<5>" LOC = "p33" ; "result<6>" LOC = "p31" ; "result<7>" LOC = "p28" ; "result<8>" LOC = "p57" ; "result<9>" LOC = "p59" ;

PROCEDURE: Software part 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code, check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window.
129

3. Perform the functional simulation using ModelSim - XE Verilog simulator. 4. Open a new UCF file and lock the pins of the design with FPGA I/O pins. 5. Implement the design by double clicking on the implementation tool selection. 6. Create programming file (i.e., bit file) for downloading into the device. Hardware part Connect the power supply cable to the FPGA kit using power supply adapter. Connect the FPGA kit to the parallel port of the PC through the cable provided along with the kit. Connect FRC1 of main board to CN8 of AU card - I using FRC cable. Connect FRC2 of main board to CN7 of AU card - I using FRC cable. Connect FRC7 of main board to CN6 of AU card - I using FRC cable. Connect FRC6 of main board to CN5 of AU card - I using FRC cable. Connect FRC4 of main board to CN4 of AU card - I using FRC cable. Connect FRC5 of main board to CN1 of AU card - I using FRC cable. Working 1. Download the program into the FPGA and connect the FRC connectors as specified. 2. On AU card I, load two 8 - bit data by using the specified switches (SW0SW7) in address location 0 and 1. 3. By pressing the LOAD switch in AU card - I, the two values are assigned to concerned memory locations. 4. After loading all values, keep pressing CALC switch in AU card I for verifying the result in LEDs on card I. SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of 18X18s Number of GCLKs Used 50 32 95 29 1 1 Available 3584 7168 7168 97 16 8 Utilization 1% 0% 1% 29% 6% 12%

130

RTL Schematic Representation Top Level

SIMULATION REPORT: (Using ModelSim)

OBSERVATION: Location 0 1 8-bit Input Data 0000 0001 1000 0001 1111 1111 1000 0001 16-bit Result

RESULT: Thus the 8 bit multiplier was designed using Verilog HDL and it was simulated, synthesized, implemented and programmed in the FPGA device.

131

EX. 14 FPGA AIM:

DESIGN AND TESTING ONBOARD SWITCHES AND LEDS IN

To simulate and test onboard switches and LEDs using Verilog code and to implement the same in FPGA. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i HARDWARE: XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, GPIO card - II ALGORITHM: 1. 2. 3. 4. Start the program. Declare the input and output variables. Declare the output as register data type. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. THEORY: TESTING ON BOARD LEDS AND SWITCHES: XC3S400 is an array of Configurable Logic Blocks (CLBs) and is embedded within a set of horizontal and vertical channels that contain Routing that can be personalized to interconnect CLBs. The configuration of the interconnect is achieved by turning ON n channel pass transistors. The state that determines a given interconnect pattern is held in the Static RAM cells distributed across the chip close to the controlled elements. The CLBs and routing channels are surrounded by a set of programmable Inputs / Outputs. PROGRAM: Verilog Code for Testing Onboard Switches and LEDs in FPGA
module buffer(a, y); input [7:0] a; 132

output [7:0] y; reg [7:0]y; always@(a) begin y=a; end endmodule

UCF file(User constraint file)

NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "a[0]" LOC = "p83" ; "a[1]" LOC = "p80" ; "a[2]" LOC = "p82" ; "a[3]" LOC = "p78" ; "a[4]" LOC = "p79" ; "a[5]" LOC = "p77" ; "a[6]" LOC = "p76" ; "a[7]" LOC = "p74" ; "y[0]" LOC = "p96" ; "y[1]" LOC = "p92" ; "y[2]" LOC = "p90" ; "y[3]" LOC = "p89" ; "y[4]" LOC = "p87" ; "y[5]" LOC = "p86" ; "y[6]" LOC = "p85" ; "y[7]" LOC = "p84" ;

PROCEDURE: Software part 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. 3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 4. Perform the functional simulation using Xilinx ISE simulator. 5. Open a new UCF file and lock the pins of the design with FPGA I/O pins. 6. Implement the design by double clicking on the implementation tool selection. 7. Create programming file (i.e., bit file) for downloading into the specified device. Hardware part 1. Connect the power supply cable to the FPGA kit using power supply adapter. 2. Connect FPGA board to parallel port of PC using parallel port cable. 3. Connect FRC1 of FPGA board with the switches (i/ps) of GPIO card - II using FRC cable. 4. Connect FRC2 of FPGA board with the LEDs (o/ps) of GPIO card - II using FRC cable.

133

SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Number of Slices Number of bonded IOBs Used 0 16 Available 3584 97 Utilization 0% 16%

RTL Schematic Representation

SIMULATION REPORT:

RESULT:

Thus the onboard switches and LEDs were designed using Verilog HDL and it was simulated and tested in the FPGA device.

134

EX.15 FPGA AIM:

DESIGN AND IMPLEMENTATION OF REAL TIME CLOCK IN

To design a Real Time Clock (2 digits, 7 segment LED displays each for Hours, Minutes and Seconds) and demonstrate its working on the FPGA Board. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i HARDWARE: XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card - I PROGRAM: Verilog Code for Real Time Clock
module real_time_clk_verilog (clk,clear,hour1,hour2,minute1,minute2,second1, second2, hour_A2, min_A1, sec_A0, load, data_in); input clk,clear; output reg [6:0]hour1,hour2,minute1,minute2,second1,second2; input load; input hour_A2,min_A1,sec_A0; input [7:0]data_in; reg clk_sec,clk_msec; reg [7:0]sec,min,hr; integer timer_count1=0,timer_count2=0; always@(posedge clk) begin if(timer_count1==3999) begin timer_count1=0; clk_msec=1'b1; end else begin timer_count1=timer_count1+1; clk_msec=1'b0; end end always@(posedge clk_msec) begin if(timer_count2==999) 135

begin timer_count2=0; clk_sec=1'b1; end else begin timer_count2=timer_count2+1; clk_sec=1'b0; end end always@(negedge clk_sec) begin if(~clear) begin sec=0; min=0; hr=0; end else if(~load) begin if(hour_A2) begin if(hr[7:4] == 4'b0010) begin if(hr[3:0] < 4'b0100) hr = data_in; end else if(hr[7:4] < 4'b0010) hr = data_in; else hr = 8'b0; end if(min_A1) begin if(min[7:4] < 4'b0110) min = data_in; else min = 8'b0; end if(sec_A0) begin if (sec[7:4] < 4'b0110) sec = data_in; else sec = 8'b0; end end else begin 136

if(sec[3:0]==4'b1001) begin sec[3:0]=4'b0; if(sec[7:4]==4'b0101) begin sec[7:4]=4'b0; if(min[3:0]==4'b1001) begin min[3:0]=4'b0; if(min[7:4]==4'b0101) begin min[7:4]=4'b0; if(hr==8'b00100011) hr=0; else if(hr[3:0]==4'b1001) begin hr[3:0]=4'b0; hr[7:4]=hr[7:4]+1; end else hr[3:0]=hr[3:0]+1; //hours count completed end else min[7:4]=min[7:4]+1; end else min[3:0]=min[3:0]+1; // minutes count completed end else sec[7:4]=sec[7:4]+1; end else sec[3:0]=sec[3:0]+1; //seconds count completed end end always@(sec) begin case (sec[3:0]) 4'b0000: second1=7'b1111110; 4'b0001: second1=7'b0110000; 4'b0010: second1=7'b1101101; 4'b0011: second1=7'b1111001; 4'b0100: second1=7'b0110011; 4'b0101: second1=7'b1011011; 4'b0110: second1=7'b1011111; 4'b0111: second1=7'b1110000; 4'b1000: second1=7'b1111111; 4'b1001: second1=7'b1111011; default: second1=7'b0; 137

endcase end always@(sec) begin case(sec[7:4]) 4'b0000: second2=7'b1111110; 4'b0001: second2=7'b0110000; 4'b0010: second2=7'b1101101; 4'b0011: second2=7'b1111001; 4'b0100: second2=7'b0110011; 4'b0101: second2=7'b1011011; 4'b0110: second2=7'b1011111; 4'b0111: second2=7'b1110000; 4'b1000: second2=7'b1111111; 4'b1001: second2=7'b1111011; default: second2=7'b0; endcase end always@(min) begin case(min[3:0]) 4'b0000: minute1=7'b1111110; 4'b0001: minute1=7'b0110000; 4'b0010: minute1=7'b1101101; 4'b0011: minute1=7'b1111001; 4'b0100: minute1=7'b0110011; 4'b0101: minute1=7'b1011011; 4'b0110: minute1=7'b1011111; 4'b0111: minute1=7'b1110000; 4'b1000: minute1=7'b1111111; 4'b1001: minute1=7'b1111011; default: minute1=7'b0; endcase end always@(min) begin case(min[7:4]) 4'b0000: minute2=7'b1111110; 4'b0001: minute2=7'b0110000; 4'b0010: minute2=7'b1101101; 4'b0011: minute2=7'b1111001; 4'b0100: minute2=7'b0110011; 4'b0101: minute2=7'b1011011; 4'b0110: minute2=7'b1011111; 4'b0111: minute2=7'b1110000; 4'b1000: minute2=7'b1111111; 4'b1001: minute2=7'b1111011; default: minute2=7'b0; endcase 138

end always@(hr) begin case(hr[3:0]) 4'b0000: hour1=7'b1111110; 4'b0001: hour1=7'b0110000; 4'b0010: hour1=7'b1101101; 4'b0011: hour1=7'b1111001; 4'b0100: hour1=7'b0110011; 4'b0101: hour1=7'b1011011; 4'b0110: hour1=7'b1011111; 4'b0111: hour1=7'b1110000; 4'b1000: hour1=7'b1111111; 4'b1001: hour1=7'b1111011; default: hour1=7'b1111110; endcase end always@(hr) begin case(hr[7:4]) 4'b0000: hour2=7'b1111110; 4'b0001: hour2=7'b0110000; 4'b0010: hour2=7'b1101101; default: hour2=7'b1111110; endcase end end module

UCF File(User Constraint File)

NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "clear" LOC = "p137" ; "clk" LOC = "p52" ; "data_in<0>" LOC = "p92" ; "data_in<1>" LOC = "p96" ; "data_in<2>" LOC = "p74" ; "data_in<3>" LOC = "p76" ; "data_in<4>" LOC = "p77" ; "data_in<5>" LOC = "p79" ; "data_in<6>" LOC = "p84" ; "data_in<7>" LOC = "p85" ; "hour1<0>" LOC = "p95" ; "hour1<1>" LOC = "p97" ; "hour1<2>" LOC = "p98" ; "hour1<3>" LOC = "p99" ; "hour1<4>" LOC = "p104" ; "hour1<5>" LOC = "p125" ; "hour1<6>" LOC = "p122" ; "hour2<0>" LOC = "p112" ; "hour2<1>" LOC = "p116" ; "hour2<2>" LOC = "p119" ; "hour2<3>" LOC = "p118" ; "hour2<4>" LOC = "p123" ; "hour2<5>" LOC = "p131" ; NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET "minute1<1>" LOC = "p15" ; "minute1<2>" LOC = "p17" ; "minute1<3>" LOC = "p18" ; "minute1<4>" LOC = "p21" ; "minute1<5>" LOC = "p23" ; "minute1<6>" LOC = "p24" ; "minute2<0>" LOC = "p129" ; "minute2<1>" LOC = "p132" ; "minute2<2>" LOC = "p135" ; "minute2<3>" LOC = "p140" ; "minute2<4>" LOC = "p1" ; "minute2<5>" LOC = "p12" ; "minute2<6>" LOC = "p13" ; "sec_A0" LOC = "p80" ; "second1<0>" LOC = "p32" ; "second1<1>" LOC = "p35" ; "second1<2>" LOC = "p36" ; "second1<3>" LOC = "p40" ; "second1<4>" LOC = "p41" ; "second1<5>" LOC = "p56" ; "second1<6>" LOC = "p60" ; "second2<0>" LOC = "p26" ; "second2<1>" LOC = "p27" ;

139

NET NET NET NET NET

"hour2<6>" LOC = "p93" ; "hour_A2" LOC = "p78" ; "load" LOC = "p83" ; "min_A1" LOC = "p82" ; "minute1<0>" LOC = "p14" ;

NET NET NET NET NET

"second2<2>" LOC = "second2<3>" LOC = "second2<4>" LOC = "second2<5>" LOC = "second2<6>" LOC =

"p6" ; "p7" ; "p8" ; "p11" ; "p10" ;

PROCEDURE: Software part 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code, check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 3. Open a new UCF file and lock the pins of the design with FPGA I/O pins. 4. Implement the design by double clicking on the implementation tool selection. 5. Create programming file (i.e., bit file) for downloading into the device. Hardtware part Connect the power supply cable to the FPGA kit using power supply adapter. Connect the FPGA kit to the parallel port of the PC through the cable provided along with the kit. Connect FRC1 of main board to CN8 of AU card - I using FRC cable. Connect FRC2 of main board to CN7 of AU card - I using FRC cable. Connect FRC7 of main board to CN6 of AU card - I using FRC cable. Connect FRC10 of main board to CN1 of AU card - I using FRC cable. Connect FRC5 of main board to CN2 of AU card - I using FRC cable. Connect FRC8 of main board to CN3 of AU card - I using FRC cable. Working: Connections are made as above and implement the design into the FPGA device and the REAL TIME clock is ON, all 7 segments displays will be in ON position and starts counting, the time can be set by the switches SW0 SW7 using A2, A1, A0 switches in card - I and the RESET pin RESETS the clock.

140

SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs Used 98 90 189 56 3 Available 3584 7168 7168 97 8 Utilization 2% 1% 2% 57% 37%

RTL Schematic Representation Top Level

RESULT:

Thus the real time clock was designed using verilog code and its working was demonstrated in FPGA board.

141

EX.NO.16 FPGA AIM:

IMPLEMENTATION OF TRAFFIC LIGHT CONTROLLER IN

To design a Traffic Light Controller using Verilog code and to test its working on the FPGA Board. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i HARDWARE: XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel port cable, FRC connector, AU card - II PROGRAM: Verilog Code for Traffic Light Controller
module traffic_verilog(seg_1,seg_2,R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG,clk,rst); output reg R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG; output reg [6:0]seg_1,seg_2; input clk,rst; integer timer_count1 = 0,timer_count2 = 0; reg clk_msec,clk_sec; reg [7:0]count; reg [1:0]state = 2'b0; always@(posedge clk) begin if(timer_count1==3999) begin timer_count1=0; clk_msec=1'b1; end else begin timer_count1=timer_count1+1; clk_msec=1'b0; end end always@(posedge clk_msec) begin if(timer_count2==999) begin timer_count2=0; 142

clk_sec=1'b1; end else begin timer_count2=timer_count2+1; clk_sec=1'b0; end end always@(posedge clk_sec) begin if(~rst) begin R1 = 1'b1; G1 = 1'b0; Y1 = 1'b0; R2 = 1'b1; G2 = 1'b0; Y2 = 1'b0; R3 = 1'b1; G3 = 1'b0; Y3 = 1'b0; state=2'b00; end else begin case(state) 2'b00://SIGNAL AT SIGNAL LIGHTS ONE begin if(count==8'b00100101) begin G1 = 1'b0; R1 = 1'b0; Y1 = 1'b1; R3 = 1'b0; Y3 = 1'b0; G3 = 1'b0; end if(count==8'b00101001) begin G1 = 1'b1; Y1 = 1'b0; R3 = 1'b1; state=2'b01; end else state=2'b00; end 2'b01://SIGNAL AT SIGNAL LIGHTS TWO begin if(count==8'b00100101) begin Y1 = 1'b1; G1 = 1'b0; R3 = 1'b1; R2 = 1'b0; 143

end if(count==8'b00101001) begin

Y2 = 1'b1; G2 = 1'b0;

R1 = 1'b1; Y1 = 1'b0; Y2 = 1'b0; G2 = 1'b1; state = 2'b10; end else state=2'b01; end 2'b10://SIGNAL AT SIGNAL LIGHTS THREE begin if(count==8'b00100101) begin Y2 = 1'b1; G2 = 1'b0; R3 = 1'b0; Y3 = 1'b1; G3 = 1'b0; end if(count==8'b00101001) begin R2 = 1'b1; Y2 = 1'b0; Y3 = 1'b0; G3 = 1'b1; state = 2'b11; end else state=2'b10; end 2'b11://ALL SIGNAL HIGH TO ALLOW PEDESTRIALS TO CROSS begin if(count==8'b00100101) begin Y1= 1'b0; Y3 = 1'b1; G3 = 1'b0; end if(count==8'b00101001) begin Y1 =1'b0; R3 = 1'b1; Y3 = 1'b0; state = 2'b00; end 144

else state=2'b11; end endcase end end always@(count,state) begin if((state==2'b00)&&(count<=8'b00101001)) begin PR = 1'b1; PG = 1'b0; end else begin PR = 1'b0; PG = 1'b1; end end always@(posedge clk_sec) begin if(rst==1'b0) count=8'b00000000; else if(clk_sec) begin if(count[3:0]==4'b1001) begin count[3:0]=4'b0000; if(count[7:4]==4'b0010) count[7:4]=4'b0000; else else end end end count[3:0]=count[3:0]+1; count[7:4]=count[7:4]+1;

always@(count) begin case(count[3:0]) 4'b0000:seg_1 = 8'b1111110; //0 4'b0001:seg_1 = 8'b0110000; 4'b0010:seg_1 = 8'b1101101; 4'b0011:seg_1 = 8'b1111001; 4'b0100:seg_1 = 8'b0110011; 4'b0101:seg_1 = 8'b1011011; 4'b0110:seg_1 = 8'b1011111; 4'b0111:seg_1 = 8'b1110000; 145

//1 //2 //3 //4 //5 //6 //7

end endmodule NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET

4'b1000:seg_1 = 8'b1111111; //8 4'b1001:seg_1 = 8'b1111011; //9 default:seg_1 = 8'b0000000; //off endcase case(count[7:4]) 4'b0000:seg_2 = 8'b1111110; //0 4'b0001:seg_2 = 8'b0110000; //1 4'b0010:seg_2 = 8'b1101101; //2 4'b0011:seg_2 = 8'b1111001; //3 4'b0100:seg_2 = 8'b0110011; //4 4'b0101:seg_2 = 8'b1011011; //5 4'b0110:seg_2 = 8'b1011111; //6 4'b0111:seg_2 = 8'b1110000; //7 4'b1000:seg_2 = 8'b1111111; //8 4'b1001:seg_2 = 8'b1111011; //9 default:seg_2 = 8'b0000000; //off endcase

UCF file (User Constraint File)

"clk" LOC = "p52" ; "G1" LOC = "p97" ; "G2" LOC = "p98" ; "G3" LOC = "p125" ; "PG" LOC = "p132" ; "PR" LOC = "p135" ; "R1" LOC = "p93" ; "R2" LOC = "p104" ; "R3" LOC = "p129" ; "rst" LOC = "p78" ; "seg_1<6>" LOC = "p27" "seg_1<5>" LOC = "p26" "seg_1<4>" LOC = "p24" "seg_1<3>" LOC = "p23" "seg_1<2>" LOC = "p21" "seg_1<1>" LOC = "p18" "seg_1<0>" LOC = "p17" "seg_2<6>" LOC = "p15" "seg_2<5>" LOC = "p14" "seg_2<4>" LOC = "p13" "seg_2<3>" LOC = "p12" "seg_2<2>" LOC = "p1" ; "seg_2<1>" LOC = "p83" "seg_2<0>" LOC = "p80" "Y1" LOC = "p95" ; "Y2" LOC = "p99" ; "Y3" LOC = "p122" ;

; ; ; ; ; ; ; ; ; ; ; ; ;

146

PROCEDURE: Software part 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code, check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 3. Open a new UCF file and lock the pins of the design with FPGA I/O pins. 4. Implement the design by double clicking on the implementation tool selection. 5. Create programming file (i.e., bit file) for downloading into the device.

Hardware part Connect the power supply cable to the FPGA kit using power supply adapter. Connect the FPGA kit to the parallel port of the PC through the cable provided along with the kit. Connect FRC1 of main board to CN2 of AU card - II using FRC cable. Connect FRC8 of main board to CN3 of AU card - II using FRC cable. Connect FRC5 of main board to CN1 of AU card - II using FRC cable. Working: 1. Connections are made as above and implement the design into the FPGA device and the Traffic Light Controller (AU card II) will be ON. 2. Initially, the Pedestrians on all the three signals will be in GREEN for 30 seconds to allow the Pedestrians to pass through. 3. After 30 seconds, the pedestrian goes to RED and the GREEN in signal1 goes ON for 25 seconds. 4. After 25 seconds, the YELLOW will be ON for 5 seconds and then it goes to RED, simultaneously the GREEN in signal2 will be ON.
147

5. Similar procedure is repeated for all the signals. Then the procedure is repeated again by switching the GREEN in all the Pedestrians. SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs Used 78 87 151 27 3 Available 3584 7168 7168 97 8 Utilization 2% 1% 2% 27% 37%

RTL Schematic Representation Top Level

RESULT: Thus the traffic light controller was designed using verilog code and its working was tested in FPGA board.

148