SN54LS06, SN74LS06, SN74LS16

HEX INVERTER BUFFERS/DRIVERS

The SN74LS16 is obsolete
and is no longer supplied. WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS020D – MAY 1990 – REVISED FEBRUARY 2003

D Convert TTL Voltage Levels to MOS Levels SN54LS06 . . . J PACKAGE

D High Sink-Current Capability

SN74LS06, SN74LS16 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
D Input Clamping Diodes Simplify System
Design 1A 1 14 VCC
D Open-Collector Driver for Indicator Lamps 1Y 2 13 6A
and Relays 2A 3 12 6Y
D Inputs Fully Compatible With Most TTL
2Y
3A
4 11 5A
5 10 5Y
Circuits
3Y 6 9 4A
description/ordering information GND 7 8 4Y

These hex inverter buffers/drivers feature

SN54LS06 . . . FK PACKAGE
high-voltage open-collector outputs to interface (TOP VIEW)
with high-level circuits (such as MOS), or for

VCC
NC
1Y
1A

6A
driving high-current loads, and also are
characterized for use as inverter buffers for driving
TTL inputs. The ’LS06 devices have a rated output 3 2 1 20 19
2A 4 18 6Y
voltage of 30 V, and the SN74LS16 has a rated NC 5 17 NC
output voltage of 15 V. The maximum sink current 2Y 6 16 5A
for the SN54LS06 is 30 mA, and for the NC
NC 7 15
SN74LS06 and SN74LS16 it is 40 mA. 14 5Y
3A 8
9 10 11 12 13
These devices are compatible with most TTL
families. Inputs are diode-clamped to minimize

3Y

4Y
4A
NC
GND
transmission effects, which simplifies design.
Typical power dissipation is 175 mW, and average
NC – No internal connection
propagation delay time is 8 ns.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP – N Tube SN74LS06N SN74LS06N
Tube SN74LS06D
SOIC – D LS06
0°C to 70°C Tape and reel SN74LS06DR
SOP – NS Tape and reel SN74LS06NSR 74LS06
SSOP – DB Tape and reel SN74LS06DBR LS06
Tube SN54LS06J SN54LS06J
CDIP – J
–55°C to 125°C Tube SNJ54LS06J SNJ54LS06J
LCCC – FK Tube SNJ54LS06FK SNJ54LS06FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
The SN74LS16 is obsolete
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS and is no longer supplied.
SDLS020D – MAY 1990 – REVISED FEBRUARY 2003

logic diagram (positive logic)

1 2 1Y
1A

3 4 2Y
2A

5 6
3A 3Y

9 8
4A 4Y

11 10
5A 5Y

13 12
6A 6Y

Pin numbers shown are for the D, DB, J, N, and NS packages.

schematic (each gate)

VCC

9 kΩ 2.5 kΩ
15 kΩ 1 kΩ

2.5 kΩ Output
Input

2 kΩ 2 kΩ

GND

Resistor values shown are nominal.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
The SN74LS16 is obsolete
and is no longer supplied. WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS020D – MAY 1990 – REVISED FEBRUARY 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage, VO (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

SN74LS06
SN54LS06
SN74LS16 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
’LS06 30 30
VOH High level output voltage
High-level V
SN74LS16 15
IOL Low-level output current 30 40 mA
TA Operating free-air temperature –55 125 0 70 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN74LS06
SN54LS06
PARAMETER TEST CONDITIONS‡ SN74LS16 UNIT
MIN TYP§ MAX MIN TYP§ MAX
VIK VCC = MIN, II = –12 mA –1.5 –1.5 V
’LS06, VOH = 30 V 0.25 0.25
IOH VCC = MIN
MIN, VIL = 0
0.8
8V mA
SN74LS16, VOH = 15 V 0.25
IOL = 16 mA 0.25 0.4 0.25 0.4
VOL VCC = MIN, VIH = 2 V IOL = 30 mA 0.7 V
IOL = 40 mA 0.7
II VCC = MAX, VI = 7 V 1 1 mA
IIH VCC = MAX, VI = 2.4 V 20 20 µA
IIL VCC = MAX, VI = 0.4 V –0.2 –0.2 mA
ICCH VCC = MAX 18 18 mA
ICCL VCC = MAX 60 60 mA
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC = 5 V, and TA = 25°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
The SN74LS16 is obsolete
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS and is no longer supplied.
SDLS020D – MAY 1990 – REVISED FEBRUARY 2003

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

FROM TO
PARAMETER TEST CONDITIONS MIN MAX UNIT
(INPUT) (OUTPUT)
tPLH 7 15
A Y RL = 110 Ω
Ω, CL = 15 pF ns
tPHL 10 20

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
The SN74LS16 is obsolete
and is no longer supplied. WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS020D – MAY 1990 – REVISED FEBRUARY 2003

PARAMETER MEASUREMENT INFORMATION

VCC
Test RL
Test Point S1
Point VCC
From Output
VCC Under Test (see Note B)
RL CL
From Output RL (see Note A) 5 kΩ
Under Test (see Note B) From Output Test
CL Under Test Point
(see Note A) CL
(see Note A) S2

LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS

3V
High-Level Timing
Pulse 1.3 V 1.3 V Input 1.3 V
0V
tw th
tsu
3V
Low-Level Data
1.3 V 1.3 V 1.3 V 1.3 V
Pulse Input
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD TIMES

Output 3V
Control
(low-level 1.3 V 1.3 V
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ

tPLH tPHL

In-Phase
Waveform 1 ≈1.5 V
VOH (see Notes C 1.3 V
Output 1.3 V 1.3 V VOL + 0.5 V
and D)
(see Note D) VOL VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase Waveform 2 VOH – 0.5 V
VOH
(see Notes C 1.3 V
Output 1.3 V 1.3 V
and D) ≈1.5 V
(see Note D) VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

 MECHANICAL DATA

MCER002C – JANUARY 1995 – REVISED JUNE 1999

J (R-GDIP-T**) CERAMIC DUAL-IN-LINE

14 LEADS SHOWN

PINS **
14 16 20
DIM

0.310 0.310 0.310

A MAX
(7,87) (7,87) (7,87)
B
0.290 0.290 0.290
14 8 A MIN
(7,37) (7,37) (7,37)

0.785 0.785 0.975

B MAX
(19,94) (19,94) (24,77)
C
0.755 0.755 0.930
B MIN
(19,18) (19,18) (23,62)

0.300 0.300 0.300

C MAX
1 7 (7,62) (7,62) (7,62)
0.065 (1,65)
0.245 0.245 0.245
0.045 (1,14) C MIN
(6,22) (6,22) (6,22)

0.100 (2,54)
0.020 (0,51) MIN A
0.070 (1,78)

0.200 (5,08) MAX

Seating Plane

0.130 (3,30) MIN

0.023 (0,58)
0.015 (0,38) 0°–15°

0.100 (2,54) 0.014 (0,36)

0.008 (0,20)

4040083/E 03/99

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, and GDIP1-T20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

 MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX

0.342 0.358 0.307 0.358

19 11 20
(8,69) (9,09) (7,80) (9,09)
20 10 0.442 0.458 0.406 0.458
28
(11,23) (11,63) (10,31) (11,63)
21 9
B SQ 0.640 0.660 0.495 0.560
22 8 44
(16,26) (16,76) (12,58) (14,22)
A SQ
23 7 0.739 0.761 0.495 0.560
52
(18,78) (19,32) (12,58) (14,22)
24 6
0.938 0.962 0.850 0.858
68
(23,83) (24,43) (21,6) (21,8)
25 5
1.141 1.165 1.047 1.063
84
(28,99) (29,59) (26,6) (27,0)
26 27 28 1 2 3 4

0.020 (0,51) 0.080 (2,03)

0.010 (0,25) 0.064 (1,63)

0.020 (0,51)
0.010 (0,25)

0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)

0.028 (0,71) 0.045 (1,14)

0.022 (0,54) 0.035 (0,89)
0.050 (1,27)

4040140 / D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

MECHANICAL

MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

16 PINS SHOWN

PINS **
14 16 18 20
DIM

0.775 0.775 0.920 1.060

A A MAX
(19,69) (19,69) (23,37) (26,92)

16 9 0.745 0.745 0.850 0.940

A MIN
(18,92) (18,92) (21,59) (23,88)

0.260 (6,60) MS-100

AA BB AC AD
0.240 (6,10) C VARIATION

1 8
0.070 (1,78)
D
0.045 (1,14)

0.045 (1,14) 0.325 (8,26)

0.020 (0,51) MIN
0.030 (0,76) D 0.300 (7,62)
0.015 (0,38)

0.200 (5,08) MAX Gauge Plane

Seating Plane

0.125 (3,18) MIN 0.010 (0,25) NOM

0.100 (2,54) 0.430 (10,92) MAX

0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M

14/18 PIN ONLY

20 pin vendor option D
4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

 MECHANICAL DATA

MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.020 (0,51)
0.050 (1,27) 0.010 (0,25)
0.014 (0,35)
8 5

0.244 (6,20) 0.008 (0,20) NOM

0.228 (5,80)
0.157 (4,00)
0.150 (3,81)

Gage Plane

1 4 0.010 (0,25)

A 0°– 8°
0.044 (1,12)
0.016 (0,40)

Seating Plane

0.010 (0,25)
0.069 (1,75) MAX 0.004 (0,10)
0.004 (0,10)

PINS **
8 14 16
DIM

0.197 0.344 0.394

A MAX
(5,00) (8,75) (10,00)
0.189 0.337 0.386
A MIN
(4,80) (8,55) (9,80)

4040047/E 09/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

 MECHANICAL DATA

MSOP002 – OCTOBER 1994

NS (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,51
1,27 0,25 M
0,35
14 8

0,15 NOM
5,60 8,20
5,00 7,40

Gage Plane

1 7 0,25

A 0°– 10° 1,05

0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24
DIM

A MAX 10,50 10,50 12,90 15,30

A MIN 9,90 9,90 12,30 14,70

4040062 / B 02/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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