SCBS682G − MARCH 1997 − REVISED OCTOBER 2003

D Support Mixed-Mode Signal Operation (5-V SN54LVTH541 . . . J OR W PACKAGE

Input and Output Voltages With 3.3-V VCC) SN74LVTH541 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C OE1 1 20 VCC
D Support Unregulated Battery Operation A1 2 19 OE2
Down to 2.7 V A2 3 18 Y1
D Ioff and Power-Up 3-State Support Hot A3 4 17 Y2
Insertion A4 5 16 Y3
D Bus Hold on Data Inputs Eliminates the A5 6 15 Y4
Need for External Pullup/Pulldown A6 7 14 Y5
Resistors A7 8 13 Y6
A8 9 12 Y7
D Latch-Up Performance Exceeds 500 mA Per
GND 10 11 Y8
JESD 17
D ESD Protection Exceeds JESD 22
SN54LVTH541 . . . FK PACKAGE
− 2000-V Human-Body Model (A114-A)
(TOP VIEW)
− 200-V Machine Model (A115-A)

OE1

OE2
VCC
A2
A1
description/ordering information
These octal buffers/drivers are designed 3 2 1 20 19
A3 4 18 Y1
specifically for low-voltage (3.3-V) VCC operation, A4 5 17 Y2
but with the capability to provide a TTL interface A5 6 16 Y3
to a 5-V system environment. A6 7 15 Y4
The ’LVTH541 devices are ideal for driving bus A7 8 14 Y5
9 10 11 12 13
lines or buffer-memory address registers. These
devices feature inputs and outputs on opposite

A8

Y8
Y7
Y6
GND
sides of the package that facilitate printed circuit
board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2)
input is high, all outputs are in the high-impedance state.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube SN74LVTH541DW
SOIC − DW LVTH541
Tape and reel SN74LVTH541DWR
SOP − NS Tape and reel SN74LVTH541NSR LVTH541
−40°C to 85°C
SSOP − DB Tape and reel SN74LVTH541DBR LXH541
Tube SN74LVTH541PW
TSSOP − PW LXH541
Tape and reel SN74LVTH541PWR
CDIP − J Tube SNJ54LVTH541J SNJ54LVTH541J
−55°C
−55 C to 125
125°C
C CFP − W Tube SNJ54LVTH541W SNJ54LVTH541W
LCCC - FK Tube SNJ54LVTH541FK SNJ54LVTH541FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.




   !"#$%&' #"'('  Copyright  2003, Texas Instruments Incorporated
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+&#)#("' +&* & &*% ") &.( '*$%&' ('!(*! /(**('0
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+(*(%&&*

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1





    


 
 

SCBS682G − MARCH 1997 − REVISED OCTOBER 2003

description/ordering information (continued)

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

FUNCTION TABLE
INPUTS OUTPUT
OE1 OE2 A Y
L L L L
L L H H
H X X Z
X H X Z

logic diagram (positive logic)

1
OE1
19
OE2

2 18
A1 Y1

To Seven Other Channels

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





    


 
 

SCBS682G − MARCH 1997 − REVISED OCTOBER 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVTH541 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH541 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH541 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH541 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

SN54LVTH541 SN74LVTH541
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 5.5 5.5 V
IOH High-level output current −24 −32 mA
IOL Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TA Operating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3





    


 
 

SCBS682G − MARCH 1997 − REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54LVTH541 SN74LVTH541
PARAMETER TEST CONDITIONS UNIT
MIN TYP† MAX MIN TYP† MAX
VIK VCC = 2.7 V, II = −18 mA −1.2 −1.2 V
VCC = 2.7 V to 3.6 V, IOH = −100 µA VCC−0.2 VCC−0.2
VCC = 2.7 V, IOH = −8 mA 2.4 2.4
VOH V
IOH = −24 mA 2
VCC = 3 V
IOH = −32 mA 2
IOL = 100 µA 0.2 0.2
VCC = 2.7 V
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
VOL V
IOL = 32 mA 0.5 0.5
VCC = 3 V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
Control inputs VCC = 3.6 V, VI = VCC or GND ±1 ±1
II µA
A
VI = VCC 1 1
Data inputs VCC = 3.6 V
VI = 0 −5 −5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VI = 0.8 V 75 75
VCC = 3 V
II(hold) Data inputs VI = 2 V −75 −75 µA
VCC = 3.6 V‡, VI = 0 to 3.6 V ±500
IOZH VCC = 3.6 V, VO = 3 V 5 5 µA
IOZL VCC = 3.6 V, VO = 0.5 V −5 −5 µA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
IOZPU ±100∗ ±100 µA
OE = don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
IOZPD ±100∗ ±100 µA
OE = don’t care

VCC = 3.6 V, Outputs high 0.19 0.19

ICC IO = 0, Outputs low 5 5 mA
VI = VCC or GND Outputs disabled 0.19 0.19
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
∆ICC§ 0.2 0.2 mA
Other inputs at VCC or GND
Ci VI = 3 V or 0 3 3 pF
Co VO = 3 V or 0 7 7 pF
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.

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4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





    


 
 

SCBS682G − MARCH 1997 − REVISED OCTOBER 2003

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH541 SN74LVTH541
FROM TO VCC = 3.3 V VCC = 3.3 V
PARAMETER VCC = 2.7 V VCC = 2.7 V UNIT
(INPUT) (OUTPUT) ± 0.3 V ± 0.3 V
MIN MAX MIN MAX MIN TYP† MAX MIN MAX
tPLH 1 3.7 4 1.1 2.4 3.5 3.9
A Y ns
tPHL 1 3.7 4 1.1 2.4 3.5 3.9
tPZH 1.4 5.3 6.3 1.5 3.5 5.2 6.2
OE1 or OE2 Y ns
tPZL 1.4 5.4 6 1.5 3.7 5.3 5.9
tPHZ 1.4 5.8 6.1 1.5 3.9 5.6 5.9
OE1 or OE2 Y ns
tPLZ 1.4 5.4 5.7 1.5 3 5 5.3
† All typical values are at VCC = 3.3 V, TA = 25°C.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5





    


 
 

SCBS682G − MARCH 1997 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

6V
500 Ω S1 Open TEST S1
From Output
Under Test GND tPHL/tPLH Open
tPLZ/tPZL 6V
CL = 50 pF
(see Note A) 500 Ω tPHZ/tPZH GND

2.7 V
LOAD CIRCUIT Timing Input 1.5 V
0V

tw
tsu th
2.7 V
2.7 V
Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

2.7 V 2.7 V
1.5 V 1.5 V Output 1.5 V
Input 1.5 V
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH 3V
Waveform 1
Output 1.5 V 1.5 V 1.5 V
S1 at 6 V VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
Waveform 2 VOH − 0.3 V
Output 1.5 V 1.5 V 1.5 V
S1 at GND
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

0.020 (0,51)
0.050 (1,27) 0.010 (0,25)
0.014 (0,35)
16 9

0.419 (10,65)
0.400 (10,15)
0.299 (7,59) 0.010 (0,25) NOM
0.291 (7,39)

Gage Plane

0.010 (0,25)
1 8
0°– 8° 0.050 (1,27)
A 0.016 (0,40)

Seating Plane

0.012 (0,30)
0.104 (2,65) MAX 0.004 (0,10)
0.004 (0,10)

PINS **
16 18 20 24 28
DIM

0.410 0.462 0.510 0.610 0.710

A MAX
(10,41) (11,73) (12,95) (15,49) (18,03)

0.400 0.453 0.500 0.600 0.700

A MIN
(10,16) (11,51) (12,70) (15,24) (17,78)

4040000/E 08/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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