DSILC6-4xx

ESD Protection for high speed interface

Main applications
Where transient over-voltage protection in ESD sensitive equipment is required, such as:

I/O3 VCC I/O4 I/O2 GND I/O1

Computers Printers Communication systems Cell phone handsets and accessories Video equipment

SOT-666 DSILC6-4P6

Flip-Chip DSILC6-4F2

Functional diagram

Description
The DSILC6-4xx is a monolithic application specific discrete dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet, display and camera serial interfaces (LVDS).

I/O4

VCC

I/O3

I/O1

VCC

I/O2

I/O4
I/O1 GND I/O2

GND

I/O3

The device is ideal for applications where both reduced printed circuit board space and power absorption capability are required.

SOT-666 Top-side view

Flip-Chip Top-side view

Features
Diode array topology

I/O1 I/O4

VCC GND

I/O2 I/O3

4 line protection 5 V VCC protection Very low capacitance: 1 pF typ. Lead-free pacakge RoHS compliant

Flip-Chip Top-side view

Order Code
Part Number DSILC6-4P6 DSILC6-4F2 Marking G EI

Benefits

Very low capacitance between lines to GND for optimized data integrity Low PCB space consumption: 2.9 mm max for SOT-666 and 1.5 mm max for Flip-Chip Cut-off frequency > 2 GHz High reliability offered by monolithic integration MDDI, SMIA, MIPI specification compliant

Complies with the following standards:

IEC 61000-4-2 level 4: 8 kV (contact discharge) 15 kV (air discharge) MIL STD 883G-Method 3015-7: class 3B

May 2007

Rev 3

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Characteristics

DSILC6-4xx

1
Table 1.
Symbol VPP IPP PPP Tstg Tj TL

Characteristics
Absolute ratings
Parameter Peak pulse voltage Peak pulse current Peak pulse power Storage temperature range Maximum junction temperature Lead solder temperature (10 seconds duration) IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge SOT-666 I/O to GND Pulse waveform = 8/20 s SOT-666 Flip-Chip Flip-Chip Value 8 15 5 7 90 120 -55 to +150 125 260 Unit kV A W C C C

Table 2.
Symbol VRM IRM VBR VF VCL IPP

Electrical characteristics (Tamb = 25 C)

Parameter Reverse stand-off voltage Leakage current Breakdown voltage Forward voltage Clamping voltage Peak pulse current

Value Symbol IRM VBR VF Parameter Leakage current VRM = 5 V 6 1 SOT-666 Flip-Chip SOT-666 Flip-Chip SOT-666 Flip-Chip SOT-666 Flip-Chip 2 2.5 1.5 1.8 1.0 1.25 0.75 0.9 2.5 3 1.8 2.0 1.25 1.5 0.9 1.20 0.06 0.05 pF Test Conditions Min Typ Max 0.5 A V V Unit

Breakdown voltage I = 1 mA between VBUS and GND R Forward voltage IF = 10 mA VI/O = 0 V, F = 1 MHz, VOSC = 30 mV VI/O = 1.65 V, VCC = 4.3 V, F = 1 MHz, VOSC = 400 mV VI/O = 0 V, F = 1 MHz, VOSC = 30 mV VI/O = 1.65 V, VCC = 4.3 V, F = 1 MHz, VOSC = 400 mV VI/O = 0 V, F = 1 MHz, VOSC = 30 mV VI/O = 0 V, F = 1 MHz, VOSC = 30 mV

Capacitance between Ci/o-GND I/O and GND

Ci/o-i/o

Capacitance between I/O

Ci/o-GND Ci/o-i/o

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DSILC6-4xx

Characteristics

Figure 1.

Relative variation of leakage current versus junction temperature - SOT-666 (typical values)

Figure 2.

Relative variation of leakage current versus junction temperature Flip-Chip (typical values)

IRM[Tj] / IRM[Tj=25C]
100
VR = 5V

100

IRM[Tj] / IRM[Tj=25C]
VR = 5V

10

10

Tj(C)
1 25 50 75 100 125
1 25 50

Tj(C)
75 100 125

Figure 3.

Remaining voltage after Figure 4. DSILC6-4P6 during ESD 15 kV positive surge (air discharge)
10 V/div

Remaining voltage after DSILC6-4F2 during ESD 15 kV positive surge (air discharge)

10 V/div

50 ns/div

50 ns/div

Figure 5.

Remaining voltage after Figure 6. DSILC6-4P6 during ESD 15 kV negative surge (air discharge)
5 V/div

Remaining voltage after DSILC6-4F2 during ESD 15 kV negative surge (air discharge)

5 V/div

50 ns/div

50 ns/div

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Characteristics

DSILC6-4xx

Figure 7.

Frequency responses of all lines DSILC6-4P6

S21(dB)

Figure 8.

Frequency response of all lines DSILC6-4F2

S21 (dB)

0.00

0.00

- 5.00

- 5.00
- 10.00

- 10.00
- 15.00

- 15.00

- 20.00

F(Hz)
- 20.00 100.0k
- 25.00

F (Hz)
100.0M Line 2 Line 4 1.0G
1.0M 3.0M 10.0M 30.0M 100.0M 300.0M Line 2 Line 4 1.0G 3.0G

1.0M Line 1 Line 3

10.0M

Line 1 Line 3

Figure 9.

Crosstalk results for lines 1/2 and 1/3 DSILC6-4P6

S21(dB)

Figure 10. Crosstalk results for lines 1/2 and 1/3 DSILC6-4F2
0.00

0.00 - 20.00 - 40.00 - 60.00 - 80.00 - 100.00 - 120.00

S21 (dB)

- 20.00

- 40.00

- 60.00

- 80.00

- 100.00

- 120.00

F(Hz)
- 140.00 100.0k
- 140.00

F (Hz)
1.0G
1.0M Xtalk 3.0M 1/2 10.0M 30.0M 100.0M 300.0M Xtalk 1/3 1.0G 3.0G

1.0M Xtalk 1/2

10.0M

100.0M Xtalk 1/3

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DSILC6-4xx

Application examples

2
2.1

Application examples
MDDI
Lower Clamshell Upper Clamshell

Hinge
Analog Earpiece Audio

Power Data+ DataStrobe+ Strobe-

Power
DSILC6-4xx

MDDI Data (Host)

MDDI Strobe (Host)

Base band IC
GND
GND

MDDI Client & LCD Controller Chip (With Frame Buffer)

PRIMARY LCD

SECONDARY LCD

2.2

SMIA

DATA1+ DATA1-

DSILC6-4xx

CLOCK+ CLOCK-

SMIA device

SCL SDA ESDALC6V1P3

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Application examples

DSILC6-4xx

2.3

Ethernet 1 Gb
+5V

SMP75-8

BI_DA+ BI_DA-

SMP75-8

BI_DB+ BI_DBDSILC6-4xx +5V DSILC6-4xx

DATA TRANSCEIVER

SMP75-8

BI_DC+ BI_DC-

SMP75-8

BI_DD+ BI_DD-

2.4

USB 2.0
+ 3.3V DEVICEUPSTREAM RPU TRANSCEIVER
SW2
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS -

+ 5V
USB connector
Protecting Bus Switch

HUBDOWNSTREAM TRANSCEIVER

SW1

VBUS D+

DRS RS RPD
USBLC6-2SC6

VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS -

GND

RS RS RPD

GND TX LS/FS + TX LS/FS -

+ 3.3V DEVICEUPSTREAM RPU TRANSCEIVER

SW2
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS -

SW1

USB connector

VBUS D+

DRS RS
USBLC6-2P6

RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS -

GND

RS

GND TX LS/FS +

DSILC6-4xx
RPD

RS RPD

TX LS/FS -

Mode Low Speed LS Full Speed FS High Speed HS

SW1 Open Closed

SW2 Closed Open

Closed then open Open

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DSILC6-4xx

Ordering information scheme

Ordering information scheme

DSI
Product Designation Low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 4 = 4 lines Packages P6 = SOT-666 F2 = Flip-Chip

LC

6 - 4

xx

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Package information

DSILC6-4xx

Package information

Epoxy meets UL94, V0 SOT-666 Dimensions

Dimensions
b1 L1

Table 3.

Ref.

Millimeters Min. Typ. Max. Min.

Inches Typ. Max. 0.024 0.007 0.013

L3 b

A A3 b
D E1

0.45 0.08 0.17 0.19 1.50 1.50 1.10 0.50 0.19 0.10 0.10 0.27

0.60 0.018 0.18 0.003 0.34 0.007

b1 D

0.34 0.007 0.011 0.013 1.70 0.059 1.70 0.059 1.30 0.043 0.020 0.007 0.30 0.004 0.004 0.012 0.067 0.067 0.051

E
L2 E A3

E1 e L1 L2

L3

Figure 11. SOT-666 footprint

0.50

Figure 12. SOT-666 marking

0.62

2.60

0.99

0.30

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DSILC6-4xx Figure 13. Flip-Chip Dimensions

650 m 65 500 m 50

Package information

500 m 50

1.1 mm 50 m

315 m 50

Figure 14. Flip-Chip footprint

Copper pad Diameter : 220m recommended Solder stencil opening : 330m recommended

1.57 mm 50m

Figure 15. Flip-Chip marking

Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)

Solder mask opening recommendation : 300m recommended

x x z y ww

Figure 16. Flip-Chip tape and reel specifications

Dot identifying Pin A1 location 4 +/- 0.1 1.5 +/- 0.1

1.75 +/- 0.1 3.5 +/- 0.1

0.73 +/- 0.05

All dimensions in mm

In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

8 +/- 0.3

ST E

ST E

ST E

xxz yww

User direction of unreeling

xxz yww

xxz yww

4 +/- 0.1

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Ordering information

DSILC6-4xx

Ordering information
Ordering code DSILC6-4P6 DSILC6-4F2 Marking G EI Package SOT-666 Flip-Chip Weight 2.9 mg 2.22 mg Base qty 3000 5000 Delivery mode Tape and reel Tape and reel

Revision history
Date 10-Aug-2006 04-Jan-2007 Revision 1 2 Initial release. Added Flip-Chip package. Added applications examples for SMIA, Ethernet 1 Gb, and USB. Updated Tj max to 150. Added VRM line in Table 2. Modified MDDI example figure. Modified Functional diagram on page 1 to show Top side view instead of Bump side view of DSILC64F2. Removed VRM line in Table 2. Added characteristic curves specific to each package for ESD, Frequency response and Crosstalk Description of Changes

28-May-2007

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DSILC6-4xx

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