Han-Ting Chiang

Address 3F., No.32, Alley 2, Lane 76, Sec. 6,

Phone 886-2-27283620 Sinyi Rd., Sinyi District, Taipei City 110, Taiwan
E-mail r92942043@ntu.edu.tw (R.O.C.)

Objective
To pursue a Ph.D degree in E.E. UMD with specialized area - communications and signal processing
Education
 National Taiwan University Taipei, Taiwan Jun. 2005
M.S in Communications and Signal Processing
Rank 3/96 G.P.A 93.96/100 (4.0/4.0)
Thesis Advisor: Prof. See-May Phoong
Thesis: Iterative Design Methods for Filter Banks and Transceivers
 National Tsing Hua University HsinChu,Taiwan Jun. 2003
B.S in Electrical Engineering
Rank 3/52 G.P.A. 88.25/100 (3.86/4.0) Major G.P.A. 91.04/100(4.0/4.0)

Publications
[1]H.T. Chiang, S.M. Phoong and Y.P. Lin, “An Improved Design of DFT Transceivers for Unknown
channels” IEEE-EURASIP International Symposium on Control, Communications, and Signal
Processing Marrakech, Morocco March, 2006.
[2]H.T. Chiang, S.M. Phoong, and Y.P. Lin “Design of Nonuniform Filter Bank Transceivers for
Frequency Selective Channels” accepted for publication by EURASIP Journal on Applied Signal
Processing.
[3]C.Y. Huang, H.T. Chiang, K.S. Wu, L.S. Lee “Future Verification Technology – Equivalence
Checking” Micro-Electronics Magazine (in Chinese) Aug. 2004.

Relevant Courses G.P.A. 92.47/100 (4.0/4.0)

“Information Theory”, “Random Processes for Communications”, “Spread Spectrum
Communications”, “W-CDMA Communication System”, “Communication Systems (I)(II)”, “Digital
Communications(I)”, “Introduction to Computer Network”, “Signals and Systems”, “Probability”,
“Linear Algebra”, “Data Structures”, “Digital Signal Processing”, “Adaptive Signal Processing”,
“Error Correcting Codes”, “Multirate Signal Processing, Filter Bank and Wavelet”, “Digital Video
Technology”
Honors
Tung-Hu Chou and Ping-Jo Lin Scholarship, 2001
Academic Achievement Award of the Dept. E.E. of National Tsing Hua Univ.(Top 2% in class), 2002
Garmin (World leader in GPS) Scholarship, 2004
Skills
High-level Language: C,C++
Hardware Description Language: Verilog
Algorithm develop environment: Matlab
Scripting Language:Perl, HTML
CAD tolls: Xilinx, Spice, ModelSim, Virtuoso, Cadence, ICFB、synopsys、DA

Work experience
 Private Tutor Oct. 2002~Apr. 2003
Teach Probability using textbook “Fundamentals of Probability” by Saeed Ghahramani
 Second Lieutenant Squadron Deputy Commander Oct. 2005~Jan. 2007
A 16-month compulsory military service in Taiwan

Projects
 Time Domain Equalizers for DMT Systems –Applying various TEQ methods on 8 ADSL loop
models with next noise, extend filter bank TEQ methods with weighting functions.
 Blind Equalizers – Stimulate and compare various techniques of blind equalizer such as such as
cyclic LSM，Modified LSM，FS-CMA，Slock LSM under various channel conditions.
 Reed Solomon Code Codec – Build Reed Solomon Code codec with specified requirements.
 De-interlacing for Video – Compare various De-interlacing techniques and modified the exist
method to get better subjective view.
 Mips-cpu – Design a cpu with five pipeline stages structure, forwarding unit and hazard
controller by Verilog and CAD tools.
 AMBA AHB - Design and simulate the operation of AMBA AHB by Verilog and CAD tools.

Extra-curriculum activities
 Six-year experience in piano
 Three-year experience in classic guitar
 More than fifteen-year experience in table tennis, and participate in many competitions and win
several titles, such as the second position in Taipei Elementary school table tennis team
competition, and Championship in inter-collegiate EE table tennis game 2001, 2003.