1. Study any one of the JFET models, draw the output characteristics. Draw equivalent circuit and describe.

An Improved Model for Four-Terminal Junction Field-Effect Transistors: [1] JFET has two distinct advantages. Due to direct contact with the substrate and absence of oxide, there are no surface effects and hence surface traps. The absence of the trapping states reduces the fluctuation of free-carrier transport, thus resulting in a very low noise in the JFET. Second, the JFET has two isolated gate terminals, which allows for two different inputs to be applied simultaneously for signal mixing purposes. Conventionally the JFET model that we use has only three terminals where the top and bottom gate are connected to a common gate voltage. The source-to-drain current ISD, including both the linear and saturation regions, for a p-channel JFET is given by: = tanh Where,
1

1 +

---- (1) ---- (2) ---- (3) ---- (4) Where, ISDSsource to drain saturation current -- parameter merging the linear and saturation regions VSD is the source-to drain voltage is the parameter accounting for the channel length modulation VP is the pinch-off voltage VGS is gate-to-source voltage ISDSO is ISDS at VGS = 0 VP is the threshold voltage For a three terminal JFET definition of VP is straightforward.

= 0 (1 2 )2 1 = 2 =

For a four-terminal JFET having two different gate voltages (see Fig. l), however, the definition of the pinch-off voltage becomes less clear. For a 4- terminal JFET the parameters change to B1 = VPT VGST ---- (5) B2 = VGST/VPT ---- (6)

Here VPT is the pinch-off voltage associated with the top gate of JFET and is a function of the bottom gate-to-source voltage VGSB. In other words, V-T is the top gate-to- source voltage VGST which causes the entire channel to become depleted (channel cutoff) for a given VGSB. While I SD in such a model is influenced by both VGST and VGSB, the single-pinch-off-voltage model implicitly assumes that the effect of VGSB on XB is much less significant compared to that of VGST on XT and that the pinch-off voltage VPB associated with the bottom gate can be omitted. More detailed discussions on the physics underlying the use of VPT and the development of (5) and (6) are given below. Because of the two independent gate voltages in the four-terminal JFET, two different pinch-off voltages VPT and VPB were derived by making following considerations. The pinch-off voltage VPT was derived under the condition VGSB is fixed, and the top gate-to-source voltage that causes the channel to cutoff is V PT. On the other hand, the pinch-off voltage VPB was derived under the condition VGST is fixed, and the bottom gate-to-source voltage that causes the channel to cutoff is VPB. Consider a four-terminal JFET biased with VGST = 2 V and VGSB = 4 V. If the doping concentrations in the top and bottom gates are the same, then the thickness of depletion region in the channel associated with the top gate will be smaller than that associated with the bottom gate, and VPT will be smaller than V PB. Since only a single pinch-off voltage is used in the JFET model (3), (4) selecting V PT or VPB as the pinch-off voltage is crucial because it can give rise to a large difference in the current-voltage characteristics. The problem becomes less complicated if the doping concentration in the top gate is much higher than that in the bottom gate. In such a device, the effect of VGSB on the depletion region in the channel associated with the bottom gate is minimal, and the obvious choice for the single pinch-off voltage is VPT because VGSB is in effect fixed. Thus, the expressions given in (5) and (6), which use V PT as the pinch-off voltage is valid for JFETs in which the doping concentration in the bottom gate is much smaller than that in the top gate. An improved four-terminal JFET model is developed including both VPT and VPB. The model developed will be valid for a wider range of impurities N DB and NDT. By way of MEDICI simulations, B1 and B2 get modified to: 1 = [(
1
)

+ +

]1

---- (7) ---- (8)

2 =

The two pinch-off voltages can be derived using the condition that at VSD = 0, h = XT + XB ---- (9) Where h is the channel height, and XT and XB are the depletion region thicknesses in the channel associated with the top and bottom gate junctions (Fig. 1). Thus, considering VGSB as the fixed gate voltage and VGST as the varying gate voltage: = [
2 1

2 + 1

]2

---- (10)

Where K1 = NDT/[NA(NA + NDT)] and K2 = NDB/[NA(NA + NDB] s is the dielectric permittivity; T and B are the top and bottom gate junctions. Thus considering VGSB as the fixed gate voltage and VGST as the varying gate voltage, = [
2 1

2 + 1

]2

---- (11)

For a JFET having NDB << NDT, VPB is much larger than VPT due to the fact that only a very small portion of the bottom-gate junction depletion region is extended into the channel. As a result, (7) and (8) reduce to (5) and (6), respectively, provided VGST is not very large. For a large VGST, the model given by (5) and (6) may still fail, because such a voltage results in a small VPB and thus invalidates the approximation of VPB >> VPT even if NDB << NDT. Physically, the inclusion of the effect of bottom-gate depletion region in the improved model will lead to channel cutoff at smaller gate voltages (e.g., smaller effective pinch-off voltages). Consider a four-terminal p-channel JFET (JFET-1) having a channel length of 4 m, channel thickness of 0.25 m, average channel doping concentration NA = 9 x 1016 cm-3, bottom-gate doping concentration NDB = 1015 cm-3 and, top-gate doping concentration NDT = 1.3 x 1017 cm-3 (e.g., NDT >> NDB). Fig. 2(a) and (b) shows ISDS-VGST and ISD-VSD characteristics, respectively, calculated from the present model, calculated from the previous model, and simulated from a two-dimensional (2-D) device simulator MEDICI. For such a device, the previous and present models yield very similar results; except for large VGST, where the present model predicts slightly smaller drain currents than the previous model (Fig. 2(b)). This results because a large V GST gives rise to a relatively small VPB, and the VPB >> VPT assumption used in the previous model becomes questionable. Next we consider a four-terminal JFET (JFET-2) having NDB = 1 x 10l6 cm-3, NDT = 1.5 x 1017 cm-3 (e.g., NDT not much larger than NDB), but otherwise identical structure as JFET-1. Fig. 3(a) and (b) shows ISDS-VGST and ISD-VSD characteristics, respectively, calculated from the present model, calculated from the previous model, and simulated from MEDICI. At VGSB = 0, the two

models have the same saturation drain current (Fig. 3(a)). As VGSB is increased, however, the degree of discrepancies of the two models increases with increasing VGSB and VGST. The results further suggest that the effective pinch-off voltage of the four-terminal JFET is smaller than that predicted by the previous model. This is due to the fact that the JFET considered here has a relatively small difference between the top- and bottom-gate doping concentrations, and the single-pinch-off-voltage approximation employed in the previous model becomes erroneous. For a constant VGSB of 4 V, the results in Fig. 3(b) indicate that the drain current can be greatly overestimated (i.e., about 40% at VGST = 2V) if the single-pinchoff-voltage approach is used.

Fig. 4 shows the relative magnitudes of VPT and VPB calculated as functions of VGST and VGSB for JFET-1 and JFET-2. We point out several important observations, which are consistent with device physics mentioned earlier. First, VPT is considerable larger than VPB for JFET-1, suggesting that (7) and (8) reduce to (5) and (6) for this device (e.g., VPB can be omitted). On the other hand, VPT can be larger or smaller than VPB for JFET-2, indicating the model given by (5) and (6) is not applicable for this device (e.g., both VPT and VPB are important). Second, VPT is constant versus VGST because VGSB is fixed, whereas VPB decreases with increasing VGST. Finally, VPT and VPB for JFET-1 are larger than those for JFET-2 for all VGST due to the fact that JFET-1 has a lower bottom-gate doping density than JFET-2.

Electrical equivalent circuit: Fig. 5 shows the electrical equivalent circuit of a 4- terminal JFET. Two gates have been shown denoted by TG(top gate) and BG(bottom gate). The associated parasitic capacitances arising out of the substrate and gate electrode is shown.

Fig 5. Electrical equivalent of a four-terminal JFET

2.

Study one of the mosfet models, draw the output and transfer characteristics. Draw an equivalent circuit and describe. A simple MOSFET model for circuit analysis: [2] SHOCKLEY model for MOSFET is widely used in analytical treatments of MOSFET circuits. However, the model is not accurate in the short-channel region because it neglects the velocity saturation effects of carriers. On the other hand, there are more precise MOS models like the SPICE LEVEL3 model, BSIM, table look-up models, and so on. However, some of them are time-consuming in evaluating models and some of them need a special system with a hardware/software combination for extracting model parameters and the number of parameters is large. In order to fill the gap between the simple Shockley model and the more precise models, a new model, namely, the nth power law MOSFET model has been discussed. The objective of this model is to provide a simple model which is placed just above the Shockley model. Model: The proposed model equations are as follows. I D is the drain current. = 0 + ( 2 = ( ) =

---- (1) ---- (2) ---- (3) ---- (4)

( )

= = 1 + ; = 0 1 : = 3 = 5 2

---- (5)

< : Where Vgs, Vds, Vbs are gate-source, drain-source, bulksource voltages respectively W Channel width; Leff Effective channel length VTo, , and 2F are parameters which describe the threshold voltage. Parameters K and m control the linear region characteristics while B and n determine the saturated region characteristics. o and l are related to the finite drain conductance in the saturated region. The subscript 3 and 5 for ID denotes a triode and a pentode operating region, respectively. The validity of (3) for various MOSFETs is shown in Fig. 1.

Fig. 1. Measured n value for different MOSFETs

An application of the model to 0.25-m MOSFETs is shown in Figs. 3 and 4.

Fig. 2. Vds-Id characteristics of 0.25-nm NMOS ( VBS = 0V)

Fig. 3. VGS-lD characteristics of 0.25-nm NMOS

V).

The present model does not give a very good approximation near and below the threshold voltage as seen in Fig. 3. The near- and sub-threshold region modelling is not important in calculating delay of most VLSIs. The modelling of the region is important in estimating the charge decay characteristic of charge storage nodes but in this case a statistical model should be used since it is very sensitive to process variation. In the sub micrometer devices, the contact resistance, drain/source diffusion resistance, and hotcarrier-induced drain resistance are important. It is better for MOS model to incorporate these resistance effects by just modifying parameters of the model. An example is shown in Fig. 4. Dotted lines in the figure are simulated ID-VDS curves of a 0.25-m Fig. 4:0.25-m PMOS VDS-ID and VGS-ID characteristics with and without source and drain resistance. PMOSFET, which includes lumped resistors whose value is 10% of the effective MOSFET resistance inserted in the drain and the source. Solid lines in the figure are calculated ID-VDS curves using the present model with the modified parameter set and without any resistors inserted in the drain and the source. This means that the present model can be fitted to the measured MOSFET I-V characteristics which include inseparable resistor effects, without adding extra nodes which are necessary when the resistor effects are modelled by lumped external resistors. The model is quite general and can be applied for GaAs FET as well. The salient feature of GaAs FET is that VDSAT is constant and not a function of VGS, which can be expressed by setting m = 0.

Electrical equivalent of MOSFET:

The electrical equivalent of MOSFET is as shown in the figure. Here the circuit is prepared using the EKV model. EKV MOSFET model is a scalable and compact simulation model built on fundamental physical properties of the MOS structure. This model is dedicated to the design and simulation of low-voltage, low-current analog, and mixed analog-digital circuits using submicron CMOS technologies. This figure represents the intrinsic and extrinsic elements of the MOS transistor. For quasi-static dynamic operation, only the intrinsic capacitances from the simpler capacitances model are shown here.

REFERENCES
[1]. J. J. Liou and Y. Yue, An Improved Model for Four-Terminal Junction Field-Effect Transistors, IEEE Transaction on electron devices Vol. 43 no. 8 p. 1309 August 1996. [2]. Takayasu Sakurai and A. Richard Newton, A Simple MOSFET model for circuit analysis, IEEE Transaction on electron devices Vol. 38 no. 4 p. 887 April 1991.