HIP4081A

Data Sheet July 2004 FN3659.7

80V/2.5A Peak, High Frequency Full Bridge FET Driver

The HIP4081A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081A can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081A can switch at frequencies up to 1MHz and is well suited to driving Voice Coil Motors, high-frequency switching power amplifiers, and power supplies. For example, the HIP4081A can drive medium voltage brush motors, and two HIP4081As can be used to drive high performance stepper motors, since the short minimum on-time can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load. A similar part, the HIP4080A, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate hysteresis mode switching. The Application Note for the HIP4081A is the AN9405.

Features
Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations Bootstrap Supply Max Voltage to 95VDC Drives 1000pF Load at 1MHz in Free Air at 50C with Rise and Fall Times of Typically 10ns User-Programmable Dead Time On-Chip Charge-Pump and Bootstrap Upper Bias Supplies DIS (Disable) Overrides Input Control Input Logic Thresholds Compatible with 5V to 15V Logic Levels Very Low Power Consumption Undervoltage Protection Pb-free Available

Applications
Medium/Large Voice Coil Motors Full Bridge Power Supplies Switching Power Amplifiers High Performance Motor Controls

Ordering Information
PART NUMBER HIP4081AIP HIP4081AIPZ (Note) HIP4081AIB HIP4081AIBZ (Note) TEMP RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 20 Ld PDIP 20 Ld PDIP (Pb-free) 20 Ld SOIC (W) 20 Ld SOIC (W) (Pb-free) PKG. DWG. # E20.3 E20.3 M20.3 M20.3

Noise Cancellation Systems Battery Powered Vehicles Peripherals U.P.S.

Pinout
HIP4081A (PDIP, SOIC) TOP VIEW
BHB BHI DIS VSS BLI ALI AHI HDEL LDEL 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 BHO BHS BLO BLS VDD VCC ALS ALO AHS AHO

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.

AHB 10

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

HIP4081A Application Block Diagram

80V

12V BHO BHS BHI BLI HIP4081A ALI AHI ALO AHS AHO BLO LOAD

GND

GND

Functional Block Diagram

(1/2 HIP4081A)
AHB 10 HIGH VOLTAGE BUS 80VDC

UNDERVOLTAGE

CHARGE PUMP

LEVEL SHIFT AND LATCH

DRIVER 11

AHO CBS AHS 12

VDD 16 AHI 7 TURN-ON DELAY

DBS DIS 3 15 VCC

TO VDD (PIN 16)

DRIVER ALI 6 TURN-ON DELAY 13

ALO CBF

+12VDC BIAS SUPPLY

ALS 14 HDEL LDEL VSS 8 9 4

HIP4081A Typical Application

(PWM Mode Switching)
80V

1 BHB HIP4081/HIP4081A 12V DIS PWM INPUT 2 BHI 3 DIS 4 VSS 5 BLI 6 ALI 7 AHI 8 HDEL 9 LDEL 10 AHB

BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11 12V LOAD

GND TO OPTIONAL CURRENT CONTROLLER

+ 6V

GND

HIP4081A
Absolute Maximum Ratings
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25C to 125C) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55C to 125C) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO . . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All Voltages relative to VSS, unless otherwise specified.

Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65C to 150C Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125C Lead Temperature (Soldering 10s)). . . . . . . . . . . . . . . . . . . . . 300C (For SOIC - Lead Tips Only

Operating Conditions
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500A to -50A Operating Ambient Temperature Range . . . . . . . . . . .-40C to 85C
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified TJ = 25C TJS = -40C TO 125C MAX MIN MAX UNITS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current VDD Operating Current VCC Quiescent Current VCC Operating Current AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage IDD IDDO ICC ICCO IAHB, IBHB IAHBO, IBHBO IHLK VAHB-VAHS VBHB-VBHS All inputs = 0V Outputs switching f = 500kHz All Inputs = 0V, IALO = IBLO = 0 f = 500kHz, No Load All Inputs = 0V, IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V f = 500kHz, No Load VBHS = VAHS = 80V, VAHB = VBHB = 93V IAHB = IAHB = 0, No Load 8.5 9.5 1 -50 0.6 11.5 10.5 12.5 0.1 1.25 -30 1.2 0.02 12.6 14.5 15.5 10 2.0 -11 1.5 1.0 14.0 7.5 8.5 0.8 -60 0.5 10.5 14.5 15.5 20 3 -10 1.9 10 14.5 mA mA A mA A mA A V

INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current IIL IIH VIN = 0V, Full Operating Conditions VIN = 5V, Full Operating Conditions VIL VIH Full Operating Conditions Full Operating Conditions 2.5 -130 -1 35 -100 1.0 -75 +1 2.7 -135 -10 0.8 -65 +10 V V mV A A

TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL, VLDEL IHDEL = ILDEL = -100A 4.9 5.1 5.3 4.8 5.4 V

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage High Level Output Voltage Peak Pullup Current VOL VCC-VOH IO + IOUT = 100mA IOUT = -100mA VOUT = 0V 0.7 0.8 1.7 0.85 0.95 2.6 1.0 1.1 3.8 0.5 0.5 1.4 1.1 1.2 4.1 V V A

HIP4081A
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified (Continued) TJ = 25C PARAMETER Peak Pulldown Current Undervoltage, Rising Threshold Undervoltage, Falling Threshold Undervoltage, Hysteresis SYMBOL IO UV+ UVHYS TEST CONDITIONS VO UT = 12V MIN 1.7 8.1 7.6 0.25 TYP 2.4 8.8 8.3 0.4 MAX 3.3 9.4 8.9 0.65 TJS = -40C TO 125C MIN 1.3 8.0 7.5 0.2 MAX 3.6 9.5 9.0 0.7 UNITS A V V V

Switching Specifications

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF. TJ = 25C TJS = -40C TO 125C MAX 60 70 70 90 25 25 75 85 70 550 620 MIN 50 40 40 30 200 MAX 80 90 90 110 35 35 95 105 90 600 690 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

PARAMETER Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) Rise Time Fall Time Turn-on Input Pulse Width Turn-off Input Pulse Width Turn-on Output Pulse Width Turn-off Output Pulse Width Disable Turn-off Propagation Delay (DIS - Lower Outputs) Disable Turn-off Propagation Delay (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS - AHO and BHO)

SYMBOL TLPHL THPHL TLPLH THPLH TR TF TPWIN-ON TPWIN-OFF TPWOUT-ON TPWOUT-OFF TDISLOW TDISHIGH TDLPLH TREF-PW TUEN

TEST CONDITIONS

MIN -

TYP 30 35 45 60 10 10 45 55 40 410 450

RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K

RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K

50 40 40 30 240 -

TRUTH TABLE INPUT ALI, BLI X 1 0 0 X NOTE: AHI, BHI X X 1 0 X U/V X 0 0 0 1 DIS 1 0 0 0 X ALO, BLO 0 1 0 0 0 OUTPUT AHO, BHO 0 0 1 0 0

X signifies that input can be either a 1 or 0.

HIP4081A Pin Descriptions

PIN NUMBER 1 SYMBOL BHB DESCRIPTION B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). Chip negative supply, generally will be ground. B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. A High-side Output. Connect to gate of A High-side power MOSFET. A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. A Low-side Output. Connect to gate of A Low-side power MOSFET. A Low-side Source connection. Connect to source of A Low-side power MOSFET. Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). B Low-side Source connection. Connect to source of B Low-side power MOSFET. B Low-side Output. Connect to gate of B Low-side power MOSFET. B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. B High-side Output. Connect to gate of B High-side power MOSFET.

BHI

DIS

4 5

VSS BLI

ALI

AHI

HDEL

LDEL

10

AHB

11 12 13 14 15 16 17 18 19 20

AHO AHS ALO ALS VCC VDD BLS BLO BHS BHO

HIP4081A Timing Diagrams

X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL U/V = DIS = 0 THPHL

XLI

XHI

XLO

XHO

THPLH

TLPLH

TR (10% - 90%)

TF (10% - 90%)

FIGURE 1. INDEPENDENT MODE

U/V = DIS = 0

XLI

XHI = HI OR NOT CONNECTED

XLO

XHO

(10% - 90%)

(10% - 90%)

FIGURE 2. BISTATE MODE

TDLPLH U/V OR DIS TREF-PW

TDIS

XLI

XHI

XLO

XHO TUEN

FIGURE 3. DISABLE FUNCTION

HIP4081A Typical Performance Curves

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified
11.0 14.0 IDD SUPPLY CURRENT (mA) 12.0 10.0 8.0 6.0 4.0 2.0 6 8 10 12 VDD SUPPLY VOLTAGE (V) 14 IDD SUPPLY CURRENT (mA) 10.5

10.0

9.5

9.0

8.5

8.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz)

FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE

FLOATING SUPPLY BIAS CURRENT (mA) 30.0

FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz)

5.0 125C ICC SUPPLY CURRENT (mA)

25.0

4.0

75C 25C

20.0

3.0

0C -40C

15.0

10.0

2.0

5.0

1.0

0.0 0 100 200 300 400 500 600 700 800 900 1000 0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz)

FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF)

2.5 FLOATING SUPPLY BIAS CURRENT (mA)

FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE

-90 LOW LEVEL INPUT CURRENT (A)

-100

1.5

-110

0.5

200 600 800 400 SWITCHING FREQUENCY (kHz)

1000

-120 -50

-25

0 25 50 75 JUNCTION TEMPERATURE (C)

100

125

FIGURE 8. IAHB, IBHB, NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY

FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE

HIP4081A Typical Performance Curves

NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) 15.0

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K and TA = 25C, Unless Otherwise Specified
80

14.0

PROPAGATION DELAY (ns) -20 0 20 40 60 80 100 120

70

13.0

60

12.0

50

11.0

40

10.0 -40

30 -40

-20

20

40

60

80

100

120

JUNCTION TEMPERATURE (C)

JUNCTION TEMPERATURE (C)

FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE
525

FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE

80

PROPAGATION DELAY (ns)

500

PROPAGATION DELAY (ns) -25 0 25 50 75 100 125 150

70

60

475

50

450

40

425 -50

30 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C)

JUNCTION TEMPERATURE (C)

FIGURE 12. DISABLE TO UPPER ENABLE, TUEN, PROPAGATION DELAY vs TEMPERATURE

450

FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE

80

REFRESH PULSE WIDTH (ns)

425

PROPAGATION DELAY (ns) -25 0 25 50 75 100 125 150

70

60

400

50

40

375

30 350 -50

20

-40

-20

20

40

60

80

100

120

JUNCTION TEMPERATURE (C)

JUNCTION TEMPERATURE (C)

FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE

FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE

HIP4081A Typical Performance Curves

80

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K and TA = 25C, Unless Otherwise Specified (Continued)
80

PROPAGATION DELAY (ns)

70 PROPAGATION DELAY (ns) -40 -20 0 20 40 60 80 100 120

70

60

60

50

50

40

40

30

30

20 JUNCTION TEMPERATURE (C)

20 -40

-20

20

40

60

80

100

120

JUNCTION TEMPERATURE (C)

FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE

80

FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE

80

PROPAGATION DELAY (ns)

PROPAGATION DELAY (ns)

70

70

60

60

50

50

40

40

30

30 20 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C)

20

FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE

13.5

FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE

13.5

GATE DRIVE FALL TIME (ns)

TURN-ON RISE TIME (ns)

12.5

12.5

11.5

11.5

10.5

10.5

9.5

9.5

8.5 -40

-20

0 20 40 60 80 100 JUNCTION TEMPERATURE (C)

120

8.5 -40

-20

20

40

60

80

100

120

JUNCTION TEMPERATURE (C)

FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE

FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE

10

HIP4081A Typical Performance Curves

6.0 HDEL, LDEL INPUT VOLTAGE (V)

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified
1500

1250 5.5 VCC - VOH (mV) 1000

5.0

750 -40C 500 0C 25C 250 75C 125C

4.5

4.0 -40

-20

0 20 40 60 80 100 JUNCTION TEMPERATURE (C)

120

0 10

12 14 BIAS SUPPLY VOLTAGE (V)

FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE

1500

FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0

1250

1000 VOL (mV)

750 -40C 500 0C 25C 250 75C 125C 0 10 12 14 BIAS SUPPLY VOLTAGE (V)

GATE DRIVE SINK CURRENT (A)

9 10 11 12 13 VDD , VCC, VAHB , VBHB (V)

14

15

16

FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100mA
3.5

FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY VOLTAGE

500 LOW VOLTAGE BIAS CURRENT (mA) 200 100 50 20 10 5 2 1 0.5 0.2 10,000pF 3,000pF 1,000pF 100pF

GATE DRIVE SINK CURRENT (A)

3.0 2.5 2.0 1.5 1.0 0.5 0.0 6 7 8 9 10 11 12 13 14 15 16 VDD, VCC, VAHB, VBHB (V)

0.1 1 2 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz)

FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY VOLTAGE

FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE

11

HIP4081A Typical Performance Curves

1000 500 LEVEL-SHIFT CURRENT (A)

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25C, Unless Otherwise Specified (Continued)

200 100 50

20 10 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz)

FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE
9.0 BIAS SUPPLY VOLTAGE, VDD (V) UV+ 8.8 DEAD-TIME (ns) 75 100 125 150 120 150

90

8.6

60

UV8.4

30 8.2 50 25 0 25 50 0 10 50 100 150 200 HDEL/LDEL RESISTANCE (k) 250 TEMPERATURE (C)

FIGURE 29. UNDERVOLTAGE LOCKOUT vs TEMPERATURE

FIGURE 30. MINIMUM DEAD-TIME vs DEL RESISTANCE

12

IN2

IN1

+12V Q1 R29 JMPR5 CONTROL LOGIC SECTION + C6 DRIVER SECTION CR2 HIP4080A/81A U1 C4 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 4 V SS 5 OUT/BLI 6 IN+/ALI 7 IN-/AHI 8 HDEL 9 LDEL R33 10 JMPR4 3 IN-/AHI 2 CW CD4069UB 1 2 CW 1 R34 3 CR1 C3 CX C5 CY 10 AHB BLS 17 16 V
DD

POWER SECTION B+ 2 C8

R21

1 3 1 Q3 2

U2 CD4069UB

JMPR1

OUT/BLI

R22 3 L1 AO +12V Q2 R23 1 3 Q4 R24 1 3 2 2 C1 L2 BO C2

13
13 5 11 ENABLE IN I R32

U2 CD4069UB U2 CD4069UB

12

JMPR2

IN+/ALI

JMPR3 HEN/BHI

VCC 15 ALS 14 ALO 13 AHS 12 AHO 11

HIP4081A HIP4081A

U2

R30

R31 COM

U2

O ALS BLS NOTES:

CD4069UB 9 U2 8 O

1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V. 2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR1 - JMPR4.

CD4069UB

FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC

GND

+12V

JMPR5

R29

R27

R28

R26

C7

C6

R32

L1

IN1 I O IN2
JMPR1 JMPR2 JMPR3 JMPR4

L2

U2

HIP4080/81

HDEL

C5

CX

ALS

CR1 R33 R34

R30

CY

BLS

FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN

R31

14

B+

COM

C8 CR2 Q1 U1 DIS C4 BHO BLO BLS Q2 1 R21 Q4 1 R22 R24 1 Q3 1 +

HIP4081A HIP4081A

ALS ALO AHO

R23

O LDEL

C3

HIP4081A Dual-In-Line Plastic Packages (PDIP)

N E1 INDEX AREA 1 2 3 N/2

E20.3 (JEDEC MS-001-AD ISSUE D)

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-

MILLIMETERS MIN 0.39 2.93 0.356 1.55 0.204 24.89 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 26.9 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93

MIN 0.015 0.115 0.014 0.045 0.008 0.980 0.005 0.300 0.240

MAX 0.210 0.195 0.022 0.070 0.014 1.060 0.325 0.280

-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E

A A1 A2 B B1 C D D1 E E1

-C-

eA eC
C

C A B S

eB

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

e eA eB L N

0.100 BSC 0.300 BSC 0.115 20 0.430 0.150 -

2.54 BSC 7.62 BSC 10.92 3.81 20

2.93

15

HIP4081A Small Outline Plastic Packages (SOIC)

N INDEX AREA E -B1 2 3 H 0.25(0.010) M B M

M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1 B MIN 0.0926 0.0040 0.014 0.0091 0.4961 0.2914 MAX 0.1043 0.0118 0.019 0.0125 0.5118 0.2992 MILLIMETERS MIN 2.35 0.10 0.35 0.23 12.60 7.40 MAX 2.65 0.30 0.49 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 1 1/02

L SEATING PLANE

C D
h x 45o

-A-

D -C-

E e

0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050

1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27

A1 0.10(0.004) C

H h L N

e
B 0.25(0.010) M C A M B S

NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

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