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ECE 5202
Integrated Circuit Microfabrication
Prof. Carlos H. Mastrangelo TR 12:25-1:45 WEB 1450

Fall 2011

Administrative Issues and Introduction Course Info Course Description Course Objectives Prerequisites Methodology Grading and Grading Policy Tentative Schedule Video Silicon Run (~40 min, bit outdated but useful)

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ECE 5202: Integrated Circuit Microfabrication Instructor: Prof. C. H. Mastrangelo (carlos.mastrangelo@utah.edu) Office: MEB 2254 Meeting Room: WEB 1450, TR 12:25-1:45 PM Office Hours: TR 3-4 PM, MEB 2254 Lab Location: MEB 1280 Main Lab TA: KyungJin Park ( kpark07@gmail.com ) Lab Meeting Time(s): TBD on Thu. 8/25 OH: F 10-12, MEB 2340

Course Description
1. ECE5202 teaches the fundamentals of integrated-circuit fabrication and giving the student a basic understanding of IC processes and the effect of processing choices on device performance. Students learn to use process simulation tools and also fabricate and characterize devices in the laboratory. This lecture part will cover the processing techniques and design methodologies of microfabrication. We will discuss the process modules: lithography, thermal oxidation, diffusion, ion implantation, etching, thin-film deposition, epitaxy, and metallization. 2. The second part of the course will cover process simulation and layout design rules aimed toward the fabrication of Metal-oxide-Semiconductor MOS devices and process integration. The laboratory part of the course will provide students opportunities to have hands-on experience to fabricate and characterize a CMOS chip

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Course Objectives
1. Teach the basic microfabrication processes construction of microelectronic devices for the

2. To gain practical hands-on experience through labs. Students will fabricate and test a simplified 7-mask polisilicon gate CMOS process 3. Lectures will cover sufficient theoretical material to permit a basic understanding of microfabrication processes so that at the end of the course you will be able to design your own device process.

Course Prerequisites
1. Students should have basic engineering mathematical problem solving skills 2. At least one introductory solid-state physics class such as ECE/MSE 3200 (Prof. Scarapulla, SP 11) 3. Students taking this class should be taking ECE 5201 concurrently (Prof. Tabib-Azar, FA 11). This class discusses physics for semiconductor devices. 4. The basic solid-state MOS device physics will be reviewed, but it is implicitly assumed that most of this material was previously learned.

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Teaching Methodology/Approach
1. Two lectures per week covering the theory of the material covered in the labs. 2. Roughly one 3-hr lab per week 3. Lab attendance is mandatory 4. Roughly weekly homework assignments 5. Roughly weekly (but brief) lab reports and one final characterization lab report

Teaching Methodology/Approach
1. The course will cover the basic microfabrication processes for the construction of microelectronic devices 2. The lectures also include some quick reviews of solid-state MOS physics 3. Some of the assignments will require the use of a 1-D process simulator (Suprem III) 4. Class lectures and homework assignments will be posted at the WebCT website ( http://webct.utah.edu ) 5. In weekly labs you will go through and fabricate a very simplistic 7-mask polysilicon gate CMOS process described in the webpage 6. A description of the features of CMOS test chip is found at the same webpage

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Other Useful Websites for Class


SIA Roadmap (Trend and Challenge) http://public.itrs.net/ Trends and forecast http://www.icknowledge.com/

Grading
1. The course grading will be determined as follows Homework 20% Two Midterm Exams 40% (20% each) Lab Reports 40% Exam 1: October 4th 2011 Exam 2: November 3rd 2011 1. Grading Policy: Adherence to deadlines is expected. It is the individual student's responsibility to keep track of deadlines and to present the work to the instructor on the specified dates. 15% per day will be subtracted from late assignments

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Class Textbook Issues


Introduction to Microelectronic Fabrication, 2nd Edition R. C. Jaeger Prentice Hall, 2002, ISBN: 0201444941

Reference Textbooks 1. S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Vol. 1, Process Technology and Vols 2-4, Lattice Press 2. R. F. Pierret, Semiconductor Device Fundamentals, Addison Wesley, 1996 3. R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, Wiley, 2002.

Tentative Course Topics

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Tentative Course Topics

Questions ?

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What is ECE5202 About?


Microfabrication Principles for IC Hands-on Fabrication and Testing of IC Devices

Silicon Planar Processing --- The Foundation of Microfabrication


All chips are built On planar substrate wafer

~100-300 mm diameter All chips fabricated simultaneously. This is called Batch Processing

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Silicon Planar Processing


Silicon chips are built on a planar substrate (wafer) on a layered manner Chips are constructed on a sequential manner through a combination of a finite set of operators or steps (combination is known as process flow) Additive steps add layers Subtractive steps remove layers Pattern Transfer removal or adding happens on selected areas

Resulting device has multi-layer 3D structure

Planar Process Yields 3D Patterned Layered Structure

S. Wolf, Silicon Processing for the VLSI ERA

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EE5202 Chip
Chip contains; N-channel MOSFETs P-channel MOSFETS Diffused resistors Metal wires MOS capacitors

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The Power of Scaling

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MOS Device Scaling

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Scaling Puts Heavy Demands on Power Management

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Beyond Transistors

Microelectromechanical Devices

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Technology can be extended for heterogeneous integration

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And it can be used to make chips that interface biological systems

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