UNIVERSITY OF UTAH

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT

EE/CS 5720/6720
Analog Integrated Circuit Design

Midterm

March 20, 2002

NAME: EE/CS 5720 EE/CS 6720

circle one
(Please print)

• Do not open the exam until instructed.

• Draw a circle or box around your final answers.

• All answers should include units (e.g., V, mA, kΩ) where appropriate. For
frequencies, use Hz (or kHz, or MHz), not radians/second.

• If you want partial credit on incorrect answers, show your work on the pages you
turn in! If you choose to turn in any sheets of scratch paper, write your name on
those sheets!

• Don’t spend all of your time on one difficult problem. Don’t be afraid to skip
ahead if you get stuck. You don’t have to work the problems in order.

• Good luck!
1. (15 points) Consider the op-amp shown below. You may assume that all the
transistors are operating in active mode.
VDD

Q5 Q6
Q10 Q8

vOUT
v- Q1 Q2 v+
CC
Q9

IBIAS
Q3 Q4 Q7

VSS
VDD = -VSS = 3 V IBIAS = 50 µA
µpCox = 40 µA/V2 µnCox = 120 µA/V2
Vtn = -Vtp = 0.8 V VA = 40 V (for all devices)
(W/L)1 = (W/L)2 = (W/L)5 = (W/L)6 = (W/L)10 = 100
(W/L)3 = (W/L)4 = 50 (W/L)8 = (W/L)9 = 200
CC = 5 pF

(a) What is the gain of this amplifier, in dB?

(b) What is the dominant pole frequency, in Hz?

(c) What is the slew rate, in V/µs?

2. (20 points) Two-stage op-amps are commonly used because single-stage amplifiers
typically yield insufficient gain. However, a high-gain single-stage amplifier can be built
if cascode transistors are added to boost the drain resistance of other transistors.
Consider the single-stage amplifier shown below.
VDD
Q5
Q10

v+ Q1 Q2 v-

Q6 VcascP
IBIAS
vOUT

Q7 VcascN

Q3 Q4

VSS
Ignore the body effect in all calculations.

(a) Write an approximate expression for the gain Av of this amplifier. You answer should
contain only gm’s and rds’s of particular transistors.

(b) Assume all transistors have the same width-to-length ratio W/L. Derive an expression
for the source voltage of Q1 if the input common-mode voltage is zero. Assume VDD > 0
and VSS < 0, and all devices are in active mode. Your answer should contain some (but
not necessarily all) of the following terms: IBIAS, W/L, µnCox, Vtn, µpCox, Vtp.
2. (continued)

(c) Derive an expression for the maximum allowable value of VcascP that keeps all
transistors in active mode, assuming the input common-mode voltage is zero. Your
answer should contain some (but not necessarily all) of the following terms: IBIAS, W/L,
µnCox, Vtn, µpCox, Vtp.

(d) Derive an expression for the minimum allowable value of VcascN that keeps all
transistors in active mode, assuming the input common-mode voltage is zero. Your
answer should contain some (but not necessarily all) of the following terms: IBIAS, W/L,
µnCox, Vtn, µpCox, Vtp.
3. (10 points) Circuit design often involves trade-offs between small-signal ac
performance (e.g., gain), and large-signal dc performance (e.g., voltage swing
limitations). Consider the following common-source amplifier:

VDD

vOUT

vIN Q1

The transistor has an Early voltage VA. Let VOUTmin be the minimum output voltage that
keeps the transistor in active (saturation) region. Express the gain of this circuit (Av) in
terms of VA and VOUTmin only.
4. (20 points) We are testing a nMOS transistor fabricated in a new CMOS process. The
device has a width of 2µm and a length of 2µm. We set the substrate and source voltage
to zero volts. We make the drain voltage equal 5V. With the gate voltage at 1.0V, we
measure 8.0µA of drain current. With the gate voltage at 2.0V, we measure 98.0µA of
drain current.

(a) What is the nMOS threshold voltage of this process? (You may neglect channel-
length modulation effects.) Circle your answer!

(b) Given that the gate oxide is made of SiO2 and has a thickness of 150 Å (15 nm), What
is the electron mobility in this process? Express your answer in units of cm2/(V·s).
Circle your answer!

Suppose we now test a pMOS transistor in this process. The device has a width of 2µm
and a length of 2µm. We set the well and source voltage to 5.0V. We make the drain
voltage equal zero volts. With the gate voltage at 3.5V, we measure 9.8µA of drain
current. With the gate voltage at 2.5V, we measure 57.8µA of drain current.

(c) What is the pMOS threshold voltage of this process? (You may neglect channel-
length modulation effects.) Circle your answer!

(d) Given that the gate oxide is made of SiO2 and has a thickness of 150 Å (15 nm), What
is the hole mobility in this process? Express your answer in units of cm2/(V·s). Circle
your answer!
5. (20 points) Consider the common-source amplifier shown below. Assume the current
source is ideal (i.e., it has an infinite output impedance). Assume that Early voltage is
proportional to transistor length.
VDD

vOUT
CL

vIN Q1

(a) If we decrease the transistor length L by a factor of two, what happens to the gain and
bandwidth of this simple amplifier?

The gain (increases decreases) by a factor of __________________

circle one

The bandwidth (increases decreases) by a factor of __________________

circle one

(b) If we decrease the bias current I by a factor of two, what happens to the gain and
bandwidth of this simple amplifier?

The gain (increases decreases) by a factor of __________________

circle one

The bandwidth (increases decreases) by a factor of __________________

circle one
6. (15 points) Consider the amplifier shown below.

VDD

Q3 Q4

Vout

Vin+ Q1 Q2 Vin-

IBIAS Q6 Q7

Q8 Q5

Ignore the body effect in all calculations.

(a) Derive an approximate expression for the gain Av of this amplifier. You answer
should contain only gm’s and rds’s of particular transistors. Hint: You may find it useful
to draw a small-signal model, substituting the T model for Q1 and Q2. You may neglect
rds6 and rds7.

(b) If all transistors in this amplifier have the same width-to-length ratio W/L, derive an
expression for the minimum allowable common-mode input voltage to keep all
transistors in active mode. Your answer should contain some (but not necessarily all) of
the following terms: IBIAS, W/L, µnCox, Vtn, µpCox, Vtp.