ASSIGNMENT

#1 Simplify the following expression using Boolean algebra.

1.

A+AB

2. AB+AB 3. ABC+AC 4. AB+ABC+ABC

#2 Simplify the following expression using three variable maps. 1 F(x,y,z)=(0,1,5,7) 2 F(x,y,z)=(1,2,3,6,7) 3 F(x,y,z)=(3,5,6,7) 4 F(x,y,z)=(0,2,3,4,6)

#3 Convert the following numbers with indicated bases to decimal no. . (12121)3 ,(4310)5, (50)7 ,(198)12 #3 Convert the following decimals no. to binary: 1231,673,1998. #4 Convert the following decimals no. to base indicated. a. 7562 to octal b. 1938 to hex

c. 175 to binary

#5 Convert the hexadecimal no. F3A7C2 to binary and octal. #6 Show the values of all bits of a 12 bit register that hold the no. equivalent to decimal 215 in binary,binary coded octal,binary coded hex,binary coded decimal. #7 Obtain 9s complement of the following eight digit decimal no.: 12349867;00980100;90009951;00000000 #8 Obtain 10s complement of the following six digit decimal no.: 123900;090657;100000,000000 #9 Obtain the 1s and 2s complements of following eight digit nos: 10101110;10000001;10000000;00000001.. #10 Perform the subtraction with following unsigned decimal nos by taking 10s complement of the subtrahend. a. 5250-1321 b. 1753-8640 c. 20-100 d. 1200-250

#11 Perform the subtraction with following unsigned binary nos by taking 2s complement of the subtrahend. a. 11010-10000 b. 11010-1101

c. 100-110000 d. 1010100-1010100

#12 Perform the arithmetic operation +42 + -13 and -42 - -13 in binary using signed-2s complement representation. Chapter 4 #1 Show the block diagram of the hardware that implements the following register transfer statement : yT2: R2R1 , R1R2

#2 Represent the following conditional control statement by two register transfer statements with control functions If (p=1) then (R1R2) else if (Q=1) then (R1R3)

#3 What has to be done with the bus system to be able to transfer information from any register to any other register ? Specifically , show the connections that must be included to provide a path from the outputs of register C to the input of register A?

#4 Draw a diagram of a bus system similar to the one shown in fig 4-3 (refer morris mano) ,but use three state buffer and a decoder instead of the multiplexer.

#5 A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers.

a. How many selection inputs are there in each multiplexer? b. What size of multiplexers are needed?
c.

How many multiplexers are there in the bus?

#6 The following transfer statements specify memory . Explain the memory operation in each use. a. R2M[AR] b. M[AR]R3 c. R5M[R5]

#7 The adder subtractor circuit of fig 4-7 (refer morris mano) has the following values for input mode M and data inputs A and B . In each case, determine the values of the output : S3,S2,S1,S0 and C4 M a. b. c. d. e. 0 0 1 1 1 A 0111 1000 1100 0101 0000 B 0110 1001 1000 1010 0001

#8 Design a 4-bit combinational circuit decrementer using four full adder circuits .

#9 Design an arithmetic circuit with one selection variable S and two n-bit data input A and B . The circuit generates the following four arithmetic operations in conjunction with the input carry Cin. Draw the logic diagram for the first two stages. S 0 (increment) 1 (subtract) Cin =0 D = A+B (add) D = A-1 (increment) Cin =1 D = A+1 D = A +B +1

#10 Design a digital circuit that performs the four logic operations of exclusive OR , exclusive NOR ,NOR and NAND . use two selection variables . Show the logic diagram of one typical stage.

#11 Register A holds the 8-bit binary 11011001.Determine the B operand and the logic microoperation to be performed in order to change the value in A to : a. 01101101 b. 11111101

#12 Starting from the initial value of R = 11011101, Determine the sequence of binary values in R after a logical shiftleft,followed by a circular shift right , followed by a logical shift right and a circular shift left.

#13 The 8-bit register AR,BR,CR and DR initially have the following values: AR = 11110010 BR = 11111111 CR = 10111001 DR = 11101010 Determine the 8-bit values in each register after the execution of the following sequence of microoperations. AR AR +BR CR CR ^ DR, BR BR +1 BR AR AR CR subtract CR from AR add BR to AR AND DR to CR , increment

Chapter 5

#13 A computer uses a memory unit 256k words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts : indirect bit , an operation code , a register code part to specify one of 64 registers, and an address part. a. How many bits are there in the operation code , the register code part , and the address part? b. Draw the instruction word format and indicate the number of bits in each part. c. How many bits are there in the data and address inputs of the memory?

#14 What is the difference between a direct and an indirect address instruction? How many references to memory are needed for each type of instruction to bring an operand into a processor register? #15 What are the two instructions needed in the basic computer in order to set the E flipflop to 1? #16 Draw a timing diagram similar to fig 5-7(refer morris mano) assuming that SC is cleared to 0 at time T3 if control signal C7 is active. C7T3 : SC0 C7 is activated with the positive clock transition associated with T1.

Chapter 8

#17 A bus organized CPU has 16 registers with 32 bits in each , an ALU , and a destination decoder.
a.

How many multiplexers are there in the A bus , and what is the size of each multiplexer?

b. How many selection inputs are needed for mux A and mux B? c. How many inputs and outputs are there in the decoder? d. How many inputs and outputs are there in the ALU for data, including input and output carries? e. Formulate a control word for the system assuming that the ALU has 35 operations.

#18 Specify the control word that must be applied to the processor of fig 8-2(refer morris mano) to implement the following microoperations a. R1 R2 +R3 b. R4 R4 c. R5 R5 1 d. R6 shl R1 e. R7 input #19 Convert the following arithmetic expressions from infix to reverse polish notation. a. A*B + C*D + E*F b. A*B+A*(B*D + C*E) c. A + B *[(C*D + E*(F +G)] d. A*[B +C * (D +E)] F* (G +H) #20 Convert the following arithmetic expressions from reverse polish notation to infix polish notation. a. A B C D E +*-/ b. A B C D E */-+ c. A B C D E F G +*+*+* d. A B C */D E F /+ #21 A computer has 32-bit instructions and 12-bit addresses.If there are 250 two address instructions, how many one address instruction can be formulated ? #22 Write a program to evaluate the arithmetic statement:

X= A B + C * (D*E F) G + H *K a. Using a general register computer with three address instructions. b. Using a general register computer with two address instructions.
c.

Using an accumulator type computer with one address instructions.

d. Using a stack organized computer with zero-address operation instructions. #23 A two-word instruction is stored in memory at an address designated by the symbol W. The address field of the instruction (stored at W +1 ) is designated by the symbol Y . the operand used during the execution of the instruction is stored at an address symbolized by z. An index register containsthe value X. State how Z is calculated from other addresses if the addressing of the instruction is a. Direct b. Indirect c. Relative d. Indexed #24 A relative mode branch type of instruction is stored in memory at an address equivalent to decimal 750 . the branch is made to an address equivalent to decimal 500. a. What should be the value of the relative address field of the instruction (in decimal)?

b. Determine the relative address value in binary using 12 bits . (why must the number be in 2s complement?) c. Determine the binary value in PC after the fetch phase and calculate the binary value of 500. Then show that the binary in PC plus the relative address calculated in part b is equal to the binary value of 500. #25 An instruction is stored at location 300 with its address field at location 301 . the address field has the value 400 . A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is (a) direct (b) immediate (c)relative (d) register indirect (e) index with R1 as the index register.

Chapter -9 #26 In certain scientific computations it is necessary to perform the arithmetic operation (Ai +Bi)(Ci + Di) with a stream of numbers . Specify a pipeline configuration to carry out this task . List the contents of all registers in the pipeline for i=1 through 6. #27 Draw a space-time diagram for a six-segment pipeline showing the time it takes to process eight tasks. #28 Determine the number of clock cycles that it takes to process 200 tasks in a six-segment pipeline. #29 The nonpipeline system takes 50 ns to process a task . the same task can be processed in a six segment pipeline with clock cycle of 10ns . Determine the speedup ratio of the pipeline for 100ns task . what is the maximum speedup that can be achieved?

#30 consider the four instructions in the following program . suppose that the first instruction starts from step 1 in the pipeline

used in fig 9-8 . specify what operation are performed in the four segments during step 4. Load ADD Inc Store R1 M[312] R2 R2 + M[313] R3 R3 +1 M[314] R3

#31 Give an Example that uses delayed load with the threesegment pipeline of sec 9-5 (refer morris mano) #32 Consider the multiplication of two 40 40 matrices using a vector processor . a. How many product terms are there in each inner product , and how many inner products must be evaluated? b. How many multiply-add operations are needed to calculate the product matrix? #33 Show the contents of registers E,A,Q and SC (as in fig 10-12, refer morris mano) during the process of multiplication of two binary numbers ,11111 (multiplicand) and 10101 (multiplier) .the signs are not included. #34 Why should the sign of the remainder after a division be the same as the sign of the dividend ? #35 Show the contents of registers E,A,Q and SC (as in fig 10-12, refer morris mano) during the process of division of (a) 10100011 by 1011; (b) 00001111 by 0011.(use a dividend of eight bits.)