UNIVERSITY OF BAHRAIN College of Information Technology Department of Computer Engineering

Laboratory Manual

ITCE 202: Digital Logic

UOB/IT/CE

UNIVERSITY OF BAHRAIN College of Information Technology Department of Computer Engineering

ITCE 202: Digital Logic Laboratory Experiments Table of Contents

1 2 3 4 5

Familiarization of the Digital Logic Laboratory Facilities Simplification of Logic Expressions and De Morgan's Law Combinational Logic Circuit Design the 7-segment Display Combinational Logic Circuit Design using Multiplexers Counter Design Using J-K Flip-Flop

3 10 13 17 19

ITCE 202: Digital Logic

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University of Bahrain College of Information Technology Department of Computer Engineering

Prepared By: Dr. Hessa Al-Junaid Ms. Fatima AlBalooshi

ITCE 202: Digital Logic Experiment No. 1

Familiarization of the Digital Logic Laboratory Facilities Objectives

1- To familiarize the student to the lab facilities including different IC types, Breadboard and Digital Trainer. 2- To study the basic logic functions of the INVERTER, AND, NAND, OR and NOR gates and their representations, truth tables, logic diagrams and Boolean algebra.

Introductory Theory
The inputs and outputs of digital circuits are represented as two voltage levels. To provide a common and standard basis for comparison, the two voltage levels are usually represented symbolically as 1 or 0. Usually + 3.5 V or more voltage is represented by a 1 symbol while +1 V or less voltage is represented by a 0 symbol. A basic gate operation is represented in the following: AND: a multi- input circuit in which the output is a 1 only if all inputs are 1. OR: a multi-input circuit in which the output is a 1 when any input is a 1. INVERTER: the output is 0 when the input is 1, and the output is 1 when the input is 0. NAND: AND followed by INVERTER. NOR: OR followed by INVERTER.

IC Pin Connections
Each of the ICs used in this experiment is a 14-pin dual-in-line IC case. The base pins progress in a counterclockwise direction as seen from the top view of the IC (the side away from the pins), as shown in Figure 1.1 below. Pin 1 is represented by a dimple, or you can identify the location of pin 1 by the index notch at the end of the IC case where Pins 1 and 14 are located.

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Figure 1.1 IC Pin locations

Breadboard Connections
The breadboard of digital circuits has standard internal connections. The internal connections help to build the digital circuits easily. For example, for the Breadboard shown below in Figure 1.2, the internal connections would be as in Figure 1.3.

Figure 1.2 Sample Breadboard.

Figure 1.3 Internal connections of the sample Breadboard.

The lab demonstrator will guide you with more details about the breadboard.

Equipment Required
(One) IC Type 7404 hex inverter (One) IC Type 7408 quad 2-input AND gate
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(One) IC Type 7400 quad 2-input NAND gate (One) IC Type 7432 quad 2-input OR gate (One) IC Type 7402 quad 2-input NOR gate (One) Digital Trainer

Experimental Procedure
In part A, B, C, D, E, F and G do the following: 1- Make sure the digital trainer is switched off. 2- Insert the required IC into the breadboard. 3- Connect the Vcc pin to +5V and the GND pin to ground (Refer to the IC pin connections diagram attached). 4- According to each parts circuit diagram, connect the inputs to switches (e.g. SW1) on the digital trainer. Connect the outputs to LEDs (e.g L1) on the digital trainer. 5- Power on the digital trainer. 6- Start taking measurements by changing switches ON and OFF and observing the LEDs. 7- Fill in the tables. Part A: OR gate. Using IC type 7432 connect one OR gate from its package using pin 1,2,3 as shown in Figure 1.4 and fill in Table 1.1. Pin1 0 0 1 1 Figure 1.4 Pin 2 0 1 0 1 Table 1.1 Pin 3

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Part B: INVERTER Using 7404 IC connect the circuit shown in Figure 1.5 and 1.6 and fill in the Table 1.2 and 1.3.

Pin1 0 1

Pin 2

Figure 1.5 Pin 1 0 1 Figure 1.6

Table 1.2 Pin 2,3 Pin 4,13 Pin 12

Table 1.3

Part C: OR+INVERTER Using 7404 and 7432 ICs connect the circuit shown in Figure 1.7 and fill in Table 1.4. 7432 Pin 1 0 0 1 1 Figure 1.7 Pin 2 0 1 0 1 Table 1.4 7404 Pin 6

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Part D: NOR Using 7402 IC connect the circuit as shown in Figure 1.8 and fill in Table 1.5. Pin3 0 0 1 1 Figure 1.8 Part E: AND Using 7408 IC connect the circuit as shown in Figure 1.9 and fill in Table 1.6. Pin1 0 0 1 1 Figure 1.9 Part F: NAND Using 7400 IC connect the circuit as shown in Figure 1.10 and fill in Table 1.7. Pin1 0 0 1 1 Figure 1.10 Pin 2 0 1 0 1 Table 1.7 Pin 3 Pin 2 0 1 0 1 Table 1.6 Pin 3 Pin 2 0 1 0 1 Table 1.5 Pin 1

ITCE 202: Digital Logic

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Part G: AND+NAND Using 7408 and 7400 ICs connect the circuit as shown in Figure 1.11 and fill in Table 1.8.

Figure 1.11 7408 Pin 1 0 0 1 1 Pin 2 0 1 0 1 Table 1.8 Pin 3 7400 Pin 1,2 Pin 3

Questions:
1- The circuit in Part C is equivalent to which single logic gate operation. 2- Construct a circuit to perform the following function X A.B using AND and NAND gates only. 3- Redraw the circuit in Part F using AND and INVERTER only. 4- Using 7432 IC Draw the logic circuit that will implement the following Boolean function. F = A+B+C+D. 5- Write a small paragraph as a conclusion stating what you have learnt in this experiment.
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ITCE 202: Digital Logic

UOB/IT/CE

University of Bahrain College of Information Technology Department of Computer Engineering

Prepared By: Dr. Hessa Al-Junaid Ms. Fatima AlBalooshi

ITCE 202: Digital Logic Experiment No. 2

Simplification of Logic Expressions and De Morgans Law Objectives:

3- To test methods of building and simplifying logic expressions by Boolean Algebra. 4- Utilizing De Morgans theorem in simplifying and modifying Boolean logic equations.

Introductory Theory:
The exact implementation of Boolean expressions into logic circuits resulted in more expensive circuits compared to the implementation of simplified expressions using Boolean Algebra. The basic Boolean simplification theorems are listed in page 52 of the text book. De Morgans Law is used primarily to change the form of a Boolean expression. De Morgans Law allows conversion of logic circuits from OR/NOR to AND/NAND and vice versa. It is given by,

A B AB AB A B

Equipment Required:
(One) IC Type 7400 quad 2-input NAND gate (One) IC Type 7402 quad 2-input NOR gate (One) IC Type 7404 hex inverter (One) IC Type 7408 quad 2-input AND gate (One) Digital Trainer

Experimental Guidelines:
1- Make sure the digital trainer is switched off. 2- Insert the required IC into the breadboard. 3- Connect the Vcc pin to +5V and the GND pin to ground (Refer to the IC pin connections diagram attached).
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4- According to each parts circuit diagram, connect the inputs to switches (e.g. SW1) on the digital trainer. Connect the outputs to LEDs (e.g L1) on the digital trainer. 5- Power on the digital trainer. 6- Start taking measurements by changing switches ON and OFF and observing the LEDs. 7- Fill in the tables.

Procedures:
1. Examine the circuit in Figure 2.1 and write the Boolean expression for the output F.

Figure 2.1 2. Fill in for F (theoretically) in the second column of Truth Table 2.1.
ABC 000 001 010 011 100 101 110 111 Output F (Theoretical) Output F (Experimental) Simplified F (Experimental)

Truth Table 2.1 3. Construct the circuit shown in Figure 2.1 on the breadboard (use experimental guidelines from the previous section). 4. Verify different values of inputs (A, B, C) and record the experimental output values in the appropriate column of Table 2.1. 5. Simplify the expression of F. Show all steps of the simplification and state the theorem(s) used. 6. Draw the logic diagram of the simplified F.
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7. Construct the circuit of the simplified F and verify its operation for each possible input combination. Record the results in the final column of Table 2.1.

Questions:

1- Indicate which of the following expressions are in product-of-sums from, sum-of-product form, or neither:

AC B F G D (A CD)(B AC ) AB(C D F )( K G ) C D EF (G Y ) X Y Z
2- Prove the following equation using truth tables:
ABC AD ( A D )( A BC )

3- Find the complement of ( A B )C using De Morgans theorem. 4- Write a small paragraph as a conclusion stating what you have learnt in this experiment.

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University of Bahrain College of Information Technology Department of Computer Engineering

Prepared By: Dr. Hessa Al-Junaid Ms. Fatima Al-Balooshi

ITCE 202: Digital Logic Experiment No. 3

Combinational Logic Circuit Design The 7-Segment Display Objectives:

5- To convert word description of specified requirements of design problem into Boolean expressions and/or truth tables. 6- To follow a procedure of designing a digital logic circuit. 7- Design the minimum logic circuit using Karnaugh maps to simplify logic functions and test the functionality of results in the lab.

Introductory Theory:
The 7-segment display takes in Binary-Coded-Decimal number (BCD) as inputs and activate the equivalent digits on the display. Figure 3.1 shows a display format of 7-segment display. It composed of seven elements or segments. For certain combinations of these elements, the ten decimal (0-9) digits can be produced. Figure 3.2 illustrates the different displays. For example, to produce a 1, segments b and c should be ON.

Figure 3.1 A 7-segment display

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Figure 3.2 Display of decimal digits with 7-segment device.

Design Procedure:
The design of combinational circuits starts form the verbal outline of the problem and ends in a logic circuit diagram, or a set of Boolean functions from which the logic diagram can be easily obtained. The procedure involves the following steps: 1234The problem is stated. The number of available input variables and required output variables are determined. The input and output variables are assigned letter symbols. The truth table that defines the required relationship between inputs and outputs is derived. 5- The simplified Boolean function for each output is obtained. 6- The logic diagram is drawn.

Equipment Required:
(One) 7-Segment Display (Two) IC Type 7404 hex inverter (Three) IC Type 7408 quad 2-input AND gate (Four) IC Type 7432 quad 2-input OR gate (One) Digital Trainer

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Design Problem:
Design a 7-segment logic circuit where the inputs to the circuit are the bits of a BCD number and the outputs are connected to the different segments as shown in Figure 3.

Figure 3. Block diagram of 7-segment logic and display

i) ii) iii) iv) v)

Obtain the truth table. Use K-map to simplify the logic functions of all segments. Find the simplified output function in sum of products. Draw the logic circuit; write pin numbers of ICs which are used. Construct the logic circuit to display (1, 4, 7) only on the breadboard and test its functionality.

Conclusion:
Your report should show the truth table and k-maps, expressions, and logic circuits of all segments. Write a small paragraph as a conclusion stating what you have learnt in this experiment.

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7-segment Data sheet

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University of Bahrain College of Information Technology Department of Computer Engineering

Prepared By: Dr. Hessa Al-Junaid Ms. Fatima Al-Balooshi

ITCE 202: Digital Logic Experiment No. 4 Combinational Logic Circuit Design using Multiplexers

Objectives:
8- To practice how to convert word description of specific requirements of design problem into Boolean expressions. 9- To design, draw and implement logic functions using multiplexers.

Introductory Theory:
Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is selected.

Equipment Required:
(One) IC Type 74151 23-to-1 multiplexer (One) Digital Trainer

Design Problem:
A combinational circuit has four inputs (ABCD) and one output(Z). The output is equal to 1 when I. II. Both first and second inputs (AB) are equal to 1 or Both third and forth inputs(CD) are equal to 1.

Design the circuit described using 8-to-1 Mux following the steps a-g: a) Obtain the truth table.
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b) Use the K-map to realize the logic function using 8-to-1 Mux where (ABC) respectively used as selectors for the Mux. c) Draw the designed circuit. d) Construct the logic circuit on the breadboard and test its functionality. e) Use K-map to realize the logic function using 8-to-1 Mux where (BCD) respectively used as selectors of the Mux. f) Draw the designed circuit. g) Construct the logic circuit on the breadboard and test its functionality.

Questions:
1. Realize the same function using 2-to-1 multiplexers (show all your work). 2. Write a small paragraph as a conclusion stating what you have learnt in this experiment.

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University of Bahrain College of Information Technology Department of Computer Engineering

Prepared By: Dr. Hessa Al-Junaid Ms. Fatima Al-Balooshi

ITCE 202: Digital Logic Experiment No. 5

Counter Design Using J-K Flip-Flop Objectives:

10- To study sequential logic circuits and be familiar with the concept of the clock. 11- To design synchronous counter of a specified sequence.

Introductory Theory:
A Flip Flop is an electronic circuit that has two stable states and capable of being a memory of 1bit data. Flip Flops have a clock input which control their operation. Counters are built from a number of flip flops depending on the number of bits e.g. A counter to count from 0 to 2 needs 2 flip flops. Flip flops will change state according the the specified sequence when input pulses are received.

Equipment Required:
(One) IC Type 7400 quad 2-input NAND gate (Two) IC Type 7476 dual J-K flip flop (One) Digital Trainer

Experimental Guidelines:
1- Make sure the digital trainer is switched off. 2- Insert the required IC into the breadboard. 3- Connect the Vcc pin to +5V and the GND pin to ground (Refer to the IC pin connections diagram attached). 4- According to each parts circuit diagram, connect the inputs to switches (e.g. SW1) on the digital trainer. Connect the outputs to LEDs (e.g L1) on the digital trainer. 5- Power on the digital trainer. 6- Start taking measurements by changing switches ON and OFF and observing the LEDs. 7- Fill in the tables.
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Design Problem:
Design a 3-bit binary counter which counts in the sequence:

000 => 100 => 111 => 010 => 011 => 000 and repeat
Using J-K flip flops. Knowing that the transition table of the J-K flip-flop is as follows: Q Q+ 0 0 0 1 1 0 1 1 J K 0 X 1 X X 1 X 0

Procedure:
1. Construct the state table for the synchronous counter as shown in Table 5.1.
Present State A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 A+ Next State B+ C+ JA A FF KA JB B FF KB JC C FF KC

Table 5.1

2. Derive the flip-flops next state k-maps as shown below. ITCE 202: Digital Logic 20

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AB

AB

AB

00
C

01

11

10
C

00

01

11

10
C

00

01

11

10

0 1

0 1

0 1

JA=

KA=

JB=

AB

AB

AB

00
C

01

11

10
C

00

01

11

10
C

00

01

11

10

0 1

0 1

0 1

KB=

JC=

KC=

3.

Derive the J-K flip-flops input equations from the next state k-maps.

JA = ________________

JB = ________________

JC = ________________

KA = ________________

KB = ________________

KC = ________________

4.

Draw the circuit diagram of the synchronous counter using J-K flip-flops and 2- inputs NAND gates only.

5.

Draw the pin diagram for the synchronous counter. Mount the circuit on the digital trainers breadboard following the experimental guidelines. Test your circuit and verify that the generated counter sequence is identical to the desired sequence.

6. 7.

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Questions:
5- Explain how to convert a single J-K flip flop to a T-flip flop. 6- What will happen if the counter is started in state 000 or 101 or 110. Draw the complete state graph (with the not specified state 000, 101 and 110). 7- Write a small paragraph as a conclusion stating what you have learnt in this experiment.

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