EXPT NO: DATE: 1. DESIGN OF A 4-20mA TRANSMITTER FOR A BRIDGE TYPE TRANSDUCER.

AIM: To design the instrumentation amplifier with the bridge type transducer and convert the amplified voltage from the instrumentation amplifier to 4-20mA current using op-amp. SOFTWARE REQUIRED: Or cad THEORY: In a number of industrial and consumer applications physical quantities such as temperature, pressure and light intensity are to be measured and controlled. These physical quantities measured with the help of transducers have to be amplified so that it can drive the display system. This function is performed by an instrumentation amplifier. The circuit uses a resistive transducer whose resistance changes as a function of the physical quantity to be measured. The bridge is initially balanced by a dc supply so that V 1=V2. As the physical quantity changes, the resistance RT of the transducer also changes, causing an unbalance in the bridge (V1V2). This differential voltage gets amplified by the three op-amp differential instrumentation amplifier. The amplified voltage is converted to current using V-I converter. The important features of instrumentation amplifier are: 1. 2. 3. 4. 5. High Gain Accuracy High CMRR High Gain Stability With Low Temperature Coefficient Low Dc Output High Output Impedance

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

DESIGN: A sensistor is a type of resistor whose resistance changes with temperature. Instrumentation Amplifier: [ Let V1 = 2.3v V2 = 2.5v V0 = 4v Assume R' = 45k R = 10k V0 = R2/R1(1+90k/10k)(0.2v) 4v = R2/R1(1+90k/10k)(0.2v) 4 = 2R2/R1 R2/R1 = 2. Let R1 = 50k R2 = 100k V - I Converter: Let V0 = 4v I0 = 8mA R = V0/ I0 R = 500 ]

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

CIRCUIT DIAGRAM:

PINDIAGRAM of IC741:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

OUPUT:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

PROCEDURE: 1. 2. 3. 4. 5. Connections are given as per the circuit diagram. Use PSPICE simulator and run. Note down the input voltages applied to the IA, output voltage of IA and output current. Vary the resistance value and note down the readings. Plot the variation of resistance Vs output current.

RESULT: Thus the instrumentation amplifier with the bridge type transducer was designed and the amplified voltage was converted to current.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE:

2. AC/DC VOLTAGE REGULATOR USING SCR

AIM: To construct a phase controlled voltage regulator using full wave rectifier and SCR. SOFTWARE: Or Cad THEORY: In phase control the Thyristors are used as switches to connect the load circuit to the input ac supply, for a part of every input cycle. That is the ac supply voltage is chopped using Thyristors during a part of each input cycle. The thyristor switch is turned on for a part of every half cycle, so that input supply voltage appears across the load and then turned off during the remaining part of input half cycle to disconnect the ac supply from the load. By controlling the phase angle or the trigger angle (delay angle), the output RMS voltage across the load can be controlled. The trigger delay angle is defined as the phase angle (the value of t) at which the thyristor turns on and the load current begins to flow.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

CIRCUIT DIAGRAM:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

OUTPUT:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

PROCEDURE: 1. 2. 3. 4. Connections are given as per the circuit diagram. Use PSPICE simulator and run. Note down the input voltages applied to the SCR, output voltage and current of SCR. Plot the Graph.

RESULT: Thus the phase controlled voltage regulator using full wave rectifier and SCR was constructed and output was verified.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE:

3. DESIGN OF PROCESS CONTROL TIMER

AIM: Design a sequential timer to switch on & off 3 relays in a particular sequence using timer IC.

SOFTWARE REQUIRED: OrCad THEORY: The process control is the activities involved in ensuring a process is predictable, stable and consistently operating at a level(target) of performance with only normal variation. The IC 555 is highly stable device for generating accurate time delay oscillations. The process control timer designed using timer IC555 is operated in either astable or monostable mode. There are three timers used to trigger the other timers through a switch control. The output of the next timer is obtained after a delay with respect to the delay in the triggering of the circuit.

DESIGN: vc= Vcc (1 e-t/RC) At t = T, vc= (2/3) Vcc Therefore, T=1.1RC Here, T=1.1 ms Assume C= 0.1uF R= R= 10K

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

CIRCUIT DIAGRAM:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

GRAPH:

TABULATION:

Timer 1

Time, t =

ms

Frequency=

Hz

Timer 2

Time, t =

ms

Frequency=

Hz

Timer 3

Time, t =

ms

Frequency=

Hz

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

PROCEDURE: 1. 2. 3. 4. Connections are given as per the circuit diagram. Use PSPICE simulator and run. Note down the input voltages applied and the output at each stage. Plot the Graph.

RESULT: Thus a sequential timer was designed to switch on & off 3 relays in a particular sequence using timer IC.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE:

4a) AM MODULATOR / DEMODULATOR AIM: To construct Amplitude Modulator circuit using multiplier IC and Demodulator circuit using envelop detector.

SOFTWARE REQUIRED: OrCad THEORY: Modulation is achieved by varying one of the three parameters, amplitude, frequency and phase in accordance with the message signal while keeping the other two parameters as constant. Hence the amplitude is varied in accordance with the instantaneous values of the low frequency signals. The frequency of the carrier is much greater than the amplitude of the modulating signal to avoid over modulation. CIRCUIT DIAGRAM:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

GRAPH:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

PROCEDURE: 1. 2. 3. 4. 5. Connections are given as per the circuit diagram. Use PSPICE simulator and run. Note down the input voltages applied and output voltage Also note down the demodulated output. Plot the Graph and calculate the modulation index.

RESULT: Thus the message signal was modulated and demodulated. The modulation index was also calculated.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE: 4.b FREQUENCY MODULATION AIM: To perform the Frequency modulation using IC 566 and to calculate the modulation index for various modulating voltages.

HARDWARE REQUIRED: Frequency generator, IC NE566, Resistors, Capacitor, CRO, Bread board and connecting wires, RPS.

THEORY: Frequency modulation is a process of changing the frequency of a carrier wave in accordance with the slowly varying base band signal. The main advantage of this modulation is that it can provide better discrimination against noise. Frequency Modulation using IC 566: A VCO is a circuit that provides an oscillating signal whose frequency can be adjusted over a control by Dc voltage. VCO can generate both square and triangular wave signal whose frequency is set by an external capacitor and resistor and then varied by an applied DC voltage. IC 566 contains a current source to charge and discharge an external capacitor C1 at a rate set by an external resistor. R1 and a modulating DC output voltage. The Schmitt trigger circuit present in the IC is used to switch the current source between charge and discharge capacitor and triangular voltage developed across the capacitor and the square wave from the Schmitt trigger are provide as the output of the buffer amplifier. The R2 and R3 combination is a voltage divider, the voltage VC must be in the range 3/4 VCC < VC < VCC. The modulating voltage must be less than 3/4VCC the frequency fc can be calculated using the formula fo = 2 (VCC-Vc) R1 C1 VCC. For a fixed value of VC and a constant C1 the frequency can be varied at 10:1 similarly for a constant R1 C1 product value the frequency modulation can be done at 10:1 ratio.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

CIRCUIT DIAGRAM

PIN DIAGRAM:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

GRAPH:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

PROCEDURE: 1. The circuit connection is made as shown in the circuit diagram. 2. The modulating signal FM is given from a FG (1KHZ) 3. For various values of modulating voltage Vm the values of Fmax and Fmin are noted. 4.The values of the modulation index are calculated.

RESULT: Thus the FM circuit using IC566 was performed and the modulation index was found.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE: 5. DESIGN OF FSK MODULATOR USING XR 2206

AIM: To design a FSK Modulator using XR 2206.

COMPONENTS REQUIRED: IC XR 2206, Resistors, Capacitors. THEORY: In digital data communication, binary code is transmitted by shifting the carrier frequency between two preset frequencies. This type of the transmission is called Frequency Shift Keying. The standard digital data input frequency is 150Hz. Modem takes the digital electrical pulses from the terminal and converts it into the analog signal that can be transmitted. The FSK technique is employed for the modulation of digital Signal.

CIRCUIT DIAGRAM:

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GRAPH:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

PROCEDURE: 1. 2. 3. 4. 5. Connections are given as per the circuit diagram. Give the message signal. Check the output and verify. Switch off the input to find the carrier frequency. Plot the graph for input and output.

RESULT: Thus a FSK was implemented using XR2206 and verified the result

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE:

PCB LAYOUT DESIGN USING CAD

AIM: To draw the schematic of simple electronic circuit and design a PCB layout using CAD SOFTWARE REQUIRED: OrCad

THEORY: The Computer Aided analysis is essential and can provide information about the circuit performances. It permits. Evaluation of effects of variation in elements such as resistors, transistors etc. The assessment of performance improvements or degradations. Evaluation of the effects of noise and signal distortion without the need of

expensive measuring instruments. Sensitivity analysis to determine the permissible bounds due to the tolerances each and every element value or parameter of active elements. Evaluation of the effects of non-linear elements of the circuit performance. Optimization of the design of electronic circuits in terms of circuit parameters. on

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CIRCUIT DIAGRAM: Cascade Amplifier:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

OUTPUT LAYERS: Global Layer

Top Layer

Bottom Layer

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

PROCEDURE: 1. 2. Draw the circuit diagram using Pspice and get the simulated output. Create .mnl file Select the required file Go to tools and select create netlist Click Layout from the dialog box appearing and give OK. Note the path in which the .mnl file is created. 3. To create PCB Design Open OrCad Layout Plus Make the data of OrCad Layout Plus to default Take the .mnl file and save it. Select the obstacle from tools and select all the components. Auto Auto Place Auto route Board Board

View the Global Layer. View the individual layers by selecting tools, layer. Give backspace and select the layers.

RESULT: Thus a schematic of cascade amplifier circuit was designed and a PCB layout Using CAD was obtained

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE:

PSUEDO-RANDOM SEQUENCE GENERATOR

AIM: To stimulate and implement a PRBS Generator.

SOFTWARES REQUIRED: PC with Xilinx ISE Software 9.1i

PROGRAM: Simulation module prbs(rand,clk,reset); input clk,reset; output rand; wire rand; reg [3:0]temp; always @ (posedge reset) begin temp[0]=1'b0; temp[1]=1'b1; temp[2]=1'b0; temp[3]=1'b1; end always @ (posedge clk) begin if(~reset) begin temp<={temp[0]^temp[1],temp[3],temp[2],temp[1]}; end end assign rand =temp[0]; endmodule

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

OUTPUT:

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

PROCEDURE: 1. Write the coding. 2. Use Xilinx ISE simulator and run. 3. Note the output and verify.

RESULT: Thus a PRBS Generator is simulated in Verilog and implemented using Spartan3 FPGA kit.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE:

MICROCONTROLLER BASED SYSTEM DESIGN

AIM: To interface a stepper motor with 8051 micro controller and operate it. APPARATUS REQUIRED: 1.8051 micro controller kit 2. Stepper motor 3. Interface card THEORY: A motor in which the rotor is able to assume only discrete stationary angular position is a stepper motor. They are used in printer, disk drive process control machine tools etc. Two-phase stepper motor has two pairs of stator poles. Stepper motor windings A1, A2, B1, B2 are cyclically excited with a DC current to run the motor in clockwise direction and reverse phase sequence A1, B2, A2, B1 in anticlockwise stepping Two-phase switching scheme: In this scheme, any two adjacent stator windings are energized. Anticlockwise Step 1 2 3 4 A1 1 0 0 1 A2 0 1 1 0 B1 0 0 1 1 B2 1 1 0 0 Data 9H 5H 6H AH Clockwise Step 1 2 3 4 A1 1 0 0 1 A2 0 1 1 0 B1 1 1 0 0 B2 0 0 1 1 Data AH 6H 5H 9H

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

Address Decoding logic:

The 74138 chip is used for generating the address decoding logic to generate the device select pulses CS1 and CS2 for selecting the IC 74175 in which latches the data bus to stepper motor driving circuitry. PROGRAM:

Address

Opcode

Label

Mnemonics

Operand

Comments

4100

90 41 1F

START

MOV

DPTR # TABLE

Load the start address of switching scheme data TABLE into Data pointer. Load the count in R0 Load the number in TABLE into A Push DPTR Value to stack

4103 4105

78 04 F0 LOOP

MOV MOV X

R0, #04 A, @ DPTR

4106

C0 83

PUSH

DPH

4108 410A

C0 82 90 FF C0

PUSH MOV

DPL DPTR, # 0FFFC0 @ DPTR, A Load the motor port address into DPTR. Send the value in A to stepper motor port address Delay loop to cause a specific amount of time delay before next data item is sent to the motor

410D

F0

MOV X

410F

7C FF

MOV

R4,#0FFH

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4110 4112

7D FF DD FE

DELAY DELAY1

MOV DNZ

R5,#0FFH R4, DELAY 1 R4,DELAY DPL POP back DPTR value from stack

4114 4116

DC FA D0 82

DJNZ POP

4118 411A

D0 83 A3

POP INC

DPH DPTR Increment DPTR to point to next item in the TABLE Decrement R0, if not zero repeat the loop Short jump to start of the program to make the motor rotate continuosly. Value as per two phase switching scheme.

411B

D8 E8

DJNZ

R0, LOOP

411D

80 E1

SJMP

START

411F

09 05 06 0AH

TABLE

DB

09 05 06 0AH

RESULT: Enter the above program starting from location 4100 and execute the same, stepper motor rotates. Varying the count at R4 and R5 can vary the speed. Entering the data in the look-up TABLE in the reverse order can vary the direction of rotation.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE: SIMULATION OF ALU USING XILINX AIM: To stimulate and implement an ALU using Xilinx.

SOFTWARES REQUIRED: PC with Xilinx ISE Software 9.1i ,

PROGRAM:
module logic_unit(d_out1,logic_unit,s0,s1,c0,A,B); output [1:0] d_out1; input s0,s1,c0,logic_unit; input [1:0] A; input [1:0] B; reg [1:0] d_out1; always @(s0,s1,A,B,logic_unit) begin if(logic_unit== 1'b1) begin if(s0 == 1'b0 & s1 == 1'b0) begin d_out1 = ( A & B); end else if(s0 == 1'b1 & s1 == 1'b0) begin d_out1 = ( A | B); end else if(s0 == 1'b0 & s1 == 1'b1) begin d_out1 = ( A ^ B);

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end else begin d_out1 = ( A ^~ B); end end else begin d_out1 = 4'b00; end end endmodule

UCF CONSTRAIN:
NET"s0" LOC="p6"; NET"s1" LOC="p18"; NET"c0" LOC="p24"; NET"logic_unit" LOC="p36"; NET"A[0]" LOC="p38"; NET"A[1]" LOC="p41"; NET"B[0]" LOC="p69"; NET"B[1]" LOC="p78"; NET"d_out1[0]" LOC="p33"; NET"d_out1[1]" LOC="p34";

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

OUTPUT: Logic_unit 1 1 1 1 S1 0 0 1 1 S0 0 1 0 1 OUTPUT A&B A|B A^B A^(~B)

PROCEDURE: 1. Write the coding. 2. Use Xilinx ISE simulator and run. 3. Note the output and verify.

RESULT: Thus a ALU is simulated in Verilog and implemented using Spartan3 FPGA kit

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

EXPT NO: DATE:

ECHO CANCELLATION
AIM: To perform echo cancellation using MATLAB SOFTWARE REQURIED: pc with MATLAB PROGRAM: clear all; mule =0.01; max_run=200; for run =1:max_run; taps=20; freq=2000; w=zeros(1,taps); time=0.2; samplerate=8000; samples=time*samplerate; max_iterations=samples-taps+1; iterations=1:max_iterations; t=1/samplerate:1/samplerate:time; rand('state',sum(100*clock)); noise=0.02*rand(1,samples); s=.4*sin(2*pi*freq*t); x=noise+s; echo_amp_per=.4; %rand('state',sum(100*clock)); echo_time_delay=.064; echo_delay=echo_time_delay*samplerate; echo=echo_amp_per*[zeros(1,echo_delay) x(echo_delay+1:samples)]; for i=1:max_iterations;

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

y(i)=w*x(i:i+taps-1)'; e(run,i)=echo(i)-y(i); %mule(i)=0.5/(x(i:i+taps-1)*x(i:i+taps-1)'+0.01); w=w+2*mule*e(run,i)*x(i:i+taps-1); end end mse=sum(e.^2,1)/max_run; b=x+echo; out=b(1:length(y))-y; subplot(3,1,1),plot(b); title('signal and echo'); ylabel('amp'); xlabel('time sec'); subplot(3,1,2),plot(b); title('output of the system'); ylabel('amp'); xlabel('time sec'); subplot(3,1,3),semilogy(mse); grid title('learning curve mu= 0.01 echo delay= 64ms runs =200'); ylabel('estimated MSE, db'); xlabel('number of iterations'); %subplot(3,1,2), semilogy(iterations,e(1,:).^2); %grid %subplot(3,1,3), semilogy(iterations,e(2,:).^2);; %grid

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.

OUPUT:

PROCEDURE:

1. Write the coding. 2. Use Mat lab and run. 3. Note the output and verify.

RESULT: Thus echo cancellation using MATLAB has been executed successfully.

SRIRAM ENGINEERING COLLEGE, PERUMALPATTU-602024.