MOS: Electrical properties

Threshold Voltage
V
t
is V
gs
for which the channel starts to invert
Threshold Voltage
V
t
= |
ms
+ (Q
B
- Q
SS
Q
OX
)/C
OX
+ 2|
fn
Where, |
ms
= work function difference between gate and Si
Q
B
= Charge in depletion layer per unit area beneath the oxide
Q
SS
= surface state charge density at Si- SiO
2
interface
Q
OX
= Oxide charge density (located at Si- SiO
2
interface)
C
ox
= gate capacitance per unit area
|
fn
= Fermi level potential between inverted surface and bulk Si
Now, Q
B
= 2c
0
c
si
qN(V
SB
+2 |
fn
)
where, c
0
= permittivity of free space
c
si
= relative permittivity of silicon
q = electron charge (=1.6 10
-19
coulomb)
N= impurity concentration in the substrate
V
SB
= substrate bias voltage [(-ve )w.r.t. source for NMOS (PMOS)]
Ideal models assume V
t
is constant
Really depends (weakly) on almost everything else:
Body voltage: Body Effect
Drain voltage: Drain-Induced Barrier Lowering
Channel length: Short Channel Effect
Threshold Voltage
Body Effect
Body is a fourth transistor terminal
V
sb
affects the charge required to invert the channel
Increasing V
s
or decreasing V
b
increases V
t
|
s
= surface potential at threshold
Depends on doping level N
A
And intrinsic carrier concentration n
i
= body effect coefficient
( )
0 t t s sb s
V V V | | = + +
2 ln
A
s T
i
N
v
n
| =
si
ox
si
ox ox
2q
2q
A
A
N
t
N
C
c
c
c
= =
DIBL (Drain-Induced Barrier Lowering)
Electric field from drain affects
channel
More pronounced in small transistors
where the drain is closer to the
channel
Drain-Induced Barrier Lowering
Drain voltage also affect V
t
High drain voltage causes current to
increase.
t t ds
V V V q
'
=
Short Channel Effect
In small transistors, source/drain depletion
regions extend into the channel
Impacts the amount of charge required to invert
the channel
And thus makes V
t
a function of channel length
Short channel effect: V
t
increases with L
Some processes exhibit a reverse short channel
effect in which V
t
decreases with L
Capacitance
Any two conductors separated by an insulator
have capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion
Gate Capacitance
Approximate channel as connected to source
C
gs
= c
ox
WL/t
ox
= C
ox
WL = C
permicron
W
C
permicron
is typically about 2 fF/m
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9c
0
)
polysilicon
gate
Diffusion Capacitance
C
sb
, C
db
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to C
g
for contacted diff
C
g
for uncontacted
Varies with process
MOSFET Capacitances
MOSFET
Capacitances
Overlap
Capacitance
Gate
Resistance
Components of C
in
and C
out
g
m
= oI
ds
/oV
gs
with V
ds
constant
Now, I
ds
= Q
channel
/t,
where t=Time for carrier to
cross channel = L
2
/ V
ds
Thus, change in I
ds
=oI
ds
=oQ
channel
/t = oQ
channel
V
ds
/L
2
We also know that, Q
channel
= C
gs
V
gc
Change in charge= oQ
channel
= C
gs
oV
gc
= C
gs
oV
gs
(as oV
gc
= oV
gs
)
Thus, oI
ds
=oQ
channel
/t = C
gs
oV
gs
V
ds
/L
2
g
m
= oI
ds
/oV
gs
= C
gs
V
ds
/L
2
= C
gs
(V
gs
-V
t
)/L
2
(for saturation, as V
ds
= V
gs
-V
t
)
As C
gs
=
ox

0
WL/ t
ox
, g
m
=
ox

0
W (V
gs
-V
t
)/L t
ox
= (V
gs
-V
t
)
By increasing width, g
m
may be increased, but that also increases input capacitance and area
Transconductance (g
m
)
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
In saturation, I
ds
= C
ox
(W/L) (V
gs
V
t
)
2
/2
= (V
gs
V
t
)
2
/2
where = C
ox
(W/L)
Current /area = I
ds
/ (WL) = C
ox
(V
gs
V
t
)
2
/2L
2
We obtained, g
m
= (V
gs
-V
t
)
g
m
= (2)
1/2
(I
ds
)
1/2
Transconductance (g
m
)
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
g
m
(for bipolar transistor) = I
C
/(kT/q)
where I
C
= collector current = I
s
exp(qV
be
/kT)
q = electron charge (=1.6 10
-19
coulomb)
k = Boltzmans constant
T= Temperature in
0
K
The expression can be rewritten in the form
g
m
(for bipolar transistor) o A
e
exp(qV
be
/kT)
where V
be
= base to emitter voltage
A
E
= emitter area
Transconductance (g
m
) - bipolar
Comparison of some parameters
bipolar versus MOS
MOS Bipolar
1. I
ds
= (V
gs
V
t
)
2
/2 1. I
C
= I
s
exp(qV
be
/kT)
2. g
m
= (2)
1/2
(I
ds
)
1/2
2. g
m
= I
C
/(kT/q)
3. g
m
= (V
gs
-V
t
) 3. g
m
o A
e
exp(qV
be
/kT
4. g
m
is dependent on process,
dependent on area
4. g
m
is independent on process ,
weak function of area
CMOS Bipolar technology
- Low static power dissipation
- High input impedance (low drive
current)
- High noise margin
- Medium speed high voltage swing
- High packing density
- High delay sensitivity to load (fan-out
limitations)
- Low output drive current
- Low transconductance (output current
changes slowly with change in V
in
: g
m
o V
in
)
- Bidirectional capability (drain and
source interchangeable)
- A near ideal switching device
- Mask levels 12 to 16
- High power dissipation
- Low input impedance (high drive
current)
- Medium noise margin
- High speed low voltage swing
- Low packing density
- Low delay sensitivity to load
- High output drive current
- Low transconductance (output
current changes rapidly with
change in V
in
: g
m
o e
Vin
)
- Essentially unidirectional with hole
as carrier
- Not ideal switching device
- Mask levels 12 to 20
BiCMOS
A known deficiency of MOS technology is its limited load driving
capabilities (due to limited current sourcing and sinking abilities of
pMOS and nMOS transistors.
Bipolar transistors have
higher gain
better noise characteristics
better high frequency characteristics
BiCMOS gates can be an efficient way of speeding up VLSI circuits
CMOS fabrication process can be extended for BiCMOS
Example Applications
CMOS - Logic
BiCMOS - I/O and driver circuits
ECL - critical high speed parts of the system
Evolution of BiCMOS from CMOS
BiCMOS technologies have tended to evolve from CMOS processes in order to
obtain the highest CMOS performance possible.
The bipolar processing steps have been added to the core CMOS flow to
realize the desired device characteristics.
BiCMOS Technology
Bi-CMOS combines CMOS and bipolar (another transistor
type) on one chip
CMOS for logic circuits
Bi-polar to drive larger electrical circuits off the chip
Advantages of BiCMOS Technology
Improved speed over CMOS
Lower power dissipation than Bipolar
Flexible input/outputs
High performance analog
Latch up immunity
V
DD
V
in
V
out T
3
T
4
T
2
T
1
C
L
GND
- Output logic levels are close to rail voltages
- High input impedance
- Low output impedance
-During saturation of T
1
and T
2
, low impedances charge or discharge C
L
rapidly
- High current drive capability, but relatively small area
- High noise margins
At V
in
= 0 volts (GND)
- T
3
off, T
1
non-conducting
- T
4
on, T
2
conducting (current source)
- C
L
is charged towards +5 volt
- V
out
= V
DD
- V
BE
of T
2
At V
in
= 5 volts (V
DD
)
- T
4
off, T
2
non-conducting
- T
3
on, T
1
conducting (current sink)
- C
L
is discharged towards 0 volt
- V
out
= V
CEsat
of T
1
BICMOS Inverter
BICMOS: Adding NPN Bipolar Transistor
The simplest way to add an NPN bipolar transistor to the previous CMOS structure
is by using PMOS N-well as the collector of the Bipolar device and introducing an
additional mask level for the P-base region.
the N+ source/drain ion implantation step is used for the emitter and collector
contact of the bipolar structure
the P+ source/drain ion implantation step is used to create a P+ base contact to
minimize the base series resistance
V
DD
V
in
V
out T
3
T
4
T
2
T
1
C
L
GND
Problems:
-At V
in
= logic 1, significant static
current flows (a DC path exists
from V
DD
to GND)
- No discharge path from base of
T
1
and T
2
when they are turned
off (slows down)
BICMOS Inverter
V
DD
V
in
V
out
T
3
T
4
T
2
T
1
C
L
GND
DC path through T
3
and T
1
is
eliminated
(With no static current flow)
BICMOS Inverter
V
DD
V
in
V
out
T
3
T
4
T
2
T
1
C
L
GND
Resistors provide improved
swing of output voltage when
each bipolar transistor is off
Also provides discharge paths
for base current during turn off
Problems:
At V
in
= 5 volts (V
DD
)
V
out
= V
BE
of T
1
The output voltage swing is
reduced
V
DD
V
in
V
out
T
3
T
4
T
2
T
1
C
L
GND
R
1
R
2
(With better output logic levels)
BICMOS Inverter
V
DD
V
in
V
out
T
3
T
4
T
2
T
1
C
L
GND
R
1
R
2
Problems:
Fabrication of resistors are not
convenient and also space
consuming
V
DD
V
in
V
out
T
3
T
4
T
2
T
1
C
L
GND
T
5
T
6
V
in
T
5
is turned on when T
2
is turned off
T
6
is turned on when T
1
is turned off
(An improved version)
CMOS Latchup
Due to large number of junctions, the consequent
presence of parasitic transistors and diodes
Latch up is a condition in which the parasitic
components give rise to the establishment of low
resistance conducting paths between V
DD
and V
SS
.
There are many safeguards that are done during
fabrication to suppress this, but it can still occur
under certain transient or fault conditions
CMOS Latchup
Latchup occurs due parasitic bipolar
transistors that exist in the basic inverter as
shown below
CMOS Latchup
Sufficient current flow causes enough voltage across R
p
to turn on npn transistor
Current will be drawn through R
n
For sufficient voltage developed, pnp will also turn on
Transition from
high to low
resistance
Latch up
current
Voltage
I
1
V
1
Remedies of CMOS Latchup
Increase in substrate doping levels with a consequent drop in value of R
p
Reducing R
n
by control of fabrication parameters and ensuring low contact
resistance to V
DD
BiCMOS Latchup Susceptibility
Reduction of both R
p
and R
n
Larger current needed to invite latch up
Beta of pnp transistor is reduced, that
decreases current