INTEGRATED CIRCUITS

DATA SHEET

74LVC163 Presettable synchronous 4-bit binary counter; synchronous reset

Product specication Supersedes data of 2003 June 02 2004 May 05

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

FEATURES Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standard JESD8-B/JESD36 Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Synchronous reset Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock. ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Specified from 40 C to +85 C and 40 C to +125 C. DESCRIPTION The 74LVC163 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC163 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a

74LVC163

HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pins CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the 1 formula: f max = ------------------------------------ . t PHL ( max ) + t su

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH CP to Qn CP to TC CET to TC fclk(max) CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION TYPE NUMBER 74LVC163D 74LVC163DB 74LVC163PW 74LVC163BQ TEMPERATURE RANGE 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C PINS 16 16 16 16 PACKAGE SO16 SSOP16 TSSOP16 DHVQFN16 maximum clock frequency input capacitance power dissipation capacitance per gate notes 1 and 2 PARAMETER propagation delay: CONDITIONS CL = 50 pF; VCC = 3.3 V 4.0 4.6 3.5 200 5.0 17

74LVC163

TYPICAL ns ns ns

UNIT

MHz pF pF

MATERIAL plastic plastic plastic plastic

CODE SOT109-1 SOT338-1 SOT403-1 SOT763-1

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

FUNCTION TABLE See note 1. OPERATING MODES Reset (clear) Parallel load Count Hold (do nothing) Note 1. * = the TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH). H = HIGH voltage level. h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition. L = LOW voltage level. l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition. INPUT MR l h h h h h CP X X CEP X X X h l X CET X X X h X l PE X l l h h h Dn X l h X X X

74LVC163

OUTPUT Qn L L H count qn qn TC L L * * * L

q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition. X = dont care. = LOW-to-HIGH clock transition. PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MR CP D0 D1 D2 D3 CEP GND PE CET Q3 Q2 Q1 Q0 TC VCC SYMBOL DESCRIPTION synchronous master reset (active LOW) clock input (LOW-to-HIGH, edge-triggered) data input data input data input data input count enable input ground (0 V) parallel enable input (active LOW) count enable carry input ip-op output ip-op output ip-op output ip-op output terminal count output supply voltage

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74LVC163

MR CP D0 D1 D2 D3 CEP GND

1 2 3 4

16 VCC 15 TC 14 Q0 13 Q1

terminal 1 index area CP D0 D1 D2 2 3 4 5 6 7

16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 CET PE 9

163
5 6 7 8
001aaa770

12 Q2 D3 11 Q3 10 CET GND 9 PE
001aaa740

GND(1) 8

CEP

Transparent top view

(1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input.

Fig.1 Pin configuration SO16 and (T)SSOP16.

Fig.2 Pin configuration DHVQFN16

handbook, halfpage handbook, halfpage

1 9 7

15 TC 3 4 5 6 9 D0 D1 D2 D3 PE CEP CET 7 10 CP 2 MR 1
MNA905

R M1 G3 G4

CTR4

Q0 Q1 Q2 Q3

14 13 12 11

10 2 3 4 5 6

C2 /1,3,4+ 1,2D 14 13 12 11 4 CT = 15
MNA906

MR

163

15

Fig.3 Logic symbol.

Fig.4 Logic symbol (IEEE/IEC).

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74LVC163

handbook, halfpage

3 D0

4 D1

5 D2

6 D3
handbook, halfpage

0 15

4 5 6 7

9 10 7 2 1

PE CET

PARALLEL LOAD CIRCUITRY

TC CEP CP MR BINARY COUNTER

15

14 13 12 11 10 9

8
MNA908

Q0 14

Q1 13

Q2 12

Q3
MNA907

11

Fig.5 Functional diagram.

Fig.6 State diagram.

handbook, full pagewidth

MR PE D0 D1 D2 D3 CP CEP CET Q0 Q1 Q2 Q3 TC 12 RESET PRESET 13 14 15 0 1 2 INHIBIT

MGU760

COUNT

Typical timing sequence: Reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit.

Fig.7 Timing sequence.

2004 May 05

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CET CEP

Philips Semiconductors

handbook, full pagewidth

Presettable synchronous 4-bit binary counter; synchronous reset counter; synchronous reset

D0

D1

D2

D3

7 7
PE MR D CP FF0 Q D FF1 Q D FF2 Q D FF3 Q CP Q CP Q CP Q CP Q

Product specication

74LVC163 74LVC163

Q0

Q1

Q2

Q3

TC
MGU761

Fig.8 Logic diagram.

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times in free air VCC = 1.2 V to 2.7 V VCC = 2.7 V to 3.6 V CONDITIONS for maximum speed performance for low-voltage applications MIN. 2.7 1.2 0 0 40 0 0

74LVC163

MAX. 3.6 3.6 5.5 VCC +125 20 10 V V V V

UNIT

C ns/V ns/V

LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = 40 C to +125 C; note 2 VI < 0 V note 1 VO > VCC or VO < 0 V note 1 VO = 0 V to VCC CONDITIONS 0.5 0.5 65 MIN. 0.5 MAX. +6.5 50 +6.5 50 VCC + 0.5 50 100 +150 500 V mA V mA V mA mA C mW UNIT

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = 40 C to +85 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = 100 A IO = 12 mA IO = 18 mA IO = 24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 12 mA IO = 24 mA ILI ICC ICC input leakage current quiescent supply current VI = 5.5 V or GND VI = VCC or GND; IO = 0 A 2.7 to 3.6 2.7 3.0 3.6 3.6 2.7 to 3.6 GND 0.1 0.1 5 0.2 0.4 2.7 to 3.6 2.7 3.0 3.0 VCC 0.2 VCC 0.5 VCC 0.6 VCC 0.8 VCC 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 VCC (V) MIN. TYP.(1)

74LVC163

MAX.

UNIT

V V V V V V V V V V V A A A

GND 0.8

0.55 5 10 500

additional quiescent VI =VCC 0.6 V; supply current per IO = 0 A input pin

2004 May 05

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = 40 C to +125 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = 100 A IO = 12 mA IO = 18 mA IO = 24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 12 mA IO = 24 mA ILI ICC ICC input leakage current quiescent supply current VI = 5.5 V or GND VI = VCC or GND; IO = 0 A 2.7 to 3.6 2.7 3.0 3.6 3.6 2.7 to 3.6 0.3 0.6 0.8 20 40 2.7 to 3.6 2.7 3.0 3.0 VCC 0.3 VCC 0.65 VCC 0.75 VCC 1 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 VCC (V) MIN.

74LVC163

TYP.(1)

MAX.

UNIT

V V V V V V V V V V V A A A

GND 0.8

additional quiescent VI =VCC 0.6 V; supply current per IO = 0 A input pin

5000

Note 1. Typical values are measured at VCC = 3.3 V and Tamb = 25 C.

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500 . CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = 40 C to +85 C; note 1 tPHL/tPLH propagation delay CP to Qn see Figs 9 and 14 1.2 2.7 3.0 to 3.6 propagation delay CP to TC see Figs 9 and 14 1.2 2.7 3.0 to 3.6 propagation delay CET to TC see Figs 10 and 14 1.2 2.7 3.0 to 3.6 tW tsu clock pulse width HIGH or LOW set-up time Dn to CP set-up time MR, PE to CP set-up time CEP, CET to CP th fmax tsk(0) hold time Dn, PE, CEP, CET to CP maximum clock pulse frequency skew see Fig.9 see Fig.12 see Fig.12 see Fig.13 see Figs 12 and 13 see Fig.9 note 3 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 1.5 1.5 1.5 1.5 1.5 1.5 5.0 4.0 3.0 2.5 3.5 3.0 5.5 5.0 0.0 0.5 150 150 18 4.0(2) 23 4.6(2) 16 3.5(2) 1.2(2) 1.0(2) 1.2(2) 2.1(2) 0.0(2) 200(2) VCC (V) MIN. TYP.

74LVC163

MAX.

UNIT

7.3 7.3 8.1 7.9 6.9 6.4 1.0

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = 40 C to +125 C tPHL/tPLH propagation delay CP to Qn see Figs 9 and 14 1.2 2.7 3.0 to 3.6 propagation delay CP to TC see Figs 9 and 14 1.2 2.7 3.0 to 3.6 propagation delay CET to TC see Figs 10 and 14 1.2 2.7 3.0 to 3.6 tW tsu clock pulse width HIGH or LOW set-up time Dn to CP set-up time MR, PE to CP set-up time CEP, CET to CP th fmax tsk(0) Notes 1. All typical values are measured at Tamb = 25 C. 2. Typical values are measured at VCC = 3.3 V. hold time Dn, PE, CEP, CET to CP maximum clock pulse frequency skew see Fig.9 see Fig.12 see Fig.12 see Fig.13 see Figs 12 and 13 see Fig.9 note 3 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 3.0 to 3.6 1.5 1.5 1.5 1.5 1.5 1.5 5.0 4.0 3.0 2.5 3.5 3.0 5.5 5.0 0.0 0.5 150 150 VCC (V) MIN. TYP.

74LVC163

MAX.

UNIT

9.5 9.5 10.5 10.0 9.0 8.0 1.5

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

AC WAVEFORMS

74LVC163

handbook, full pagewidth

1/fmax VI CP input GND tW t PHL VOH Qn, TC output VOL VM

MGU762

VM

VM

t PLH

VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load.

Fig.9

Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency.

V handbook, halfpage I CET input GND tPLH VOH TC output VOL VM VM

MGU763

VM

VM

tPHL

VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load.

Fig.10 Input (CET) to output (TC) propagation delays.

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74LVC163

handbook, full pagewidth

VI MR input GND th t su VI CP input GND VM

MGU764

VM

VM

th t su

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig.11 Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal times.

handbook, full pagewidth

VI PE input GND t su th VI CP input GND t su th VI Dn input GND

MGU765

VM

VM t su th

VM

VM

t su th

VM

VM

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig.12 Set-up and hold times for the input (Dn) and parallel enable input (PE).

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74LVC163

handbook, full pagewidth

VI CEP, CET input GND t su VI CP input GND VM VM

MGU766

VM

VM

th

t su

th

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig.13 CEP and CET set-up and hold times.

VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL

mna616

VCC 1.2 V 2.7 V 3.0 V to 3.6 V Note VCC

VI

CL 50 pF 50 pF 50 pF

RL 500 (1) 500 500

VEXT tPLH/tPHL tPZH/tPHZ open open open GND GND GND tPZL/tPLZ 2 VCC 2 VCC 2 VCC

2.7 V 2.7 V

1. The circuit performs better when RL = 1000 .

Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig.14 Load circuitry for switching times.

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm

74LVC163

SOT109-1

A X

c y HE v M A

Z 16 9

Q A2 A1 pin 1 index Lp 1 e bp 8 w M L detail X (A 3) A

2.5 scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3

0.010 0.057 0.069 0.004 0.049

0.019 0.0100 0.39 0.014 0.0075 0.38

0.244 0.041 0.228

0.028 0.004 0.012

8o o 0

ISSUE DATE 99-12-27 03-02-19

2004 May 05

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74LVC163

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

A X

c y HE v M A

Z 16 9

Q A2 A1 pin 1 index Lp L 1 bp 8 w M detail X (A 3) A

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 o 0
o

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

2004 May 05

17

Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74LVC163

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

c y HE v M A

16

Q A2 pin 1 index A1 Lp L (A 3) A

1
e bp

8
w M detail X

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

74LVC163

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm

A A1 E c

terminal 1 index area

detail X

terminal 1 index area e 2 L

e1 b 7 v M C A B w M C y1 C

C y

1 Eh 16

8 e 9

15 Dh

10 X 2.5 scale 5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27

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Philips Semiconductors

Product specication

Presettable synchronous 4-bit binary counter; synchronous reset

DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION

74LVC163

This data sheet contains data from the objective specication for product development. Philips Semiconductors reserves the right to change the specication in any manner without notice. This data sheet contains data from the preliminary specication. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specication without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specication. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notication (CPCN).

II

Preliminary data Qualication

III

Product data

Production

Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status Production), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

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Philips Semiconductors a worldwide company

Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales ofces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2004

SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

R20/05/pp21

Date of release: 2004

May 05

Document order number:

9397 750 13116