Beruflich Dokumente
Kultur Dokumente
assume cs:code,ds:code
code segment
org 1000h
mov si,1200h
mov di,2000h
mov cx,04h
cld
loop1:mov sb
loop1,
org 1200h
db ‘ABCD’
code ends
end
mov dptr,#FFCE
mov A, 36
movx @dptr,A
mov A,#0A
mov dptr,#FFC8
movx @dptr,A
mov A,#00
movx @dptr,A
sjmp 410F
Addition Subtraction
clr c clr c
mov A,#33h mov A,#33h
addc A,#21h subb A,#21h
mov dptr,#4150h mov dptr,#4150h
mov @dptr,A mov @dptr,A
sjmp 4209 sjmp 4209
Interfacing IC 8279
ORG 4100H
MVI A,00
OUT C2
MVI A,CC
OUT C2
MVI A,90
OUT C2
MVI A,88
OUT DAT-FF
MVI A,FF
OUT C0
OUT C0
OUT C0
OUT C0
HLT
Interfacing IC 8253(Generation of square wave)
MVI A,36
OUT CC
MVI A,0A
OUT C8
MVI A,00
OUT C8
HLT
MVI A,10
OUT C8
MVI A,18
OUT C8
MVI A,01
OUT D0
XRA A
XRA A
XRA A
MVI A,00
OUT D0
loop IN D8
ANI 01
CPI 01
JNZ loop
IN C0
STA 4150
HLT
TRANSMITTER
MVI A,36
OUT C6
MVI A,0A
OUT C8
MVI A,00
OUT C8
MVI A,4E
OUT C2
MVI A,37
OUT C2
loop JZ C2
ANI 04
JZ loop
MVI A,41
OUT C0
RST 1
RECEIVER
MVI A,36
OUT C6
MVI A,0A
OUT C8
MVI A,00
OUT C8
MVI A,4E
OUT C2
MVI A,37
OUT C2
IN C2
ANI 02
IN C0
STA 4150
RST 1
STEPPER MOTOR
TRANSMITTER
MVI A,84
OUT C6
MVI A,data
OUT C2
HLT
RECEIVER
MVI A,9B
OUT C6
IN C2
STA 4150
HLT
Sorting Of Numbers
assume cs:code,ds:code
code segment
org 1000h
mov si.1200h
mov cl,[si]
dec cl
inc si
loop: cmp al,[si]
jc loop1
mov al,[si]
loop:inc si
dec cl
jnz loop
mov si,1500h
mov [si],al
hlt
code ends
end
Searching Of Numbers
assume cs:code,ds:code
code segment
org 1000h
mov si.1200h
mov di,1500h
mov cl,[si]
inc si
mov al,[si]
inc si
loop: cmp al,[si]
jz loop1
inc si
dec cl
jnz loop
loop1:mov bl,[si]
mov [di],bl
hlt
code ends
end
8 Bit Addition
MVI C,03
LXI H,4150
MOV A,M
INX H
ADD M
DCR C
JNZ 4106
STA 4200
HLT
8 Bit Subtraction
LDA 4201
MOV B,A
LDA 4200
MVI C,00
SUB B
JNC loop
INR C
CNR
ADI 01
STA 4202
MOV A,C
STA 4203
HLT
8 Bit Multiplication
LDA 4200
MOV B,A
LDA 4201
MOV C,A
DEC B
ADD C
DEC B
Loop JNC loop
STA 4202
HLT
8 Bit Division
LDA 4200
MOV B,A
LDA 4201
MVI C,00
CMP B
JC loop
SUB B
INR C
JMP loop1
STA 4202
MOV A,C
STA 4203
HLT
16 Bit Addition
LHLD 4200
XCHG
LHLD 4202
DAD D
SHLD 4204
HLT
16 Bit Subtraction
LHLD 4200
XCHG
LHLD 4202
MOV A,E
SUB L
MOV L,A
MOV A,D
SUB H
MOV H,A
SHLD 4204
HLT
16 Bit Multiplication
LHLD 4200
SPHL
LHLD 4202
XCHG
LXD H,0000
loop DAD SP
DCX D
MOV A,E
ORA D
JNZ loop
SHLD 4204
HLT
Arrange in Ascending
LDA 4200
MOV B,A
DCR B
loop3 LXI H,4200
MOV B,A
DCR C
INX H
loop2 MOV A,M
INX H
CMP M
JC loop1
MOV D,M
MOV M,A
DCX H
MOV M,D
INX H
loop1 DCR C
JNZ loop2
DCR B
JNZ loop3
HLT
LXI H,4200
MOV A,M
MVI C,05
loop1 INX H
CMP M
JNC loop2
MOV A,M
loop2 DCR C
JNZ loop1
STA 4250
HLT
Digital Clock
MVI A,80
OUT C6
MVI H,02
MVI L,00
start MVI D,3D
XRA A
next OUT C2
INR A
DAA
MVI E,02
loop3 MVI B,FF
loop2 MVI C,FF
loop1 DCR C
JNZ loop1
DCR B
JNZ loop2
DCR E
JNZ loop3
DCR D
JNZ next
XRA A
OUT C2
INR L
MOV A,L
OUT C4
DCR H
JNZ start
HLT