11/5/2011

Basic Components of Digital Computer

Embedded Processors

CPU Memory I/O

Memory CPU I/O

Could be a chip, a board, or several boards

Microcontrollers
Memory CPU

ROM

RAM

I/O Subsystems: Timers, Counters, Analog Interfaces, I/O interfaces A single chip

Ampros Encore 400 board

Why Use an Integrated Processor?

Increase in performance because they no longer have to deal with the latencies involved with transmitting data over buses between processors. Fewer board components, simplifies the entire board design, simpler to debug Less power requirements Fewer components and lower power, result in a smaller and cheaper board. Less flexibility in adding, changing, or removing functionality

Architecture
Embedded processors can be categorized into two "groups based on 1. H/W and 2. Instruction set based architecture. Architecture's instruction set are commonly referred to as the Instruction Set Architecture or ISA. ISA: operations code (opcode) are used to create programs for that architecture, the operands (data) that are accepted and processed by an architecture, storage, addressing modes are used to gain access to and process operands, and the handling of interrupts.

11/5/2011

Operations code
Operations codes are unique for each instructions that execute certain commands. Different processors can execute the exact same operations using a different types of instructions. An ISA typically defines the types and formats of operations.

Types of Operations
Operations are the functions that can be performed on the data: Computations (math operations), Movement (moving data from one memory location/register to another), Branches (conditional/unconditional moves to another area of code to process), Input/output operations (data transmitted between I/O components and master processor), Context switching operations (where location register information is temporarily stored when switching to some routine ).

Common operations defined in an ISA

Math and Logical Shift/Rotate

Operation Formats
The format of an operation is the actual number and combination of bits (l's and 0's) that represent the operation, and is commonly referred to as the operation code or opcode. MPC823 opcodes, for instance, are structured the same and are all 6 bits long (063 decimal) An architecture can have several instruction set formats

Add Subtract Multiply Divide AND OR XOR

Logical Shift Right Logical Shift Left Rotate Right Rotate Left

Compare Instructions.. Move Stack Instructions... PUSH Branch Stack POP Instructions ... Load Store

Load/Store

MIPS32/MIPS I CMP and ADD operation sizes and locations

Operands
Operands are the data that operations manipulate. An ISA defines the types and formats of operands for a particular architecture. the ISA defines simple operand types of bytes (8 bits), halfwords (16 bits), and words (32 bits). More complex data types such as integers, characters, or floating point are based on the simple types

Storage/ A. The organization of memory used to store operands.

Memory is simply an array of programmable storage that stores data, including operations, operands, and so on. The indices of this array are locations referred to as memory addresses The actual physical or virtual range of addresses available to a processor is referred to as the address space. how data is stored in memoryThe two byte ordering approaches are bigendian, in which the most significant byte or bit is stored first, and littleendian, in which the least significant bit or byte is stored first.

Simple operand types

11/5/2011

ISA defines specific characteristics of the address space

Linear. A linear address space is one in which specific memory locations are represented incrementally, typically starting at "0" thru 2N1. Segmented. A segmented address space is a portion of memory that is divided into sections called segments. Specific memory locations can only be accessed by specifying a segment identifier, a segment number that can be explicitly defined or implicitly obtained from a register, and specifying the offset within a specific segment within the segmented address space. Containing any special address regions.

Storage/ B. Register Set

A register is simply fast programmable memory normally used to store operands that are immediately or frequently used. A processor's set of registers is commonly referred to as the register set or the register file. Different processors have different register sets, and the number of registers in their sets vary between very few to several hundred (even over a thousand). For example, the SA1110 register set has 37 32 bit registers, whereas the MPC823, on the other hand, has about a few hundred registers (general purpose, special purpose, floating point registers, etc.).

Storage/ C. How Registers Are Used

An ISA defines which registers can be used for what transactions, such as special purpose, floating point, and which can be used by the programmer in a general fashion (general purpose registers). one of many ways processors can be referenced is according to the size (in bits) of data that can be processed and the size (in bits) of the memory space that can be addressed in a single instruction by that processor.. Commonly used embedded processors support 4 bit, 8bit, 16bit, 32bit, and/or 64bit processing. Some processors can process larger amounts of data and can access larger memory spaces in a single instruction, such as 128bit architectures, but they are not commonly used in embedded designs.

Addressing Modes
Addressing modes define how the processor can access operand storage. The usage of registers is partly determined by the ISA's Memory Addressing Modes. The two most common types of addressing mode models are the: Load-Store Architecture, which only allows operations to process data in registers, not anywhere else in memory. For example, the PowerPC architecture has only one addressing mode for load and store instructions: register plus displacement (supporting register indirect with immediate index, register indirect with index, etc.). Register-Memory Architecture, which allows operations to be processed both within registers and other types of memory. Intel's i960 Jx processor is an example of an addressing mode architecture that is based upon the registermemory model (supporting absolute, register indirect, etc.).

Interrupts and Exception Handling

Interrupts are mechanisms that stop the standard flow of the program in order to execute another set of code in response to some event, such as problems with the hardware, resets, and so forth. The ISA defines what if any type of hardware support a processor has for interrupts.

Application-Specific ISA Models

Applicationspecific ISA models define processors that are intended for specific embedded applications, such as processors made only for TVs. There are several types of applicationspecific ISA models implemented in embedded processors, the most common models being: Controller Model Datapath Model Finite State Machine with Datapath (FSMD) Model Java Virtual Machine (JVM) Model

11/5/2011

Controller Model
The Controller ISA is implemented in processors that are not required to perform complex data manipulation, such as video and audio processors that are used as slave processors on a TV board

Data-path Model
The Datapath ISA is implemented in processors whose purpose is to repeatedly perform fixed computations on different sets of data, a common example being digital signal processors (DSPs)

Analog TV board example with controller ISA implementations

Finite State Machine with Data-path (FSMD) Model

The FSMD ISA is an implementation based upon a combination of the Datapath ISA and the Controller ISA for processors that are not required to perform complex data manipulation and must repeatedly perform fixed computations on different sets of data. Common examples of an FSMD implementation are application specific integrated circuits (ASICs), programmable logic devices (PLDs), and fieldprogrammable gatearrays (FPGAs, which are essentially more complex PLDs).

Java Virtual Machine (JVM) Model

The JVM ISA is based upon one of the Java Virtual Machine standards, Sun Microsystem's Java Language. realworld JVMs can be implemented in an embedded system via hardware, such as aj80 and aj100 processors

Board example with FSMD ISA implementationsolid-state digital camcorder

JVM ISA implementation example

General-Purpose ISA models

Generalpurpose ISA models are typically implemented in processors targeted to be used in a wide variety of systems, rather than only in specific types of embedded systems. The most common types of generalpurpose ISA architectures implemented in embedded processors are: Complex Instruction Set Computing (CISC) Model Reduced Instruction Set Computing (RISC) Model

Microcontroller Architectures
Address Bus CPU Data Bus
2n Memory 0

Program + Data

Von Neumann Architecture

Address Bus CPU Fetch Bus

Program

Address Bus 0 Data Bus Data

Harvard Architecture

11/5/2011

Complex Instruction Set Computing (CISC) Model

The CISC ISA defines complex operations made up of several instructions. Common examples of architectures that implement a CISC ISA are Intel's x86 and Motorola/Freescale's 68000 families of processors.

Reduced Instruction Set Computing (RISC) Model

The RISC ISA usually defines: an architecture with simpler and/or fewer operations made up of fewer instructions. an architecture that has a reduced number of cycles per available operation.
Many RISC processors have only onecycle operations, whereas CISCs typically have multiple cycle operations. ARM, PowerPC, SPARC, and MIPS are just a few examples of RISCbased architectures.

CISC ISA implementation example

RISC ISA implementation example

Instruction-Level Parallelism ISA Models

Instructionlevel Parallelism ISA architectures are similar to generalpurpose ISAs, except that they execute multiple instructions in parallel, as the name implies. In fact, instructionlevel parallelism ISAs are considered higher evolutions of the RISC ISA, which typically has onecycle operations, one of the main reasons why RISCs are the basis for parallelism. Examples of instructionlevel parallelism ISAs include: Single Instruction Multiple Data (SIMD) Model Superscalar Machine Model Very Long Instruction Word Computing (VLIW) Model

Single Instruction Multiple Data (SIMD) Model

The SIMD Machine ISA is designed to process an instruction simultaneously on multiple data components that require action to be performed on them.

SIMD ISA implementation example

Superscalar Machine Model

The superscalar ISA is able to process multiple instructions simultaneously within one clock cycle through the implementation of multiple functional components within the processor.

The VLIW ISA defines an architecture in which a very long instruction word is made up of multiple operations. These operations are then broken down and processed in parallel by multiple execution units within the processor

Very Long Instruction Word Computing (VLIW) Model

Superscalar ISA implementation example

VLIW ISA implementation example(VLIW) Trimedia-based DTV board

11/5/2011

DSP ARCHITECTURES
DSP architecture is similar to Microprocessor but optimised with instruction set to perform signal processing operations. DSP architecture is modified Harvard architecture having separate memory for code and data but multiple address and data buses to accesses data at faster rate. This also has on chip ROM and RAM and has peripherals like ADC,DAC, DMA, Timers , communication interface similar to controllers It has H/w multipliers and adders to carry out multiply and accumulate operation. It has pipelining architecture for faster execution It has registers capable of holding floating point data. ability to complete several accesses to memory in a single instruction cycle

DSP architecture continued

Modern DSP has SIMD (Single instruction multiple data), VLIW (very long instruction word) and super scalar architecture integrated to achieve faster operation. Example: Architecture of TMS320C54x DSP One program bus, 3 data bus and 4 address bus 40 bit ALU including 40 bit barrel shift register and two 40 bit accumulator 17x17 bit multiplier with coupled 40 bit accumulator for multiply and accumulate operation. PLL based clock generator and other peripherals

Type of DSP Systems

Real-Time NonrealTime Resource Adequate Resource Limited Complexity Throughput Recursive Algorithms Nonrecursive Algorithms Data Dependent Data Independent Static Scheduling Dynamic Scheduling of Operations Control Dominated Data Dominated Irregular Regular/Modular

Design and Implementation Constraints

Fixed/Variable Throughput Resource Adequate/Limited Fixed/Multi Functional Design Resources Skilled Manpower Previous Design Experience Energy/Power Limited Product Family Size Design Reuse Volume (number of units) Platform Based Flexibility (Design modifications) CAD Tools Technology Independence

Standard DSPs
+ Standardized hardware structure + Emphasis on short design time + Flexible + Easy to modify/correct errors + Low cost due to the wide applicability of the hardware initial cost Low performance/throughput High power consumption The flexibility is not needed in many applications/overhead Not always costeffective

Application-Specific DSPs
+ Some IP protection + Some CAD tools available Inflexible Very difficult + Lower unit cost, but higher

Selection criteria for microprocessor

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. No. bits of ALU Addressing capacity of processor Data bus width Clock speed Memory availability and interface capacity Power consumption Computation capacity viz instruction set, instruction execution parallism, availability of cache memory Depending on application Software tools available Testing and debugging facility available Cost of the processor. Peripherals availability

+ Higher performance/throughput + Lower power consumption + Optimized

11/5/2011

Selection criteria for microcontroller

1. No. bits of ALU 2. 2. Speed of operation 3. CISC or RISC 4. Program storage architecture Harvard/ Princeton 5. Total internal and external memory available. 6. Cache and MMU availability. 7. Availability of resources viz Timer, EEPROM, RAM,FLASH, UART, WDT, PWM, ADC/DAC, MODAM, DSP ports with instruction set, N/W interface, Wireless and mobile interface, USB,PCI,IIC, CAN, JTAG, GPIB etc. 8. Cost 9. H/W and S/W integration

Continued
10. S/W tools availability 11. Testing and debugging tools availability

Selection criteria for DSP

1. Arithmetic format : Floating point or fixed point processor. 2. Data width: ALU operation capacity or data bus width. 3. Speed of operation: 4. Memory organisation: On chip memory (ROM and RAM) and external memory that can be connected and number of address and data bus for accessing memory. 5. Easy of development: support available from manufacturer viz data manual, software tools, prototype boards, programming tools etc.

continued
6. Multiprocessor support 7. Power consumption and management: power down mode, sleep mode and idle mode etc 8. Cost