Beruflich Dokumente
Kultur Dokumente
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DESCRIPTION
The LTC1407/LTC1407A are 12-bit/14-bit, 3Msps ADCs with two 1.5Msps simultaneously sampled differential inputs. The devices draw only 4.7mA from a single 3V supply and come in a tiny 10-lead MS package. A Sleep shutdown feature lowers power consumption to 10W. The combination of speed, low power and tiny package makes the LTC1407/LTC1407A suitable for high speed, portable applications. The LTC1407/LTC1407A contain two separate differential inputs that are sampled simultaneously on the rising edge of the CONV signal. These two sampled inputs are then converted at a rate of 1.5Msps per channel. The 80dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The devices convert 0V to 2.5V unipolar inputs differentially. The absolute voltage swing for CH0+, CH0, CH1+ and CH1 extends from ground to the supply voltage. The serial interface sends out the two conversion results in 32 clocks for compatibility with standard serial interfaces.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6084440, 6522187.
3Msps Sampling ADC with Two Simultaneous Differential Inputs 1.5Msps Throughput per Channel Low Power Dissipation: 14mW (Typ) 3V Single Supply Operation 2.5V Internal Bandgap Reference with External Overdrive 3-Wire Serial Interface Sleep (10W) Shutdown Mode Nap (3mW) Shutdown Mode 80dB Common Mode Rejection at 100kHz 0V to 2.5V Unipolar Input Range Tiny 10-Lead MS Package
APPLICATIONS
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Telecommunications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control I and Q Demodulation Industrial Control
BLOCK DIAGRAM
10F 3V 7 CH0+ 1
+
S AND H
THD 2nd
CH0
SDO
CH1+
+
S AND H
CH1
14-BIT LATCH
3rd
10 TIMING LOGIC
CONV
3 10F 6 11
EXPOSED PAD
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PIN CONFIGURATION
TOP VIEW CH0+ CH0 VREF CH1+ CH1 1 2 3 4 5 10 9 8 7 6 CONV SCK SDO VDD GND 11
Supply Voltage (VDD) .................................................4V Analog Input Voltage (Note 3) ..... 0.3V to (VDD + 0.3V) Digital Input Voltage .................... 0.3V to (VDD + 0.3V) Digital Output Voltage ................. 0.3V to (VDD + 0.3V) Power Dissipation ...............................................100mW Operation Temperature Range LTC1407C/LTC1407AC ............................. 0C to 70C LTC1407I/LTC1407AI ........................... 40C to 85C LTC1407H/LTC1407AH ....................... 40C to 125C Storage Temperature Range...................65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
MSE PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150C, JA = 40C/W EXPOSED PAD (PIN #) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC1407CMSE#PBF LTC1407IMSE#PBF LTC1407HMSE#PBF LTC1407ACMSE#PBF LTC1407AIMSE#PBF LTC1407AHMSE#PBF TAPE AND REEL LTC1407CMSE#TRPBF LTC1407IMSE#TRPBF LTC1407HMSE#TRPBF LTC1407ACMSE#TRPBF LTC1407AIMSE#TRPBF LTC1407AHMSE#TRPBF PART MARKING* LTBDQ LTBDR LTBDR LTAFE LTAFF LTAFF PACKAGE DESCRIPTION 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP TEMPERATURE RANGE 0C to 70C 40C to 85C 40C to 125C 0C to 70C 40C to 85C 40C to 125C
Consult LTC Marketing for parts specied with wider operating temperature ranges. *The temperature grade is identied by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specications, go to: http://www.linear.com/tapeandreel/
The l denotes the specications which apply over the full operating temperature range, otherwise specications are at TA = 25C. With internal reference, VDD = 3V.
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Offset Error Offset Match from CH0 to CH1 Gain Error Gain Match from CH0 to CH1 Gain Tempco (Notes 5, 17) (Notes 4, 17) (Note 17) (Notes 4, 17) (Note 17) Internal Reference (Note 4) External Reference
l
CONVERTER CHARACTERISTICS
CONDITIONS
l l l
MIN 12 2 10 5 30 5
LTC1407 LTC1407A LTC1407H LTC1407AH TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX 14 0.25 1 0.5 5 1 15 1 2 10 5 30 5 4 20 10 10 0.5 2 1 2 15 1 4 20 10 60 10 12 2 20 5 40 5 0.25 1 0.5 5 1 15 1 2 20 5 40 5 14 4 30 10 10 0.5 2 1 2 15 1 4 30 10 80 10
60 10
80 10
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LTC1407/LTC1407A
The l denotes the specications which apply over the full operating temperature range, otherwise specications are at TA = 25C. With internal reference, VDD = 3V.
SYMBOL PARAMETER VIN VCM IIN CIN tACQ tAP tJITTER tSK CMRR Analog Differential Input Range (Notes 3, 9) Analog Common Mode + Differential Input Range (Note 10) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Sample-and-Hold Aperture Skew from CH0 to CH1 Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V (Note 6)
l l
ANALOG INPUT
MIN
MAX
UNITS V V
1 13 39 1 0.3 200 60 15
A pF ns ns ps ps dB dB
DYNAMIC ACCURACY
SYMBOL PARAMETER SINAD Signal-to-Noise Plus Distortion Ratio
The l denotes the specications which apply over the full operating temperature range, otherwise specications are at TA = 25C. With internal reference, VDD = 3V.
CONDITIONS 100kHz Input Signal 750kHz Input Signal 750kHz Input Signal (H Grade) 100kHz Input Signal, External VREF = 3.3V, VDD 3.3V 750kHz Input Signal, External VREF = 3.3V, VDD 3.3V 100kHz First 5 Harmonics 750kHz First 5 Harmonics 750kHz First 5 Harmonics (H Grade) 100kHz Input Signal 750kHz Input Signal 1.25V to 2.5V 1.40MHz into CH0+, 0V to 1.25V, 1.56MHz into CH0. Also Applicable to CH1+ and CH1 VREF = 2.5V (Note 17) VIN = 2.5VP-P, SDO = 11585LSBP-P (3dBFS) (Note 15) S/(N + D) 68dB
l l
LTC1407/LTC1407H LTC1407A/LTC1407AH MIN TYP MAX MIN TYP MAX 68 67 70.5 70.5 70.5 72.0 72.0 87 83 82 87 83 82 0.25 50 5 77 76 70 69 73.5 73.5 73.5 76.3 76.3 90 86 85 90 86 82 1 50 5 80 79
THD
Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth
l l
SFDR IMD
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The l denotes the specications which apply over the full operating temperature range, otherwise specications are at TA = 25C. VDD = 3V.
CONDITIONS VDD = 3.3V VDD = 2.7V VIN = 0V to VDD
l l l
MIN 2.4
TYP
MAX 0.6 10
UNITS V V A pF V V V A pF mA mA
POWER REQUIREMENTS
SYMBOL VDD IDD PARAMETER Supply Voltage Supply Current
The l denotes the specications which apply over the full operating temperature range, otherwise specications are at TA = 25C. With internal reference, VDD = 3V.
CONDITIONS Active Mode, fSAMPLE = 1.5Msps Active Mode (LTC1407H/LTC1407AH) Nap Mode Nap Mode (LTC1407H/LTC1407AH) Sleep Mode (LTC1407/LTC1407H) Sleep Mode (LTC1407A/LTC1407AH) Active Mode with SCK in Fixed State (Hi or Lo)
l l l l
MIN 2.7
UNITS V mA mA mA mA A A mW
PD
The l denotes the specications which apply over the full operating temperature range, otherwise specications are at TA = 25C. VDD = 3V.
SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV t1 t2 t3 t4 t5 t6 PARAMETER Maximum Sampling Frequency per Channel (Conversion Rate) Minimum Sampling Period (Conversion + Acquisiton Period) Clock Period Conversion Time Minimum Positive or Negative SCLK Pulse Width CONV to SCK Setup Time SCK Before CONV Minimum Positive or Negative CONV Pulse Width SCK to Sample Mode CONV to Hold Mode (Note 16) (Note 6) (Note 6) (Notes 6, 10) (Note 6) (Note 6) (Note 6) (Notes 6, 11) CONDITIONS
l l l
TIMING CHARACTERISTICS
MIN 1.5
TYP
MAX
UNITS MHz
ns ns SCLK cycles ns ns ns ns ns ns
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LTC1407/LTC1407A
The l denotes the specications which apply over the full operating temperature range, otherwise specications are at TA = 25C. VDD = 3V.
SYMBOL t7 t8 t9 t10 t12 PARAMETER 32nd SCK to CONV Interval (Affects Acquisition Period) Minimum Delay from SCK to Valid Bits 0 Through 11 SCK to Hi-Z at SDO Previous SDO Bit Remains Valid After SCK VREF Settling Time After Sleep-to-Wake Transition CONDITIONS (Notes 6, 7, 13) (Notes 6, 12) (Notes 6, 12) (Notes 6, 12) (Notes 6, 14) MIN 45 8 6 2 2 TYP MAX UNITS ns ns ns ns ms
TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below GND or greater than VDD without latchup. Note 4: Offset and range specications apply for a single-ended CH0+ or CH1+ input with CH0 or CH1 grounded and using the internal 2.5V reference. Note 5: Integral linearity is tested with an external 2.55V reference and is dened as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The analog input range is dened for the voltage difference between CH0+ and CH0 or CH1+ and CH1. Note 9: The absolute voltage at CH0+, CH0, CH1+ and CH1 must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. Note 11: Not the same as aperture delay. Aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns CONV to Hold mode delay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage latch. Note 13: The time period for acquiring the input signal is started by the 32nd rising clock and it is ended by the rising edge of CONV. Note 14: The internal reference settles in 2ms after it wakes up from Sleep mode with one or more cycles at SCK and a 10F capacitive load. Note 15: The full power bandwidth is the frequency where the output code swing drops by 3dB with a 2.5VP-P input sine wave. Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read with an arbitrarily long clock period. Note 17: The LTC1407A is measured and specied with 14-bit resolution (1LSB = 152V) and the LTC1407 is measured and specied with 12-bit resolution (1LSB = 610V).
SINAD (dB)
3rd
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VDD = 3V, TA = 25C (LTC1407A) 748kHz Sine Wave 4096 Point FFT Plot
0 1.5Msps 10 20 MAGNITUDE (dB) 30 40 50 60 70 80 90 100 110 120
1.5Msps
100
600
700
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1403kHz Input Summed with 1563kHz Input IMD 4096 Point FFT Plot
0 10 20 30 MAGNITUDE (dB) 40 50 60 70 80 90 100 110 120 0 100 200 300 400 500 FREQUENCY (kHz) 600 700
1407 G06
Integral Linearity End Point Fit for CH0 with Internal 2.5V Reference
2.0 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 2.0 0 4096 12288 8192 OUTPUT CODE 16384
1407 G16
1.5Msps
Integral Linearity End Point Fit for CH1 with Internal 2.5V Reference
2.0 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 2.0 0 4096 12288 8192 OUTPUT CODE 16384
1407 G18
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CMRR vs Frequency
0 20 30 40 40 60 CH0 80 100 120 100 CH1 CROSSTALK (dB) 50 60
Crosstalk vs Frequency
1k
10M
100M
1407 G08
1k
1M
10M
1407 G09
PSSR vs Frequency
25 30 35 40 PSRR (dB)
CH0 CH1
1407 G11
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BLOCK DIAGRAM
10F 3V 7 CH0+ 1
LTC1407A
+
S AND H
CH0
CH1+
+
S AND H
CH1
14-BIT LATCH
SDO
10 TIMING LOGIC 9
CONV
3 10F 6 11
SCK
EXPOSED PAD
1407A BD
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t2
t3
33
34
SCK t5
t4
TIMING DIAGRAMS
CONV tACQ HOLD t10 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0 D10 12-BIT DATA WORD tCONV tTHROUGHPUT 12-BIT DATA WORD D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* X* Hi-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 t9 t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1 D1 D0 X* X* Hi-Z
1407A TD01
t6 HOLD t8
SAMPLE
SAMPLE t9
HOLD
t8
SDO
Hi-Z
D11
t2
t3
33
34
SCK t5
t4
CONV tACQ HOLD t10 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0 D12 14-BIT DATA WORD tCONV tTHROUGHPUT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z t9 t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1 D13 D12 D11 D10 D9 D8 D7 D6 14-BIT DATA WORD D5 D4 D3 D2 D1 D0 Hi-Z
1407A TD01
t6 HOLD t8
SAMPLE
SAMPLE t9
HOLD
t8
SDO
Hi-Z
D13
LTC1407/LTC1407A
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t1
CONV
NAP
t1
CONV
t1
NAP
SLEEP
t12
VREF
1407 TD02
VIH
SCK
VIH t9 90%
SDO 10%
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10
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11
ANALOG INPUT
51*
1 47pF* 2
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Figure 2
1k
10M
100M
1407 G08
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13
FS 1LSB
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POWER-DOWN MODES Upon power-up, the LTC1407/LTC1407A are initialized to the active state and are ready for conversion. The Nap and Sleep mode waveforms show the power-down modes for the LTC1407/LTC1407A. The SCK and CONV inputs control the power-down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1407/LTC1407A in Nap mode and the power drain drops from 14mW to 6mW. The internal reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC1407/LTC1407A for service very quickly and CONV can start an accurate conversion within a clock cycle.
Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC1407/LTC1407A in Sleep mode and the power drain drops from 14mW to 10W. To bring the part out of Sleep mode requires one or more rising SCK edges followed by a Nap request. Then one or more rising edges at SCK wake up the LTC1407/LTC1407A for operation. When Nap mode is entered after Sleep mode, the reference that was shut down in Sleep mode is reactivated. The internal reference (VREF ) takes 2ms to slew and settle with a 10F load. Using Sleep mode more frequently compromises the settled accuracy of the internal reference. Note that for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption.
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3V VDD 7
1407 F06
0V TO 3V LOGIC SWING
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of executable of incoming 1407A data of BSP buffer for clearing of result for clearing start of code
; ; ; ; ; ; ; ;
stop timer stop TDM serial port to AC01 set up iptr. Processor Mode STatus register init stack pointer. data page pointer to computed receive buffer. pointer to Buffered Serial Port receive buffer reset record counter ; Double clutch the initialization to insure a proper
; reset. The external frame sync must occur 2.5 clocks ; or more after the port comes out of reset.
breceive: ifr = #10h ; clear interrupt ags TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer if (NTC) goto bufull ; if this still the rst half get next half bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15)) return_enable
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dummy bsend return return_enable ;this is also a dummy return to dene bsend ;in vector table le BVECTORS.ASM end ISR .copy c:\dskplus\1407A\s2k14ini.asm ;initialize buffered serial port .space 16*32 ;clear a chunk at the end to mark the end
;====================================================================== ; ; VECTORS ; ;====================================================================== .sect vectors ;The vectors start here .copy c:\dskplus\1407A\bvectors.asm ;get BSP vectors .sect buffer .space 16*0x800 .sect result .space 16*0x800 .end ;Set address of BSP buffer for clearing ;Set address of result for clearing
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
*************************************************************************** File: BVECTORS.ASM -> Vector Table for the C54x DSKplus 10.Jul.96 BSP vectors and Debugger vectors TDM vectors just return *************************************************************************** The vectors in this table can be congured for processing external and internal software interrupts. The DSKplus debugger uses four interrupt vectors. These are RESET, TRAP2, INT2, and HPIINT. * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER * All other vector locations are free to use. When programming always be sure the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.
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nmi
trap2
;08; trap2
int0
;0C-3F: vectors for software interrupts 18-30 ;40; external interrupt int0
int1
int2
tint
brint
bxint
trint
txint
int3
hpiint
;64; HPIint
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21
; ; ; ; ; ; ; ;
places buffered serial port in reset programs BSPCE and ABU initializes transmit buffer start address initializes transmit buffer size initializes receive buffer start address initializes receive buffer size bring buffered serial port out of reset for transmit and receive because GO=0xC0
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2.794 (.110
0.102 .004)
0.889 (.035
0.127 .005)
0.29 REF
2.083 (.082
0.05 REF DETAIL B CORNER TAIL IS PART OF DETAIL B THE LEADFRAME FEATURE. FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 0.497 0.076 (.0196 .003) REF
10
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
4.90 0.152 (.193 .006) 0.254 (.010) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL A 0.18 (.007) SEATING PLANE 1.10 (.043) MAX DETAIL A 0 6 TYP 1 2 3 4 5
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.1016 (.004
0.0508 .002)
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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