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ADC (Analog to Digital Converter) Module for

FPGA Design
By botondkirei
Created 10/22/2008 - 21:17

Embedded ADC analog to digital converter FPGA fpga board fpga design

The Digilent Inc. from USA is a vendor for FPGA solutions. The portfolio of the company includes high
quality educational FPGA boards and adequate peripheral modules as ADCs and DACs.
This is equipped with the National Semiconductor’s ADCS7476MSPS 12-bit A/D converter providing up to
1 MSample/second on two independent channels. The analog input is conditioned by the 2 pole Sallen-Key
anti-alias filter. Due to its small size (0.95" x 0.80") and the 6-pin standard header it becomes suitable not
only for didactic use, but for some commercial applications also.
And now let’s focus on the FPGA interface. By opening the ADC datasheet, you will find out that it has a
standards SPI interface. Trough this you can introduce the samples for the further processing in the FPGA
design.
Some designers can get lucky and they already have some Intellectual Property for the SPI interface. They
don’t have anything to do just to instantiate this module in their design and the interfacing is done. But
some of the designers are not so lucky. They have to prepare themselves the ADC interface for DMA
controller or other industry standard bus.
My advice is to build an interface heaving the structure Form Fig. 1. This structure contains a buffer; on the
write side there is a state machine reading the samples and writing them to the buffer; on the read side
another state machine reads the samples and passes towards the interface.

Fig. 1. Suggested structure for interface

This buffer can be created by the development tools of the FPGA vendors. The Xilinx FPGAs design suite
is the ISE Foundation Software. Within this software anybody can find the Core Generator tool, which
allows us to generate the buffer core. The Altera FPGAs are also supported by core generator software,
which can be accessed form the Quartus II design environment.
The core generator software will provide a wrapper module for simulation purpose and synthesizable
structure for implementation. From the wrapper module the designer can easily learn the necessary
read/write interface of the buffer.

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ADC (Analog to Digital Converter) Module for FPGA Design http://dev.emcelettronica.com/print/52000

Using the specifications of the SPI interface and the buffer write side signals, the designer can build “State
Machine 1” from Fig. 1. The HDL designers find much easier to write directly the code in Verilog or VHDL.
To prepare the state machine there are other options also, by using state machine computer aided design
suites. One of them StateCAD, is included in Xilinx’ ISE Foundation Software.

Fig. 2. Diagram for “State Machine 1”

On Fig 2. the state diagram of “State Machine 1” is depicted. The ‘idle’ state waits for a transaction to begin.
The transaction is started by pulling the CS signal low (see the ADC converter datasheet). When the
transaction begins 16 bits are read from the SDA pin. This operation is accomplished by the ‘read_state’.
Finally the buffer write is done by the ‘buffer_write’ state. In this state the ‘bufwr’ signal is activated and
waits for the ‘bufer_write_ack’ signal to finish the transaction.

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