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Shift Registers

Using registers to store, manipulate and transfer data

Definition
A register is a digital circuit with two basic functions: Data Storage and Data Movement
A shift register provides the data movement function A shift register shifts its output once every clock cycle

A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs connected together in such a way that the data is shifted from one device to another when the circuit is active
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Shift Register Applications


communications
UART

some counter applications


Johnson counter ring counter LSFR counters

converting between serial data and parallel data temporary storage in a processor
scratch-pad memories

time delay devices more

some arithmetic operations


multiply, divide
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Shift Register Characteristics


Types
Serial-in, Serial-out Serial-in, Parallel-out Parallel-in, Serial-out Parallel-in, Parallel-out Universal

Direction
Left shift Right shift Rotate (right or left) Bidirectional

n-bit shift register

Data Movement
The bits in a shift register can move in any of the following manners

Data Movement
Block diagrams for shift registers with various input/output options:

n-bit shift register

n-bit shift register

n-bit shift register

n-bit shift register

Serial-In Serial-Out
Data bits come in one at a time and leave one at a time One Flip-Flop for each bit to be handled Movement can be left or right, but is usually only a single direction in a given register Asynchronous preset and clear inputs are used to set initial values
n-bit shift register

Serial-In Serial-Out
The logic circuit diagram below shows a generalized serial-in serial-out shift register
SR Flip-Flops are shown Connected to behave as D Flip-Flops Input values moved to outputs of each Flip-Flop with the clock (shift) pulse

N-Bit Shift Register


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Shift Registers
The simplest shift register is one that uses only Flip-Flops The output of a given Flip-Flop is connected to the D input of the Flip-Flop at its right. Each clock pulse shifts the contents of the register one bit position to the right. The Serial input (SI) determines what goes into the leftmost FlipFlop during the shift. The Serial output (SO) is taken from the output of the rightmost Flip-Flop.

Serial-In Serial-Out
A simple way of looking at the serial shifting operation, with a focus on the data bits, is illustrated at right The 4-bit data word 1011 is to be shifted into a 4-bit shift register One shift per clock pulse Data is shown entering at left and shifting right

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Serial-In Serial-Out
The diagram at right shows the 4-bit sequence 1010 being loaded into the 4-bit serial-in serialout shift register Each bit moves one position to the right each time the clocks leading edge occurs Four clock pulses loads the register
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Serial-In Serial-Out
This diagram shows the 4-bit sequence 1010 as it is unloaded from the 4bit serial-in serial-out shift register Each bit moves one position to the right each time the clocks leading edge occurs Four clock pulses unloads the register
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Serial-In Serial-Out
Serial-in, serial-out shift registers are often used for data communications
such as RS-232 modem transmission and reception Ethernet links SONET etc.

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Serial-In Serial-Out in VHDL


Following is the VHDL code for an 8-bit shift-right register with a positive-edge clock, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) = tmp(i); end loop; tmp(0) = SI; end if; end process; SO = tmp(7); end archi;

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Serial-to-Parallel Conversion
We often need to convert from serial to parallel
e.g., after receiving a series transmission
n-bit shift register

The diagrams at right illustrate a 4-bit serial-in parallel-out shift register Note that we could also use the Q of the right-most FlipFlop as a serial-out output

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Serial-to-Parallel Conversion
We would use a serial-in parallel-out shift register of arbitrary length N to convert an N-bit word from serial to parallel It would require N clock pulse to LOAD and one clock pulse to UNLOAD

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Serial-to-Parallel Conversion
These two shift registers are used to convert serial data to parallel data The upper shift register would grab the data once it was shifted into the lower register

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Parallel-to-Serial Conversion
We usa a Parallel-in Serial-out Shift Register The DATA is applied in parallel form to the parallel input pins PA to PD of the register It is then read out sequentially from the register one bit at a time from PA to PD on each clock cycle in a serial format One clock pulse to load Four pulses to unload
n-bit shift register

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Parallel-to-Serial Conversion
Logic circuit for a parallel-in, serial-out shift register

0 1 0 1

Mux-like

1
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Parallel-In Parallel-Out
Parallel-in Parallel-out Shift Registers can serve as a temporary storage device or as a time delay device The DATA is presented in a parallel format to the parallel input pins PA to PD and then shifted to the corresponding output pins QA to QD when the registers are clocked One clock pulse to load One pulse to unload

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Universal Shift Register


Universal shift register Can do any combination of parallel and serial input/output operations Requires additional inputs to specify desired function Uses a Mux-like input gating

n-bit shift register

L/S A B

L/S

0 1

A B

0 1

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Universal Shift Register


Parallel-in, parallel-out shift register

0
1

0
1

Mux-like

1
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Universal Shift Register


Parallel shift register (can serve as converting parallel-in to serial-out shifter):

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MSI Shift Registers


74LS164 is an 8-Bit Serial-In Parallel-Out Shift Register Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers

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MSI Shift Registers


74LS164 8-Bit Serial-In Parallel-Out Shift Register

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MSI Shift Registers


The 74LS164 is an edgetriggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B);
either of these inputs can be used as an active HIGH Enable for data entry through the other input an unused input must be tied HIGH, or both inputs connected together

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MSI Shift Registers


Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right This also enters into Q0 the logical AND of the two data inputs (AB) that existed before the rising clock edge.

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MSI Shift Registers


74LS164 logic diagram

A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.

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MSI Shift Registers


74LS166 is an 8-Bit Shift Register Parallel-in or serial-in
shift/load input establishes the parallel-in or serial-in mode

Serial-out Synchronous Load


Serial data flow is inhibited during parallel loading

Direct Overriding Clear

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MSI Shift Registers


74LS166 is an 8-Bit Shift Register

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MSI Shift Registers


74LS166 8-Bit Shift Register is a parallel-in or serial-in, serial-out shift register

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MSI Shift Registers


74LS166 is an 8-Bit Shift Register

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MSI Shift Registers


74LS166 is an 8-Bit Shift Register

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MSI Shift Registers


74LS194 4-Bit Bidirectional Universal Shift Register may be used in
serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel

data register transfers

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MSI Shift Registers


74LS194 4-Bit Bidirectional Universal Shift Register

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MSI Shift Registers


74LS194 control inputs S1 and S0

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MSI Shift Registers


74LS194 4-Bit Bidirectional Universal Shift Register

01

11

10

00

01

11

10

00

01

11

10

00

01

11

10

00

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MSI Shift Registers


74LS194 4-Bit Bidirectional Universal Shift Register

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Universal shift register 74x194


Shift left Shift right Load Hold

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MSI Shift Registers


One stage of the 74x194

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VHDL Dhift Register


Universal shift register design The 3-bit function select determines the operation of the register Serial in and Parallel load available
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Vshftreg is port (CLK, CLR, RIN, LIN: in STD_LOGIC; S: in STD_LOGIC_VECTOR (2 downto 0); -- function select D: in STD_LOGIC_VECTOR (7 downto 0); -- data in Q: out STD_LOGIC_VECTOR (7 downto 0) -- data out); end Vshftreg; architecture Vshftreg_arch of Vshftreg is signal IQ: STD_LOGIC_VECTOR (7 downto 0); begin process (CLK, CLR, IQ) begin if (CLR='1') then IQ <= (others=>'0'); elsif (CLK'event and CLK='1') then case CONV_INTEGER(S) is when 0 => null; when 1 => IQ <= D; when 2 => IQ <= RIN & IQ(7 downto 1); when 3 => IQ <= IQ(6 downto 0) & LIN; when 4 => IQ <= IQ(0) & IQ(7 downto 1); when 5 => IQ <= IQ(6 downto 0) & IQ(7); when 6 => IQ <= IQ(7) & IQ(7 downto 1); when 7 => IQ <= IQ(6 downto 0) & '0'; when others => null; end case; end if; Q <= IQ; end process; end Vshftreg_arch;

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Hold Load Shift Shift Shift Shift Shift Shift

right left circular right circular left arithmetic right arithmetic left

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MSI Shift Registers


74LS299 is an 8-bit universal shift/storage register with 3-state outputs Four modes of operation are possible:
hold (store) shift left shift right load data
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MSI Shift Registers


74LS299 universal shift/storage register

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MSI Shift Registers


74LS299 universal shift/storage register

S0 S1

CP CD

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MSI Shift Registers


74LS299 logic circuit diagram:
The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register.

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Serial Communications

A practical application of Registers / Shift Registers

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Serial data systems (e.g., TPC)

Read discussion and study circuits in text.


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Serial Data Transmission


Parallel-to-serial conversion for serial transmission
out: parallel data

in: parallel data

Source module

Destination module

serial transmission media


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Serial data in the phone system (E-1)


2.048 Mb/s links between phone switches and subscribers
partitioned into 32 64 Kb/s channels

Each channel gets a timeslot in a frame where it can send 8 bits every 125 sec.
8000 frames/sec

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Timeslot details

count = 255

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256

Parallel-to-serial conversion
LSBs are bit number

Assert shift-register LOAD input during bit 7


Timeslot number can be decoded and used to select source of parallel data

count = 255
Serial data to destination
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Synchronize destinations counter to sources

Serial-toparallel conversion
Detect that a complete byte has been received Holding register for complete byte
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Note: loads 00

Shift in serial data

Destination timing

Grab complete byte when available Holding-register outputs Serial-in, parallel-out shift register outputs
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Serial communication on ONE wire


Serial communication requires three signals: CLOCK, SYNC, and DATA. Yet only one wire is used. How? One solution: Manchester code.

Or use a phase-locked loop (analog circuit) to extract clock from the data:

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Still a couple of problems


Framing -- SYNC signal
Solution: Use a unique data pattern for SYNC

PLL clock recovery -- what if too many zeroes are transmitted? PLL cant stay in sync.
Solution: Use a code that guarantees a minimum number of ones Phone system: Map 00000000 --> 00000010 (creating slight voice distortion)

Gigabit Ethernet: Uses 8B10B code, solving both problems


Map each byte into 8 bits Use only a good subset of 210 code words Use another code word for synchronization
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Assignments
Completed Part 2 Midterm problems due Wednesday Continue working on the MIPS project
Description available on the course web page

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