Sie sind auf Seite 1von 16

Complementary MOS (CMOS) Inverter

Concept: transistor switches connect output either to V DD or to ground

INPUT

HIGH

V DD V DD V DD V IN OUTPUT INPUT OUTPUT LOW LOW HIGH +
V DD
V DD
V DD
V IN
OUTPUT
INPUT
OUTPUT
LOW
LOW
HIGH
+
C L
V OUT
C L
C L
(a)
(b)
(c)

Practical realization: connect input to gate of p-channel device.

V IN = V DD --> V SG2 = V DD - V IN = 0 < - V Tp --> cutoff

V IN = 0 --> V SG2 = V DD - V IN = V DD >> - V Tp --> on (triode region)

Graphical analysis: need to find family of load lines since input is connected to gate of M 2

EE 105 Spring 1997 Lecture 11

p-Channel MOSFET Characteristics

p-channel MOS load device:

V SGp = V DD - V IN

as V IN increases , the source-gate voltage V SGp decreases .

V IN

V DD

+ V SGp _ + _
+
V SGp
_
+
_

+

V SDp = v SUP

_

- I Dp = i SUP

note that the bulk connection is tied to the source ( V DD ), which results in a constant threshold voltage.

EE 105 Spring 1997 Lecture 11

Switchable Current-Source Pull-Up

* The drain characteristics are - I Dp = - I Dp ( V SG , V SD ), which can be expressed as the “switchable” pull-up’s current-voltage characteristic,

i SUP = i SUP ( V IN , v SUP )

since i SUP = - I Dp and V SG = V DD - V IN and v SUP = V SD .

- I Dp =

i SUP

- V I N and v S U P = V S D . - I

1

23

4

5

1 23 4 5

V SD = v SUP

- V Tp

EE 105 Spring 1997 Lecture 11

CMOS Transfer Characteristic ■ plotting the p-channel pull-up on the n-channel “driver’s” drain characteristics
CMOS Transfer Characteristic
■ plotting the p-channel pull-up on the n-channel “driver’s” drain characteristics
allows us to find the input-output voltage pairs that satisfy the constraint that
I Dn = - I Dp
V OUT
1
V DD
2
3
4
5
V DD
V IN
I Dn = I Dp
I Dp = I Dn
V IN
3
3
4
4
2
2
1
5
1 5
V DD
V OUT
V DD
V OUT
n-channel
p-channel
(a)
(b)

EE 105 Spring 1997 Lecture 11

Simplified Voltage Transfer Curve

For CMOS inverters, the voltage transfer curve of the inverter is ideal enough that we can approximate it with a construction that is suitable for quick hand calculation

V OUT

V OH = V MAX

V M

V OL = V MIN

Slope A v V IN V IL V M V IH
Slope A v
V IN
V IL
V M
V IH

We first observe that:

V OH

V MAX

=

V DD

and

V OL

V MIN

=

0 V

The edges of the transition region are then found as the intersections of the tangent to the voltage transfer curve at V IN = V M (a line of slope A v )

In order to construct the VTC for a CMOS inverter (and to find estimates of the noise margins), we need to first:

(i) find the voltage V M

(ii) find the small-signal voltage gain A v at V IN = V M

EE 105 Spring 1997 Lecture 11

Step 1. Finding V M ■ Goal: find V M = input voltage for the
Step 1. Finding V M
■ Goal: find V M = input voltage for the output = V M
both transistors are saturated at V IN = V M since
V DSn = V M - 0 > V M - V Tn
V SDp = V DD - V M = (V DD - V M ) +V Tp
■ Equate drain currents, omitting the channel length modulation terms
(1 + λ n V DSn ) and (1 + λ p V SDp ) since they tend to cancel out (if λ n = λ p ,
they exactly cancel out)
W
------
(
V
) 2
I Dn
= µ n C ox
M
V Tn
2L
n
W
=
------
(
– V
) 2
– I Dp
µ p C ox
V DD
V Tp
2L
M +
p
■ Letting k n = µ n C ox (W/L) n and k p = µ p C ox (W/L) p --
---k 2 1 n (
V
) 2
= ---k 2 1 p (
V
V
) 2
M
V Tn
V DD
M +
Tp

EE 105 Spring 1997 Lecture 11

Finding V M (cont.)

Result:

V M

k p ----- ( V DD k n k p 1 + ----- k n
k
p
-----
(
V
DD
k
n
k
p
1 +
-----
k
n

)

= ------------------------------------------------------------

V Tn

+

+

V Tp

We can set V M = V DD / 2 and achieve a symmetrical transfer curve

Example: suppose V Tn = - V Tp = 1 V and V DD = 5 V

V M

k p ----- k n k p ----- k n
k
p
-----
k
n
k
p
-----
k
n

4

1

+

= ----------------------- = 2.5

1 +

V --> k p = k n

which makes sense since the transistors must have identical characteristics for the transfer curve to be symmetrical.

The mobility of holes in p-channels is about half that of electrons in n-channels, µ p = µ n / 2, which implies that we must adjust the width-length ratios to compensate:

k n = k p --> (W/L) p = 2(W/L) n

EE 105 Spring 1997 Lecture 11

+

v in

_

Step 2. Finding A v

s2 + g mp v sg2 v sg2 r op _ g1 = g2 d1=d2
s2
+
g mp v sg2
v sg2
r op
_
g1 = g2
d1=d2
+
v out
v gs1
g mn v gs1
r on
_

s1

We note that v sg2 = - v in and can simplify the small-signal circuit

v in

       
 
       
 
       
 
       
 
       
 

+

       

+

g

g

   
g        
   

v

mn v

v mn v     g mp v  
 
v mn v     g mp v  
 

g

mp v

 

r on

r op

       
 
       
 
       
 
       
 
       

v out

+
+

EE 105 Spring 1997 Lecture 11

Approximate Transfer Curve ■ The small-signal gain (which is the slope of the transfer curve
Approximate Transfer Curve
■ The small-signal gain (which is the slope of the transfer curve when the input is
equal to the mid-point voltage) is:
= – (
g
+
) (
)
= A v
v out
v in
mn
g mp
r on
r op
CMOS inverters have a channel length that is as short as possible (to minimize the
area
and maximum the density)
the output resistances are relatively small and a
typical value is v out / v in = - 5 to - 10.
* The input-low and input-high voltages are:
V OUT
V OH = V DD
A v
V DD
V M
A v
V OL = 0 V
V M
V IN
V IL
V IH
= – (
V
⁄ ( 2
A
)
)
V IL
M
V DD
v
= + (
V
⁄ ( 2
A
)
)
V IH
M
V DD
v

EE 105 Spring 1997 Lecture 11

Noise Margins

For k N = k P , the mid-point voltage is V M = 2.5 V. For a slope A v = - 5, the input- low voltage and input-high voltages are:

V IL = 2.5 V - (1/5) (2.5 V) = 2 V

V IH = 2.5 V + (1/5) (2.5 V) =3 V

The low and high noise margins are therefore:

N ML = V IL - V OL = 2 - 0 = 2 V

N MH = V OH - V IH =5 - 3 = 2 V

The transition region (or “gray area”) is the interval

V IL < V IN < V IH

or

2 V < V IN < 3 V

Finding the actual transfer function requires solving the drain current equations

when the p-channel and n-channel are in the appropriate operating regions finding the transition voltages for the regions.

SPICE is good at this job!

and

EE 105 Spring 1997 Lecture 11

CMOS Inverter: Propagation Delay

The propagation delays t PHL and t PLH are obviously of major importance for digital circuit design

Example:

clock frequency = 250 MHz --> clock period = 4 ns

complex systems (e.g., microprocessor) have around 20-50 propagation delays per clock period, so we need to have

t PLH and t PHL < 100 ps = 10 -10 s

Hand calculation of propagation delays: use approximation that input changes instantaneously

V IN

V OH

V OL

V OUT

V OH

V OL

t CYCLE
t
CYCLE
t PHL t PLH
t PHL
t PLH

t

50%

t CYCLE

V OH

instantaneously V IN V OH V OL V OUT V OH V OL t CYCLE t

t

EE 105 Spring 1997 Lecture 11

Estimating the Load Capacitance ■ The load capacitance C L consists of C G ,
Estimating the Load Capacitance
■ The load capacitance C L consists of
C G , the input capacitances of the inverters 2 and 3, and
C P , the parasitic capacitance to the substrate from the drain regions of inverter 1
and the interconnections between the output of inverter 1 and the inputs of
inverters 2 and 3.
V DD
W
p2
L
2
V DD
V DD
W
W
n2
L
L
p1
1
V IN
V IN
+
V
DD
W
C L
V OUT
L
W
n1
p3
L
3
W
n3
L
(a)
(b)
■ For hand calculation, we do a worst case estimate of C G by adding the maximum
gate capacitances for inverters 2 and 3
=
[
(W ⋅ L)
+ (W ⋅ L)
+
(W ⋅ L)
+ (W ⋅ L)
]
C G
C ox
p2
n2
p3
n3

EE 105 Spring 1997 Lecture 11

Parasitic Capacitance from Drain Depletion Regions

The drain n and p regions have depletion regions whose stored charge changes during the transient.

Take the worst case and use the zero-bias depletion capacitance (the maximum value) as a linear charge-storage element during the transient.

A

active area (thin oxide area) gate contact gate polysilicon gate interconnect contact n + polysilicon
active area (thin
oxide area)
gate contact
gate
polysilicon gate
interconnect
contact
n + polysilicon gate
metal
interconnect
source contacts
W
bulk
contact
drain
contacts
edge of
source
drain
active area
interconnect
interconnect
L

(b)

L

L diff

W bulk contact drain contacts edge of source drain active area interconnect interconnect L (b) L
W bulk contact drain contacts edge of source drain active area interconnect interconnect L (b) L

W

EE 105 Spring 1997 Lecture 11

Calculation of Parasitic Depletion Capacitance

“Bottom” of depletion regions of the load inverters’ drain diffusions contribute a depletion capacitance

C BOTT = C Jn (W n L diffn ) + C Jp (W p L diffp )

with C Jn and C Jp being the zero-bias junction capacitances (fF/µm 2 ) for the n- channel MOSFET drain-bulk junction and the p-channel MOSFET drain-bulk junction, respectively.

“Sidewall” of depletion regions of the load inverters’ drain diffusions make an additional contribution:

C SW = (W n + 2L diffn )C JSWn + (W p + 2L diffp )C JSWp

with C JSWn and C JSWp being the zero-bias sidewall capacitances (fF/µm) for the n-channel MOSFET drain-bulk junction and the p-channel MOSFET drain-bulk junction, respectively.

The total depletion capacitance C DB = C BOTT + C SW

Typical numbers: C JN and C JP are about 0.2 fF/µm 2 and C JSWn and C JSWp are about 0.5 fF/µm.

EE 105 Spring 1997 Lecture 11

Parasitic Capacitance from Interconnections

“Wires” consist of metal lines connecting the output of the inverter to the input of the next stage. In cross section,

polysilicon metal interconnect gate (width , length L ) W m m 0.6 m deposited
polysilicon
metal interconnect
gate
(width
, length L
)
W m
m
0.6
m deposited oxide
0.5
m thermal oxide
p +
p
(grounded)
gate oxide

The p + layer (i.e., heavily doped with acceptors) under the thick thermal oxide (500 nm = 0.5 µm) and deposited oxide (600 nm = 0.6 µm) depletes only slightly when positive voltages appear on the metal line, so the capacitance is approximately the oxide capacitance:

C WIRE

=

C thickox

(

W

m

L

m )

where the oxide thickness = 500 nm + 600 nm = 1.1 µm.

* For large digital systems, the parasitic interconnect capacitance can dominate the load capacitance --

C L = C G + C P = C G + (C DB + C WIRE )

EE 105 Spring 1997 Lecture 11

EE 105 Spring 1997 Lecture 11

EE 105 Spring 1997 Lecture 11