Complementary MOS (CMOS) Inverter

Concept: transistor switches connect output either to VDD or to ground

VDD VDD VDD

INPUT HIGH

OUTPUT LOW CL

INPUT LOW

OUTPUT HIGH CL

VIN + CL VOUT (c)

(a)

(b)

Practical realization: connect input to gate of p-channel device. VIN = VDD --> VSG2 = VDD - VIN = 0 < - VTp --> cutoff VIN = 0 --> VSG2 = VDD - VIN = VDD >> - VTp --> on (triode region)

Graphical analysis: need to nd family of load lines since input is connected to gate of M2

EE 105 Spring 1997 Lecture 11

p-Channel MOSFET Characteristics

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p-channel MOS load device: VSGp = VDD - VIN

as VIN increases, the source-gate voltage VSGp decreases.

VDD VSGp + _ + VSDp = vSUP _

+ VIN _

- IDp= iSUP

note that the bulk connection is tied to the source (VDD), which results in a constant threshold voltage.

EE 105 Spring 1997 Lecture 11

Switchable Current-Source Pull-Up

* The drain characteristics are - IDp = - IDp (VSG, VSD), which can be expressed as the switchable pull-ups current-voltage characteristic, iSUP = iSUP(VIN, vSUP) since iSUP = -IDp and VSG = VDD - VIN and vSUP = VSD.

- IDp = iSUP

VSD = vSUP

- VTp

EE 105 Spring 1997 Lecture 11

CMOS Transfer Characteristic

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plotting the p-channel pull-up on the n-channel drivers drain characteristics allows us to nd the input-output voltage pairs that satisfy the constraint that IDn = - IDp

VOUT VDD 1 2

5 VDD

VIN

IDn = IDp

IDp = IDn

VIN 3 4 5 n-channel (a) 2 1 VDD VOUT 5 p-channel (b) 4 3 2 1 VDD VOUT

EE 105 Spring 1997 Lecture 11

Simplied Voltage Transfer Curve

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For CMOS inverters, the voltage transfer curve of the inverter is ideal enough that we can approximate it with a construction that is suitable for quick hand calculation
VOUT VOH = VMAX Slope Av

VM

VOL = VMIN VIL VM VIH VIN

We rst observe that: V OH V MAX = V DD and V OL V MIN = 0 V The edges of the transition region are then found as the intersections of the tangent to the voltage transfer curve at VIN = VM (a line of slope Av)

In order to construct the VTC for a CMOS inverter (and to nd estimates of the noise margins), we need to rst: (i) nd the voltage VM (ii) nd the small-signal voltage gain Av at VIN = VM

EE 105 Spring 1997 Lecture 11

Step 1. Finding VM
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Goal: nd VM = input voltage for the output = VM both transistors are saturated at VIN = VM since VDSn = VM - 0 > VM - VTn VSDp = VDD - VM = (VDD - VM) +VTp

Equate drain currents, omitting the channel length modulation terms (1 + n VDSn) and (1 + p VSDp) since they tend to cancel out (if n = p, they exactly cancel out)

2 W I Dn = n C ox ------ ( V M V Tn ) 2L n

2 W I Dp = p C ox ------ ( V DD V + V Tp ) 2L p M

Letting kn = n Cox (W/L)n and kp = p Cox (W/L)p --

2 2 1 1 -- k n ( V M V Tn ) = -- k p ( V DD V M + V Tp ) 2 2

EE 105 Spring 1997 Lecture 11

Finding VM (cont.)
Result: kp V Tn + ----- ( V DD + V Tp ) kn V M = ----------------------------------------------------------kp 1 + ----kn

We can set VM = VDD / 2 and achieve a symmetrical transfer curve Example: suppose VTn = - VTp = 1 V and VDD = 5 V kp 1 + 4 ----kn V M = ---------------------- = 2.5 V --> kp = kn kp 1 + ----kn which makes sense since the transistors must have identical characteristics for the transfer curve to be symmetrical. The mobility of holes in p-channels is about half that of electrons in n-channels, p = n / 2, which implies that we must adjust the width-length ratios to compensate: kn = kp --> (W/L)p = 2(W/L)n

EE 105 Spring 1997 Lecture 11

Step 2. Finding Av
s2 + vsg2 _ + vin _ + vgs1 _ s1 g1 = g2 d1=d2 gmnvgs1 ron vout gmpvsg2 rop

We note that vsg2 = - vin and can simplify the small-signal circuit
+ vin + v gmnv ron rop gmpv + vout

EE 105 Spring 1997 Lecture 11

Approximate Transfer Curve

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The small-signal gain (which is the slope of the transfer curve when the input is equal to the mid-point voltage) is: v out v in = ( g mn + g mp ) ( r on r op ) = A v

CMOS inverters have a channel length that is as short as possible (to minimize the area ... and maximum the density) ... the output resistances are relatively small and a typical value is vout / vin = - 5 to - 10. * The input-low and input-high voltages are:
VOUT VOH = VDD Av VDD VM Av VOL = 0 V

VIL

VM

VIH

VIN

V IL = V M ( V DD ( 2 A v ) ) V IH = V M + ( V DD ( 2 A v ) )

EE 105 Spring 1997 Lecture 11

Noise Margins
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For kN = kP, the mid-point voltage is VM = 2.5 V. For a slope Av = - 5, the inputlow voltage and input-high voltages are: VIL = 2.5 V - (1/5) (2.5 V) = 2 V VIH = 2.5 V + (1/5) (2.5 V) =3 V The low and high noise margins are therefore: NML = VIL - VOL = 2 - 0 = 2 V NMH = VOH - VIH =5 - 3 = 2 V The transition region (or gray area) is the interval VIL < VIN < VIH or 2 V < VIN < 3 V

Finding the actual transfer function requires solving the drain current equations when the p-channel and n-channel are in the appropriate operating regions ... and nding the transition voltages for the regions. SPICE is good at this job!

EE 105 Spring 1997 Lecture 11

CMOS Inverter: Propagation Delay

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The propagation delays tPHL and tPLH are obviously of major importance for digital circuit design ... Example: clock frequency = 250 MHz --> clock period = 4 ns complex systems (e.g., microprocessor) have around 20-50 propagation delays per clock period, so we need to have tPLH and tPHL < 100 ps = 10-10 s

Hand calculation of propagation delays: use approximation that input changes instantaneously
VIN VOH tCYCLE

VOL t VOUT VOH 50% VOL t tCYCLE tPHL tPLH VOH

EE 105 Spring 1997 Lecture 11

Estimating the Load Capacitance

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The load capacitance CL consists of CG, the input capacitances of the inverters 2 and 3, and CP, the parasitic capacitance to the substrate from the drain regions of inverter 1 and the interconnections between the output of inverter 1 and the inputs of inverters 2 and 3.

V DD W L p2 VDD V DD W L p1 VIN CL + V OUT 3 W L n3 V IN 1 W L n1 2 W L n2

V DD W L p3

(a)

(b)

For hand calculation, we do a worst case estimate of CG by adding the maximum gate capacitances for inverters 2 and 3 C G = C ox [ ( W L ) p2 + ( W L ) + ( W L ) p3 + ( W L ) ] n2 n3

EE 105 Spring 1997 Lecture 11

Parasitic Capacitance from Drain Depletion Regions

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The drain n and p regions have depletion regions whose stored charge changes during the transient. Take the worst case and use the zero-bias depletion capacitance (the maximum value) as a linear charge-storage element during the transient.
gate contact active area (thin oxide area)

n+ polysilicon gate

source contacts

source interconnect

 

 ,,,  
,,  
,,  


gate interconnect polysilicon gate contact metal interconnect
W

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bulk contact L L drain interconnect drain contacts edge of active area (b) W
Ldiff

EE 105 Spring 1997 Lecture 11

Calculation of Parasitic Depletion Capacitance

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Bottom of depletion regions of the load inverters drain diffusions contribute a depletion capacitance CBOTT = CJn(WnLdiffn) + CJp(WpLdiffp) with CJn and CJp being the zero-bias junction capacitances (fF/m2) for the nchannel MOSFET drain-bulk junction and the p-channel MOSFET drain-bulk junction, respectively.

Sidewall of depletion regions of the load inverters drain diffusions make an additional contribution: CSW = (Wn + 2Ldiffn)CJSWn + (Wp + 2Ldiffp)CJSWp with CJSWn and CJSWp being the zero-bias sidewall capacitances (fF/m) for the n-channel MOSFET drain-bulk junction and the p-channel MOSFET drain-bulk junction, respectively.

The total depletion capacitance CDB = CBOTT + CSW

Typical numbers: CJN and CJP are about 0.2 fF/m2 and CJSWn and CJSWp are about 0.5 fF/m.

EE 105 Spring 1997 Lecture 11

Parasitic Capacitance from Interconnections

,,
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Wires consist of metal lines connecting the output of the inverter to the input of the next stage. In cross section,

polysilicon gate

The p+ layer (i.e., heavily doped with acceptors) under the thick thermal oxide (500 nm = 0.5 m) and deposited oxide (600 nm = 0.6 m) depletes only slightly when positive voltages appear on the metal line, so the capacitance is approximately the oxide capacitance: C WIRE = C thickox ( W m L m )

where the oxide thickness = 500 nm + 600 nm = 1.1 m. * For large digital systems, the parasitic interconnect capacitance can dominate the load capacitance -CL = CG + CP = CG + (CDB + CWIRE)

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metal interconnect (width Wm, length Lm) 0.6 m deposited oxide 0.5 m thermal oxide (grounded) p+ p gate oxide
EE 105 Spring 1997 Lecture 11

EE 105 Spring 1997 Lecture 11