TABLE OF CONTENTS

1. INTRODUCTION................................................................................................................... 5
2. TUNER.................................................................................................................................... 5
2.1.
General description of UV1316: ................................................................................. 5
2.2.
Features of UV1316: ................................................................................................... 5
2.3.
Pinning: ....................................................................................................................... 6
3. AUDIO AMPLIFIER STAGE WITH TDA8933 ................................................................... 6
3.1.
General Description..................................................................................................... 6
3.2.
Features ....................................................................................................................... 6
3.3.
Applications ................................................................................................................ 7
3.4.
Absolute Ratings ......................................................................................................... 7
3.4.1.
Performance figures SE........................................................................................... 7
3.4.2.
Performance figures BTL........................................................................................ 8
3.5.
Pinning ........................................................................................................................ 9
4. POWER STAGE ..................................................................................................................... 9
5. MICROCONTROLLER (MSTAR) ........................................................................................ 9
5.1.
General Descripction................................................................................................... 9
5.2.
General Features........................................................................................................ 10
5.3.
Port Allocation .......................................................................................................... 13
5.4.
ELECTRICAL PECIFICATIONS .......................................................................... 26
6. TDA 9886 I2C-bus controlled single/multistandard alignment-free IF PLL....................... 27
6.1.
General Desription .................................................................................................... 27
6.2.
Features ..................................................................................................................... 27
6.3.
Absolute Maximum Ratings...................................................................................... 28
6.4.
Pinning ...................................................................................................................... 28
7. SERIAL 32K I2C EEPROM................................................................................................. 29
7.1.
General Description................................................................................................... 29
7.2.
Features ..................................................................................................................... 29
7.3.
Absolute Maximum Ratings...................................................................................... 29
7.4.
Pinning ...................................................................................................................... 30
8. CLASS AB STEREO HEADPHONE DRIVER TDA1308 ................................................. 30
8.1.
General Description................................................................................................... 30
8.2.
Features ..................................................................................................................... 30
8.3.
Pinning ...................................................................................................................... 31
9. SAW FILTER ....................................................................................................................... 31
9.1.
IF Filter for Audio Applications Epcos K9656M .................................................. 31
9.1.1.
Standart: ................................................................................................................ 31
9.1.2.
Features: ................................................................................................................ 31
9.1.3.
Pin configuration: .................................................................................................. 31
9.1.4.
Frequency response: .............................................................................................. 32
9.2.
IF Filter for Video Applications Epcos K9658M................................................... 33
9.2.1.
Standart: ................................................................................................................ 33
9.2.2.
Features: ................................................................................................................ 33
9.2.3.
Frequency response: .............................................................................................. 33
10.
8M x 16 DDR Synchronous DRAM (SDRAM) ............................................................... 35
10.1.
General Description............................................................................................... 35
10.2.
Features ................................................................................................................. 35
10.3.
Absolute Maximum Ratings.................................................................................. 36
10.4.
Pinning .................................................................................................................. 38
11.
Low On-Resistance Wideband/Video Quad 2-Channel Mux/DeMux - PI5V330............ 40
11.1.
General Description............................................................................................... 40

11.2.
Features ................................................................................................................. 40
11.3 Absolute Maximum Ratings...................................................................................... 40
11.4 Pinning ...................................................................................................................... 41
12.
Low voltage mono/stereo power Amplifier - TDA7050T ................................................ 42
12.1.
General Description............................................................................................... 42
12.2.
Features ................................................................................................................. 42
11.3 Absolute Maximum Ratings...................................................................................... 42
13.
Mbit Uniform Sector, Serial Flash Memory ..................................................................... 43
13.1 General Description................................................................................................... 43
13.2 Features ..................................................................................................................... 43
13.3 Absolute Maximum Ratings...................................................................................... 44
13.4 Pinning ...................................................................................................................... 46
14.
IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM ........................................ 46
14.1.
LM1117 ................................................................................................................. 46
14.1.1. General Description............................................................................................... 46
14.1.2. Features ................................................................................................................. 47
14.1.3. Applications .......................................................................................................... 47
14.1.4. Absolute Maximum Ratings.................................................................................. 47
14.1.5. Pinning .................................................................................................................. 47
14.2.
MP1593 ................................................................................................................. 48
14.2.1. General Description............................................................................................... 48
14.2.2. Features ................................................................................................................. 48
14.2.3. Applications .......................................................................................................... 48
14.2.4. Absolute Maximum Ratings.................................................................................. 48
14.2.5. Electrical Characteristics....................................................................................... 49
14.2.6. Pinning .................................................................................................................. 49
14.3.
FDC642P............................................................................................................... 50
14.3.1. General Description............................................................................................... 50
14.3.2. Features ................................................................................................................. 50
14.3.3. Absolute Maximum Ratings.................................................................................. 50
14.3.4. Pinning .................................................................................................................. 50
14.4.
24LC02.................................................................................................................. 51
14.4.1. General Description............................................................................................... 51
14.4.2. Features ................................................................................................................. 51
14.4.3. Pinning .................................................................................................................. 51
14.5.
PA672T ............................................................................................................... 52
14.5.1. General Description............................................................................................... 52
14.5.2. Features ................................................................................................................. 52
14.5.3. Absolute Maximum Ratings.................................................................................. 52
14.5.4. Pinning .................................................................................................................. 52
14.6.
M74HC4052.......................................................................................................... 53
14.6.1. General Description............................................................................................... 53
14.6.2. Features ................................................................................................................. 53
14.6.3. Absolute Maximum Ratings.................................................................................. 53
14.6.4. Pinning .................................................................................................................. 53
14.7.
Max810.................................................................................................................. 54
14.7.1. General Description............................................................................................... 54
14.7.2. Features ................................................................................................................. 54
14.7.3. Absolute Maximum Ratings.................................................................................. 55
14.7.4. Pinning .................................................................................................................. 55
14.8.
24LC21.................................................................................................................. 56

14.8.1. General Description............................................................................................... 56

14.8.2. Features ................................................................................................................. 56
14.8.3. Absolute Maximum Ratings.................................................................................. 56
14.8.4. Pinning .................................................................................................................. 57
15.
SERVICE MENU SETTINGS.......................................................................................... 57
15.1.
Video Setup ........................................................................................................... 57
15.2.
AudioSetup............................................................................................................ 58
15.3.
Service Scan/Tuning Setup ................................................................................... 59
15.4.
Options .................................................................................................................. 60
15.5.
External Source Settings ....................................................................................... 61
15.6.
Select Language .................................................................................................... 62
15.7.
Preset ..................................................................................................................... 62
15.8.
NVM Edit .............................................................................................................. 63
15.9.
Programming ......................................................................................................... 63
15.10. Diagnostic.............................................................................................................. 63
16.
SOFTWARE UPDATE DESCRIPTION.......................................................................... 63
16.1 17MB30 Analog Part Software Update Procedure .................................................. 63
16.2 17MB30 HDCP key upload procedure. ................................................................... 64
16.3 17MB30 HDMI EDID key upload procedure.......................................................... 64
17.
BLOCK DIAGRAMS ....................................................................................................... 66
17.1.
General Block Diagram......................................................................................... 66
17.2.
Power Management............................................................................................... 67
17.3.
IF Demodulator Block Diagram............................................................................ 69
17.4.
MSTAR General Block Diagram .......................................................................... 70

1. INTRODUCTION
17MB30 Main Board consists of MSTAR consept. This IC is capable of handling Audio
processing, video processing, Scaling-Display processing, 3D comb filter, OSD and text
processing, 8 bit dual LVDS transmitter.
TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards
as B/G, D/K, I/I, and L/L including German and NICAM stereo.
Sound system output is supplying 2x3W (10%THD) for stereo 4 speakers.
Supported peripherals are:
1 RF input VHF1, VHF3, UHF @ 75Ohm
1 Side AV (SVHS, CVBS, HP, R/L_Audio)
2 SCART sockets
1 YPbPr
1 PC input
2 HDMI input
1 Stereo audio input for PC
1 Line out
1 Subwoofer out
1 SPDIF output

2. TUNER
A vertical mounted tuner is used in the product, which is suitable for CCIR + CATV
channel (3 bant) systems B/G, H, L/ L, I/I, and D/K. The tuning is available through the
digitally controlled I2C bus (PLL). Below you will find info on the Tuner in use.

2.1.

General description of UV1316:

Lgtuner is designed to meet a wide range of applications. It is a combined VHF, UHF

tuner suitable for CCIR+ CATV channel (3 bant) systems B/G, H, L, L, I and I. The low
IF output impedance has been designed for direct drive of a wide variety of SAW filters
with sufficient suppression of triple transient.

2.2.

Features of UV1316:

small sized UHF/VHF tuners

Systems CCIR: B/G, H, L, L, I and I; OIRT: D/K

Digitally controlled (PLL) tuning via I2C-bus

Off-air channels, S-cable channels and Hyper band
Compact size
Complies with the requirements of radiation, signal handling capability and
immunity
conforming to European standards CENELEC EN55020 and
EN55013.

2.3.

Pinning:

3. AUDIO AMPLIFIER STAGE WITH TDA8933

3.1.

General Description

17MB30 uses a Switched Mode Amplifier (SMA) for audio, based on the TDA8933
device of Philips Semiconductors operating from an asymmetrical supply. TDA8933 can
be used in either a stereo SE configuration or a mono BTL configuration. These features
enable an engineer to design a high performance, reliable and cost effective Switch
Mode Amplifier (SMA) with only a small number of external components.

3.2.

Features

High efficiency Class-D audio amplifier due to a low RDS_ON

Operates from a wide voltage range 10 V to 36 V (asymmetrical) or +/-5 V to +/-18 V
(symmetrical)
Maximum power capability:
TDA8932 is 2 x 25 WRMS maximum in 4 SE without heat sink
TDA8933 is 2 x 15 WRMS maximum in 8 SE without heat sink
Cycle-by-cycle current limiting to avoid interruption during normal operation
Unique Thermal Foldback (TF) to avoid interruption during normal operation
Integrated Half Supply Voltage (HVP) buffers for reference and SE output capacitance
(asymmetrical supply)
Internal logic for pop-free power supply on/off cycling
Low standby-current in SLEEP-mode for power saving regulations
Window Protection (WP)
Under Voltage Protection (UVP)
Over Voltage Protection (OVP)

 UnBalance Protection (UBP)

Over Current Protection (OCP)
Over Temperature Protection (OTP)

3.3.

Applications

The TDA8933 Class-D amplifier is intended for:

Flat-TV application
Flat panel monitors
Multimedia systems
Wireless speakers
Micro systems

3.4.

Absolute Ratings

3.4.1. Performance figures SE

3.4.2. Performance figures BTL

3.5.

Pinning

4. POWER STAGE
The DC voltages required at various parts of the chassis and inverters are provided by a
main power supply unit and power interface board. IPS generates 12V and 5V DC
supply. Power stage which is on-chasis generates +12V for audio amplifier, 1.2V and
3.3V stand by voltage and 33V, 12V, 5V and 3.3Vsupplies for other different parts of the
chassis.

5. MICROCONTROLLER (MSTAR)
5.1.

General Descripction

The MST6W82BL is a high performance and fully integrated IC for multi-function LCD
monitor/TV with resolutions up to SXGA/WXGA+. It is configured with an integrated

triple-ADC/PLL, an integrated DVI/HDCP/HDMI receiver Note, a multi-standard TV

video and audio decoder, two video de-interlacers, two scaling engines, the MStarACE3 color engine, an on-screen display controller, an 8-bit MCU and a built-in
output panel interface. By use of external frame buffer, PIP/POP is provided for
multimedia applications. Furthermore, 3-D video decoding and processing are fulfilled
for high-quality TV applications. To further reduce system costs, the MST6W82BL also
integrates intelligent power management control capability for green-mode requirements
and spread-spectrum support for EMI management. Note: The optional HDMI function is
available with MST6W82BLD.
LCD TV controller with PIP/POP display functions
Input supports up to SXGA & 1080P
Panel supports up to SXGA/WXGA+
TV decoder with 3-D comb filter
Multi-Standard TV sound demodulator and decoder
10-bit triple-ADC for TV and RGB/YPbPr
10-bit video data processing
Integrated DVI/HDCP/HDMI compliant receiver Note 1
High-quality scaling engine & 3-D video de-interlacer
Full function PIP/PBP/POP
MStarACE-3 picture/color processing engine
Embedded On-screen display controller (OSD) engine
Built-in MCU supports PWM & GPIO
Built-in dual-link 8-bit LVDS transmitter
5 Volt tolerant inputs
Low EMI and power saving features
256-pin LQFP

5.2.

General Features

NTSC/PAL/SECAM Video Decoder

Supports NTSC M, NTSC-J, NTSC-4.43, PAL (B,D,G,H,M,N,I,Nc), and SECAM
Automatic TV standard detection
Motion adaptive 3-D comb filter for NTSC/PAL
8 configurable CVBS & Y/C S-video inputs
Supports Teletext level-1.5, WSS, VPS, Closed-caption, and V-chip
Macrovision detection
CVBS video output
Multi-Standard TV Sound Decoder
Supports BTSC/NICAM/A2/EIA-J demodulation and decoding
FM stereo & SAP demodulation
L/Rx4, mono, and SIFx2 audio input
L/Rx3 loudspeaker and line output
Supports sub-woofer output
Built-in audio output DACs
Audio processing for loudspeaker channel, including volume, balance, mute,
tone, EQ, and virtual stereo/surround
Supports advanced surround (Dolby1, SRS2, BBE3 etc) Note 2

1 Trademark of Dolby Laboratories

2 Trademark of SRS Labs, Inc.
3 Registered trademark of BBE Sound, Inc.
Digital Audio Interface
I2S digital audio input & output
S/PDIF digital audio input & output
HDMI audio channel processing capability Note 1
Programmable delay for audio/video synchronization
Analog RGB Compliant Input Ports
Three analog ports support up to 150MHz
Supports PC RGB input up to SXGA@75Hz
Fast blanking and function selection switch support full SCART functions
Supports HDTV RGB/YPbPr/YCbCr up to 1080P
Supports Composite Sync and SOG (Sync-on-Green) separator
Automatic color calibration
DVI/HDCP/HDMI Compliant Input Port Note 1
Two HDMI input ports with built-in switch
Operates up to 150 MHz (up to SXGA @75Hz)
Single link on-chip DVI 1.0 compliant receiver
High-bandwidth Digital Content Protection
(HDCP) 1.1 compliant receiver
High Definition Multimedia Interface (HDMI) 1.2 compliant receiver
Long-cable tolerant robust receiving
Support HDTV up to 1080P
Auto-Configuration/Auto-Detection
Auto input signal format and mode detection
Auto-tuning function including phasing, positioning, offset, gain, and jitter
detection
Sync Detection for H/V Sync
Digital Video Input
One 4:2:2 ITU-R BT.656 8/10-bit digital video input port
One 4:2:2 ITU-R BT.601 16-bit digital video input port
High-Performance Scaling Engine
Fully Programmable shrink/zoom capabilities
Nonlinear video scaling supports various modes including Panorama
Video Processing & Conversion
3-D motion adaptive video deinterlacers
Edge-oriented adaptive algorithm for smooth low-angle edges
Automatic 3:2 pull-down & 2:2 pull-down detection and recovery
PIP/PBP/POP with programmable size and location, supports multi-video
applications

MStar 3rd Generation Advanced Color Engine (MStarACE-3) automatic picture

enhancement gives:
Brilliant and fresh color
Intensified contrast and details
Vivid skin tone
Sharp edge
Enhanced depth of field perception
Accurate and independent color control
sRGB compliance allows end-user to experience the same colors as viewed on
CRTs and other displays
Programmable 12-bit RGB gamma CLUT
3-D video noise reduction
Frame rate conversion supports 120Hz panels

On-Screen OSD Controller

16/256 color palette
256/512 1-bit/pixel font
128/256 4-bit/pixel font
Supports texture function
Supports 4K attribute/code
Horizontal and vertical stretch of OSD menus
Pattern generator for production test
Supports OSD MUX and alpha blending capability
Supports blinking and scrolling for closed caption applications
8-bit LVDS/TTL Panel Interface
Supports dual link LVDS up to SXGA@75Hz or WXGA@120Hz
Supports 8-bit single TTL panel
Supports 2 data output formats: Thine & TI data mappings
Compatible with TIA/EIA
With 6/8 bits options
Reduced swing for LVDS for low EMI
Supports flexible spread spectrum frequency with 360Hz~11.8MHz and up to
25% modulation
Integrated Micro Controller
Embedded 8032 micro controller
Configurable PWMs and GPIOs
Low-speed ADC inputs for system control
SPI bus for external flash
Supports external MCU option controlled through 4-wire double-data-rate direct
MCU bus or 8-bit direct MCU bus
External Connection/Component
16-bit data bus for external frame buffer (SDR or DDR DRAM)
All system clocks synthesized from a single external clock
Note:
1. The optional HDMI function is available with
MST6W82BLD.
2. Please see Ordering Guide for details on advanced
surround.

6. TDA 9886 I2C-bus controlled single/multistandard

alignment-free IF PLL
6.1.

General Desription

The TDA9886 is an alignment-free multistandard (PAL,SECAM and NTSC) vision and

sound IF signal PLL demodulator for positive and negative modulation including sound
AM and FM processing.

6.2.

Features

5 V supply voltage
Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (ACcoupled)
Multistandard true synchronous demodulation with active carrier regeneration
(very linear demodulation, good intermodulation figures, reduced harmonics,
excellent pulse response)
Gated phase detector for L/L accent standard
Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free;
frequencies switchable for all negative and positive modulated standards via I2Cbus
Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and
58.75 MHz
4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning
system] or operating as crystal oscillator
VIF Automatic Gain Control (AGC) detector for gain control, operating as peak
sync detector for negative modulated signals and as a peak white detector for

positive modulated signals

Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digitalto-analog converter; AFC bits via I2C-bus readable
TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by
FM-PLL oscillator
Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL
controlled)
SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to
operate in high performance single reference QSS mode and in intercarrier
mode, switchable via I2C-bus
AM demodulator without extra reference circuit
Alignment-free selective FM-PLL demodulator with high linearity and low noise
I2C-bus control for all functions
I2C-bus transceiver with pin programmable Module Address (MAD).

6.3.

Absolute Maximum Ratings

6.4.

Pinning

7. SERIAL 32K I2C EEPROM

7.1.

General Description

The M24C32 devices is I2C-compatible electrically erasable programmable memories

(EEPROM). t is organized as 4096 8 bits.

7.2.

Features

Two-Wire I2C serial interface Supports 400kHz Protocol

Single supply voltages
2.5 to 5.5V
1.8 to 5.5V
1.7 to 5.5V
Write Control Input
Byte and Page Write
Random And Sequential Read modes
Self-Timed programming cycle
Automatic address incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Write cycles
More than 40-year data retention
Packages ECOPACK (RoHS compliant)

7.3.

Absolute Maximum Ratings

7.4.

Pinning

8. CLASS AB STEREO HEADPHONE DRIVER TDA1308

8.1.

General Description

The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8

or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has
been primarily developed for portable digital audio applications. It gets its input from two
analog audio outputs (DACA_L and DACA_R) of MSP 34x0G. The gain of the output is
adjustable by the feedback resistor between the inputs and outputs.

8.2.

Features

Wide temperature range

No switch ON/OFF clicks
Excellent power supply ripple rejection
Low power consumption
Short-circuit resistant
High performance
High signal-to-noise ratio
High slew rate
Low distortion
Large output voltage swing.
Power supply maximum 60 mW to 32 (THD<0.1%)
5V single supply
SNR 110 dB
Power supply ripple rejection
Typically 3 mA supply current at no load

8.3.

Pinning

9. SAW FILTER
9.1.

IF Filter for Audio Applications Epcos K9656M

9.1.1. Standart:

B/G
D/K
I
L/L

9.1.2. Features:

TV IF audio filter with two channels

Channel 1 (L) with one pass band for sound carriers at 40,40 MHz (L) and 39,75
MHz (L- NICAM)
Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35
MHz and 33,40 MHz

9.1.3. Pin configuration:

1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output

9.1.4. Frequency response:

9.2.

IF Filter for Video Applications Epcos K9658M

9.2.1. Standart:

B/G
D/K
I
L/L

9.2.2. Features:
TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
Constant group delay
Pin configuration:
1 Input
2 Input - ground
3 Chip - carrier ground
4 Output
5 Output

9.2.3. Frequency response:

10. 8M x 16 DDR Synchronous DRAM (SDRAM)

10.1.

General Description

The EM6A9160 SDRAM is a high-speed CMOS double data rate synchronous DRAM
containing 128 Mbits. It is internally configured as a quad 2M x 16 DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CK). Data outputs occur at both rising edges of CK and /CK. Read and write accesses
to the SDRAM are burst oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence. Accesses begin with
the registration of a BankActivate command which is then followed by a Read or Write
command. The EM6A9160 provides programmable Read or Write burst lengths of 2, 4,
or 8. An auto precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The refresh functions, either Auto or
Self Refresh are easy to use. In addition, EM6A9160 features programmable DLL
option. By having a programmable mode register and extended mode register, the
system can choose the most suitable modes to maximize its performance. These
devices are well suited for applications requiring high memory bandwidth, result in a
device particularly well suited to high performance main memory and graphics
applications.

10.2.

Features

Fast clock rate: 300/275/250/200MHz

Differential Clock CK & /CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 1M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- /CAS Latency: 3, 4
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
4096 refresh cycles / 32ms
Precharge & active power down
Power supplies: VDD & VDDQ = 2.5V
5%
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
Lead-free Package is available.

10.3.

Absolute Maximum Ratings

10.4.

Pinning

11. Low On-Resistance Wideband/Video Quad 2-Channel

Mux/DeMux - PI5V330
11.1.

General Description

Pericom Semiconductors PI5V330 is a true bidirectional Quad 2-channel

multiplexer/demultiplexer recommended for both RGB and composite video switching
applications. The video switch can be driven from a current output RAMDAC or voltage
output composite video source. Low On-Resistance and wide bandwidth make it ideal
for video and other applications. Also this device has exceptionally high current
capability which is far greater than most analog switches offered today. A single 5V
supply is all that is required for operation. The PI5V330 offers a high-performance, lowcost solution to switch between video sources.

11.2.

Features

High-performance solution to switch between video sources

Wide bandwidth: 400 MHz (typical)
Low On-Resistance: 5 (typical)
Low crosstalk at 10 MHz: 56dB
Ultra-low quiescent power (0.1A typical)
Single supply operation: +5.0V
Packaging (Pb-free & Green Available):
16-pin 300-mil wide plastic SOIC (S)
16-pin 150-mil wide plastic SOIC (W)
16-pin 150-mil wide plastic QSOP (Q)

11.3 Absolute Maximum Ratings

11.4 Pinning

12. Low voltage mono/stereo power Amplifier - TDA7050T

12.1.

General Description

The TDA7050T is a low voltage audio amplifier for small radios with headphones (such
as watch, pen and pocket radios) in mono (bridge-tied load) or stereo applications.

12.2.

Features

Limited to battery supply application only (typ. 3 and 4 V)

Operates with supply voltage down to 1,6 V
No external components required
Very low quiescent current
Fixed integrated gain of 26 dB, floating differential input
Flexibility in use mono BTL as well as stereo
Small dimension of encapsulation

11.3 Absolute Maximum Ratings

13. Mbit Uniform Sector, Serial Flash Memory

13.1 General Description
The EN25F80 is a 8M-bit (1024K-byte) Serial Flash memory, with advanced write
protection mechanisms, accessed by a high speed SPI-compatible bus. The memory
can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The
EN25F80 is designed to allow either single Sector at a time or full chip erase operation.
The EN25F80 can be configured to protect part of the memory as the software protected
mode. The device can sustain a minimum of 100K program/erase cycles on each
sector.

13.2 Features
Single power supply operation
- Full voltage range: 2.7-3.6 volt
8 Mbit Serial Flash
- 8 M-bit/1024 K-byte/4096 pages
- 256 bytes per programmable page
High performance
- 100MHz clock rate

 Low power consumption

- 5 mA typical active current
- 1 A typical power down current
Uniform Sector Architecture:
- 256 sectors of 4-Kbyte
- 16 blocks of 64-Kbyte
- Any sector or block can be erased individually
Software and Hardware Write Protection:
- Write Protect all or portion of memory via software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Page program time: 1.5ms typical
- Sector erase time: 150ms typical
- Block erase time 800ms typical
- Chip erase time: 10 Seconds typical
Lockable 256 byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- All Pb-free packages are RoHS compliant
Commercial and industrial temperature Range

13.3 Absolute Maximum Ratings

13.4 Pinning

14. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM

LM1117
MP1593
FDC642P
24LC02
PA672T
M74HC4052
Max810
24LC21

14.1.

LM1117

14.1.1.

General Description

The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at
800mA of load current. It has the same pin-out as National Semiconductors industry
standard LM317. The LM1117 is available in an adjustable version, which can set the
output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also
available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers
current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap

reference to as-sure output voltage accuracy to within 1%. The LM1117 series is
available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10F
tantalum capacitor is required at the output to improve the transient response and
stability.

14.1.2.

Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions

Space Saving SOT-223 Package
Current Limiting and Thermal Protection
Output Current 800mA
Line Regulation 0.2% (Max)
Load Regulation 0.4% (Max)
Temperature Range
LM1117 0C to 125C
LM1117I -40C to 125C

14.1.3.

Features

Applications

2.85V Model for SCSI-2 Active Termination

Post Regulator for Switching DC/DC Converter
High Efficiency Linear Regulators 15
32 TFT TV Service Manual 10/01/2005
Battery Charger
Battery Powered Instrumentation

14.1.4.

Absolute Maximum Ratings

14.1.5.

Pinning

14.2.

MP1593

14.2.1.

General Description

The MP1593 is a step-down regulator with an internal Power MOSFET. It achieves 3A

continuous output current over a wide input supply range with excellent load and line
regulation. Current mode operation provides fast transient response and eases loop
stabilization. Fault condition protection includes cycle-by-cycle current limiting and
thermal shutdown. Adjustable soft-start reduces the stress on the input source at turnon. In shutdown mode the regulator draws 20A of supply current. The MP1593
requires a minimum number of readily available external components to complete a 3A
step down DC to DC converter solution.

14.2.2.

3A Output Current
Programmable Soft-Start
100m Internal Power MOSFET Switch
Stable with Low ESR Output Ceramic Capacitors
Up to 95% Efficiency
20A Shutdown Mode
Fixed 385KHz Frequency
Thermal Shutdown
Cycle-by-Cycle Over Current Protection
Wide 4.75 to 28V Operating Input Range
Output Adjustable from 1.22V
Under Voltage Lockout
Available in 8-Pin SOIC Package

14.2.3.

Features

Applications

Distributed Power Systems

Battery Chargers
Pre-Regulator for Linear Regulators
Flat Panel TVs
Set-Top Boxes
Cigarette Lighter Powered Devices
DVD/PVR Devices

14.2.4.

Absolute Maximum Ratings

14.2.5.

Electrical Characteristics

14.2.6.

Pinning

Pin1:BS
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel
MOSFET switch. Connect a 10nF or greater capacitor from SW to BS to power the high
side switch.
Pin2:IN
Power Input. IN supplies the power to the IC, as well as the step-down converter
switches. Drive IN with a 4.75V to 28V power source. Bypass IN to GND with a suitably
large capacitor to eliminate noise on the input to the IC.
Pin3:SW
Power Switching Output. SW is the switching node that supplies power to the output.
Connect the output LC filter from SW to the output load. Note that a capacitor is required
from SW to BS to power the high-side switch.
Pin4:GND
Ground.
Pin5:FB
Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a
resistive voltage divider from the output voltage. The feedback threshold is 1.222V.
Pin6:COMP
Compensation Node. COMP is used to compensate the regulation control loop. Connect
a series RC network from COMP to GND to compensate the regulation control loop. In
some cases, an additional capacitor from COMP to GND is required.
Pin7:EN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn
on the regulator, drive EN low to turn it off. An Under Voltage Lockout (UVLO) function
can be implemented by the addition of a resistor divider from VIN to GND. For complete
low current shutdown its needs to be less than 0.7V. For automatic startup, leave EN
unconnected.
Pin8:SS

Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS
to GND to set the soft-start period. A 0.1F capacitor sets the soft-start period to 10ms.
To disable the soft-start feature, leave SS unconnected.

14.3.

FDC642P

14.3.1.

General Description

This p-channel 2.5V specified MOSFET is produced using Fairchilds advanced

PowerTrench process that has been especially tailored to minimize on state resistance
and yet maintain low gate charge for superior switching performance.

14.3.2.

Features

14.3.3.

Absolute Maximum Ratings

14.3.4.

Pinning

14.4.

24LC02

14.4.1.

General Description

24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM. The device is

organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby and active currents of only 1A
and 1mA, respectively. The 24XX02 also has a page write capability for up to 8 bytes of
data.

14.4.2.

Features

Single supply with operation down to 1.8V

Low-power CMOS technology
-1mA active current typical
-1A standby current typical (I-temp)
Organized as 1 block of 256 bytes (1 x 256 x 8)
2-wire serial interface bus, I2C compatible
Schmitt Trigger inputs for noise suppression
Output slope control to eliminate ground bounce
100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
Self-timed write cycle (including auto-erase)
Page write buffer for up to 8 bytes
2ms typical write cycle time for page write
Hardware write-protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 4,000V
1,000,000 erase/write cycles
Data retention > 200 years
8-lead PDIP, SOIC, TSSOP and MSOP packages
5-lead SOT-23 package
Pb-free finish available
Available for extended temperature ranges:
-Industrial (I): -40C to +85C
-Automotive (E): -40C to +125C

14.4.3.

Pinning

14.5.

PA672T

14.5.1.

General Description

N-channel Mos-Fet array for switching.The PA672T is a super-mini-mold device

provided with two MOS FET elements. It achieves high-density mounting and saves
mounting costs.

14.5.2.

Features

Two MOS FET circuits in package the same size as SC-70

Automatic mounting supported

14.5.3.

Absolute Maximum Ratings

14.5.4.

Pinning

14.6.

M74HC4052

14.6.1.

General Description

The M74HC4052 is a dual four-channel analog MULTIPLEXER/DEMULTIPLEXER

fabricated with silicon gate C2MOS technology and it is pin to pin compatible with the
equivalent metal gate CMOS4000B series. It contains 8 bidirectional and digitally
controlled analog switches.

14.6.2.

Features

LOW POWER DISSIPATION: ICC = 4mA(MAX.) at TA=25C

LOGIC LEVEL TRANSLATION TO ENABLE 5V LOGIC SIGNAL TO
COMMUNICATE
WITH 5V ANALOG SIGNAL
LOW "ON" RESISTANCE:
70W TYP. (VCC - VEE = 4.5V)
50W TYP. (VCC - VEE = 9V)
WIDE ANALOG INPUT VOLTAGE RANGE: 6V
FAST SWITCHING:
tpd = 15ns (TYP.) at TA = 25 C
LOW CROSSTALK BETWEEN SWITCHES
HIGH ON/OFF OUTPUT VOLTAGE RATIO
WIDE OPERATING SUPPLY VOLTAGE RANGE (VCC - VEE) = 2V TO 12V
LOW SINE WAVE DISTORTION: 0.02% at VCC - VEE = 9V
HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)
PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4052

14.6.3.

Absolute Maximum Ratings

14.6.4.

Pinning

VEE supply pin is provided for analog input signals. It has an inhibit (INH) input terminal
to disable all the switches when high. For operation as a digital
multiplexer/demultiplexer, VEE is connected to GND.

A and B control inputs select one channel out of four in each section. All inputs are
equipped with protection circuits against static discharge and transient excess voltage.

14.7.

Max810

14.7.1.

General Description

The MAX809 and MAX810 are costeffective system supervisor circuits designed to
monitor VCC in digital systems and provide a reset signal to the host processor when
necessary. No external components are required.
The reset output is driven active within 10 _sec of VCC falling through the reset voltage
threshold. Reset is aintained active for a timeout period which is trimmed by the factory
after VCC rises above the reset threshold. The MAX810 has an activehigh RESET
output while the MAX809 has an activelow RESET output. Both devices are available
in SOT23 and SC70 packages.

14.7.2.

Features

Precision VCC Monitor for 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V, and 5.0 V Supplies
Precision Monitoring Voltages from 1.2 V to 4.9 V Available in 100 mV Steps
Four Guaranteed Minimum PowerOn Reset Pulse Width Available (1 ms, 20
ms, 100 ms, and 140 ms)
RESET Output Guaranteed to VCC = 1.0 V.
Low Supply Current
Compatible with Hot Plug Applications
VCC Transient Immunity
No External Components
Wide Operating Temperature: 40C to 105C
PbFree Packages are Available

14.7.3.

Absolute Maximum Ratings

14.7.4.

Pinning

14.8.

24LC21

14.8.1.

General Description

The 24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),

organized by 8 bits.This device can operate in two modes: Transmit Only mode and I2C
bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM
data clocked out from the rising edge of the signal applied on VCLK.

14.8.2.

Features

1 MILLION ERASE/WRITE CYCLES

40 YEARS DATA RETENTION
2.5V to 5.5V SINGLE SUPPLY VOLTAGE
400k Hz COMPATIBILITY OVER the FULL RANGE of SUPPLY VOLTAGE
TWO WIRE SERIAL INTERFACE I2C BUS COMPATIBLE
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP PERFORMANCES

14.8.3.

Absolute Maximum Ratings

14.8.4.

Pinning

15. SERVICE MENU SETTINGS

In order to reach service menu, First Press MENU Then press the remote control
code, which is 4725

15.1.

Video Setup

Panel Select <..................................>

LTM220M1-L01
On Timing 1 (10ms) <...........> Value between 1 to 16
On Timing 2 (10ms) <...........> Value between 16 to 80
Off Timing 1 (10ms) <...........> Value between 4 to 20
Off Timing 2 (10ms) <...........> Value between 1 to 16
Blue Screen <.....>
If Menu selected, Blue Background item is seen in Feature
menu.
If Yes selected, Blue Background is on and not seen in
Feature menu
User Picture Mode <.....>
If Yes selected, USER item is seen picture mode menu.
Dynamic Contrast <.....>
If Yes selected, Dynamic Contrast feature is active.
Picture Adjustment <...........>
Sources Type <.......>
Tuner 50 Hz
CVBS 50 Hz
SVHS 50Hz
RGB 50 Hz
DTV
HDMI
YPbPr

PC
Tuner 60 Hz
CVBS 60Hz
SVHS 60Hz
RGB 60Hz
HDMI/DVI
HDMI HD
YPbPr HD
Picture Mode <.......>
User
Dynamic
Natural
Cinema
Colour Temp <.......>
Cool
Normal
Warm
Contrast <.......> Value between 0 to +63
Brightness <.......> Value between 0 to +63
Sharpness <.......> Value between 0 to +31
Colour <.......> Value between 0 to +63
Hue <.......> Value between 0 to +64
Backlight <.......> Value between 0 to +255
R Gain <.......> Value between -63 to +63
G Gain <.......> Value between -63 to +63
B Gain <.......> Value between -63 to +63
ADC Adjust <...........>
ADC source <.......>
PC
YPbPr
Scart RGB
Auto ADC Calibration <.......>
Press "right button to Calibrate the ADC
R Gain <.......> Value between 0 to 255
G Gain <.......> Value between 0 to 255
B Gain <.......> Value between 0 to 255
R Offset <.......> Value between 0 to 255
G Offset <.......> Value between 0 to 255
B Offset <.......> Value between 0 to 255

15.2.

AudioSetup

BG<.....>
Europe
New Zelland
Australia
No

DK<.....>
I<.....>
L<.....>
Equalizer <.....>
If Yes selected, Equalizer item is seen in Sound menu.
Headphone <.....>
If Yes selected, Headphone item is seen in Sound menu.
Dynamic Bass <.....>
If Yes selected, Dynamic Bass item is seen in Sound
menu.
Audio Delay ,offset <.....> Value between 0 to 255
Prescales ( AVL On)
FM Prescale<.......> Value between 0 to 255
AM Prescale <.......> Value between 0 to 255
NICAM Prescale <.......> Value between 0 to 255
SCART Prescale <.......> Value between 0 to 255
FAV/PC Prescale <.......> Value between 0 to 255
DTV Prescale <.......> Value between 0 to 255
HDMI Prescale <.......> Value between 0 to 255
Prescales ( AVL Off)
FM Prescale<.......> Value between 0 to 255
AM Prescale <.......> Value between 0 to 255
NICAM Prescale <.......> Value between 0 to 255
SCART Prescale <.......> Value between 0 to 255
FAV/PC Prescale <.......> Value between 0 to 255
DTV Prescale <.......> Value between 0 to 255
HDMI Prescale <.......> Value between 0 to 255

15.3.

Service Scan/Tuning Setup

First Search for L/L <.......>

ATS Delay Time (ms) <.......> Value between 0 to +200
AGC : VHF-1 <.......> Value between 0 to +31
AGC : VHF-III&UHF <.......> Value between 0 to +31
Main Tuner Setup
Tuner Type
Alps TDQG2XC01
Thomson DTT71300
Philips TD1318AF-3
Generic ( Analog Only)
Control Byte <.......> Value between 0 to +255
BSW1 <.......> Value between 0 to +255
BSW2 <.......> Value between 0 to +255
BSW3 <.......> Value between 0 to +255
Low-Mid Low Byte <.......>
Low-Mid High Byte <.......>
Mid-High Low Byte <.......>

Mid-High High Byte <.......>

15.4.

Options

Options-1
Power Up
Standby
Last state
TV Open Mode
Source
1st TV
Last Tv
First APS <.......>
If Yes selected, first time TV opens by asking APS.
APS Volume <.......> Value between 0 to +63
Burn In Mode <.......>
If Yes selected, TV opens with Burn-In mode. This mode is
used in manufacturing.
APS Test
Autostore <.......>
If Yes selected, Channel is automatically stored.
Options-2
Source List menu <.......>
If Yes selected, Sorce List Menu appears on the screen
when press source button.
RS232 for B2B <.......>
If Yes selected, Remote Control commandsthe TV via
RS232 and vice versa.
Remote Control Unit <.......>
RC1050
RC1055
RC1061
RC1062
RC1063
RC1071
RC1072
RC1082
RC1110
RC1243
RC1546
RC1549
RC1558
RK18
Double Digit Key <.......>
If Yes selected, Double Digit Button on RC activates.
Protection <.......>
If Yes selected,short circuit protection activates.
Led Type <.......>
1 Led 1 Color
1 Led 2 Color

2 Led 2 Color
1 Led 3 Color
2 Led 3 Color
Teletext Option
TXT Type <.......>
Fasttext&Toptext
No
Default
Fastext
Toptext
TXT Language <.......>
Menu
West
East
Cyrillic
Turk/Gre
Arabic
Persian
Auto
No Txt Warning <.......>
If Yes selected, No Txt Transmission warning appears on
the screen when pressing txt button from RC.
Optional Features
Default Zoom <.......>
Menu
16:9
4:3
Panaromic
14:9 Zoom
Menu Timeout <.......>
Menu
15 Sec
30 Sec
60 Sec
No Time
Backlight <.......>
If Yes selected, Backlight feature is active.
PIP Options
Pip <......>
AV PIP
No PIP
PC PIP
Hotel TV <......>
If Yes selected, Hotel TV feature is active.
IR Smartloader

15.5.

External Source Settings

TV <.......>
DTV <.......>

Ext 2 S <.......>
FAV <.......>
BAV <.......>
S-Video <.......>
HDMI 1 <.......>
HDMI 2 <.......>
YPbPr <.......>
PC <.......>

15.6.

Select Language

Select Language-1
English
German
French
Spanish
Italian
Danish
Finnish
Swedish
Greek
Select Language-2
Norwegian
Dutch
Portuguese
Polish
Turkish
Russian
Czech
Hungarian
Slovak
Select Language-3
Slovenian
Romanian
Bulgarian
Croatian
Serbian
Hebrew
Arabian
Persian

15.7.

Preset

User Ad.j
White Balance Adj.
ADC Adj.
Service Adj.
All Adj.

15.8.

NVM Edit

NVM-edit addr. (hex)

NVM-edit data (hex)
NVM-data dec

15.9.

Programming

HDMI DDC Update Mode <.......>

HDCP Key Update Mode <.......>
DDR Spread Spctrm Step <.......> Value between 0 to +255
PLL Spread Spctrm Span L <.......> Value between 0 to +3
PLL Spread Spctrm Span H <.......> Value between 0 to +255
DDR Spread Spctrm Enable <.......>
PLL Spread Spctrm Step L <.......> Value between 0 to +255
PLL Spread Spctrm Step H <.......> Value between 0 to +7
PLL Spread Spctrm Span L <.......> Value between 0 to +255
PLL Spread Spctrm Span H <.......> Value between 0 to +127
PLL Spread Spctrm Mode <.......> Value between 0 to +1
PLL Spread Spctrm Enable <.......>

15.10.

Diagnostic

Eeprom I2C
Tuner I2C
IF I2C
Video Decoder I2C
DTV RS232

16. SOFTWARE UPDATE DESCRIPTION

16.1 17MB30 Analog Part Software Update Procedure
1) ISP Windows Driver should be installed
2) 4 channel cable should be connected to CON5 on ISP apparatus and the other
end should be connected to CN117(Next to VGA connector on 17MB30 board.
Another option is to use service connector CN108(In front of the tuner). In that
case female service connector should be used instead of standard 4 channel
cable
3) ISP aparatus should be connected to PC via USB cable
4) ISP_Tool_V.X.X.exe is executed
5) Click on Connect icon located on upper menu tabs
6) An information window should pop-up showing: Device Type is XXXXXX. Press
OK. If the window does not appear check cable connections and close the
ISP_Tool_V.X.X.exe. Disconnect USB cable and reconnect. Restart application
and repeat the steps all-over again
7) To download a binary to PC Load tab is used. To upload a binary file to TV
Read tab is used.
8) Please select Read Tab from upper menu. Binary file to be uploaded should be
specified by clicking Read icon.

9) Click on Auto Tab. Checkboxes to be selected are shown in image below.

Before starting to upload the file please make sure these adjustments are made
correctly. Then click on Run to upload the file. While uploading file please do
not interrupt. In case of failed upload please retry.

16.2 17MB30 HDCP key upload procedure.

1) Turn on TV set.
2) Open a COM connection using fallowing parameters and select ISP COM Port
No
Baud Rate: 9600 bps
Data Bits: 8
Stop Bits: 1
Parity: None
Flow Control: None
3) Enter service menu by pressing 4 7 2 5 consecutively while main menu is
open
4) Select 9. Programming
5) Select HDMI HDCP Update Mode yes.
6) On Hyper Terminal Window press k
7) Click on send file under Transfer Tab.
8) Select Xmodem and choose the HDCP key to be uploaded.
9) Press send button
10)Restart TV set

16.3 17MB30 HDMI EDID key upload procedure.

1) Turn on TV set.
2) Connect HDMI cable between TV HDMI port and ISP HDMI port
3) Enter service menu by pressing 4 7 2 5 consecutively while main menu is
open
4) Select 9. Programming
5) Select HDMI DDC Update Mode yes.

6) Turn off TV set.

7) Close all running programs.
8) Open MsEEPROM_1.52.exe.
9) Make sure EEPROM 24C02 is selected.
10)Click Load File to Table as shown in below figure then select the file to be
upladed

11)Select Write All from the right hand side menu

12)Compare File to Table and make sure there is no difference.

13)Repeat steps 1-11 for HDMI Port 2

17. BLOCK DIAGRAMS

17.1.

General Block Diagram

17.2.

Power Management

MB30
Voltages
12V
5V
3.3V
2.5V
1.2V
1.5V
IC

1.5V
MAX
350mA

EMMA2LL
UPD61450
DDR RAM
FLASH
AUDIO DAC
VIDEO AMP
CI
BUFFERS&GATES
CI
TOTAL CURRENT 350mA
IC
M-STAR

1.5V
TYP
310mA

1.8V
MAX

1.8V
TYP

310mA

1.2V
STBY
370mA

MAX Current
A
1
0,635
1,033
0,784
0,37
0,525
2.5V
MAX
50mA

2.5V
TYP
40mA

300mA

270mA

350mA

1.2V
TYP
330mA

1.8V
MAX

310mA

1.8V
TYP

FrontEND
DDR
RAM
FLASH
ClassD+HP
TOTAL
CURRENT
IC
M-STAR
Front-END
DDR RAM
FLASH
ADV7180
Class-D+HP
TOTAL
CURRENT

370mA

3.3V
STBY
463mA

453mA

330mA

3.3V
MAX
160mA

3.3
TYP
30mA

50mA

30mA
3mA

210mA

63mA

3.3V
MAX
130mA
100mA

3.3V
TYP
120mA
90mA

50mA

30mA

100mA

90mA

380mA

330mA

2.5V
MAX
34mA

2.5V
TYP
30mA

400mA

250mA

434mA

280mA

5V
MAX

5V
TYP

300mA

260mA

35mA
335mA

30mA
290mA

24V
MAX

1A
1A

5V
MAX

5V
TYP

300mA
300mA

280mA
280mA

24V
TYP

900mA
900mA

17.3.

IF Demodulator Block Diagram

17.4.

MSTAR General Block Diagram

L114
F120
2

MCLK

C363
100n
10V

2
1

51

C624
10p
50V

S350

C642

2R1

VIF2

SIF1

VIF1

SIF2

10V
100N

220N
16V

20

C116 R466
1
22K
AFC

21

2
1

C121
100n
10V

2
1

C119
100n
10V

R483
100R

R595
10k

23
R361
15K

R178
47R
1

SIF_T

24

R396
18k

IF_AGC_DVB

C275
22n
16V

C320
22n
16V

2
1

S101

U114
74HCT4053
SCL_T_DVB
SCL_5V
RF_AGC_DVB

16V
22N
2

2
1
3

R177
47R

C319
1u
16V

S103

1
1

S106

VCC
2Z
1Z
1Y1
1Y0
S1
S2
S3

R208
4K7

S128

S281

5V

R536
75R

R465
22K

IDTV_SW
2

PROJECT NAME :
22N
16V

T_VCOM

Q107
BC848B

SDA_TUNER

SDA_T_DVB
SDA_5V

100N
10V

R608
2K2
1

Q104
BC848B

C114

C132
100N
10V

SCL_TUNER

Q106
BC848B

10P
50V
TUN_CVBS

16
15
14
13
12
11
10
9
1

SIF

2Y1
2Y0
3Y1
3Z
3Y0
E
VEE
GND

R537
75R

RF_AGC_A

C260

C480
Q105
BC848B

RF_AGC

1
2
3
4
5
6
7
8

C259

R387
22k

1
1

10N
16V

1
2
2

C262
100n
10V

5V_TUN

5V

1
1

R145
4k7

R144
4k7

R603
1k5
2

5V_TUN

C375
22n
16V

S338

SAW_SW

D135

C448

C347
22n
16V

5V

22

R342
22K

R141
150R

Z101
1 IN1
OUT1 4
K9656M
2 IN2
OUT2 5
GND

1N4148

RF_AGC_DVB
2

1
1

R392
10K

C425

19

C318
10U
16V

R467
22K

18

600R

17

R402
18k

F219
1

10K
R388

R371
22k

R597
1k5

OP2

D134

4MHz

470N
16V

3
10K
R393

10N
16V
SAW_SW

SYNC_PORT1
16

AVDD33_AD2
15

VCOMO_AD2
14

VRTO_AD2

VRB0_AD2
13

12

VNQN

VNQP

17

3V3A_DEMOD

C261
100n
10V

R367
2K4

OP1

C447

5V_LIMITED

AGC1

R394

AFC

$1I2079

5k6
R587
R596
10k

FMPLL

1N4148

RF_AGC

C652
22u
16V

VP

10V

C112

100N

10V

X105
1

VPLL

DEEM

S112

R209
4K7

C698
100n
16V

5V_TUN

1
1

C122
100n
10V

SCL_T_DVB

3V3_DEMOD
R493
100R 2

RF_AGC_A
C289
1u
16V

ANT_CNT

AGND

TDA9886T
U148

C111

S111

C310

16

50V
22P

60R

10V

100N

15

S344

C120
100n
10V

CVBS

3
1

1V5_DEMOD
R269
100R 2

R586
5k6
2

AUD

C483

R395
10K

VAGC

14

TOP

5V_TUN

880n

REF

AFD

Z102
1 IN1
OUT1 4
K3958M
2 IN2
OUT2 5
GND

TAGC

SDA

DGND

L119

1u

L101

2
1

R328
5K6

S107

IF_MONO

10N
16V

SDA_T_DVB

F187
2

C118

S110

R734
4k7
2

SCL_TUNER

TU101
TD1318AF

SCL

R108
12K

100N

SDA_TUNER

R210
100R

R274
100R

S116

S102
1
1

100N

10V

5
4

10N
16V

DC_POWER

R277
100R

13

RF_GAIN

7
R272
100R
R273
100R

10

470N 16V

C366

11

CLKFREQ2

10

64

AGND_AD2

AEXTCLK

10k
R326

AGND_AD1

63

VNP

GND5

PLL

VCC_33V

11
2

390P
50V
C456

1N

GND1

18

CLKFREQ1

62

C117

SCL

S119

19

61

SDA

50V

C477

NC

R594
10k
AGC2

3V3_DEMOD

10K

F_OUT

VDD33_1

20

C309

SIOMAD

12

V_TUN

PSYNC

21

R372
47K

SDA_5V

C455

SCL2

C367

W_IF

33

VDD15_6

SIF_T

R607
2K2 2
R275
1
100R
R276
1
100R

S109

R205
33R
R207
33R

60

VCC_33V

880n

S117

22

SIF_GND

10

34

VDD15_1

1N

IF_GAIN

CKO

X1

35

59

ANT_CNT

N_IF1

DO7_SDO

23

SCLK

RESET

1
1

10P
50V
L120

11

3V3_DEMOD

SDA2

R593
10k

50V

N_IF2

36

X0

10p
50V

VDD33_2

58

37

24

C115

SCL_5V

C452

DO6

I2CSEL0

SDATA

1V5_DEMOD

ANT_CNT

IF_AGC_DVB

1V5_DEMOD

AVDD15_PLL

3V3A_DEMOD

100N
10V

38

25

VCC_3V3

C207
100n
10V

C575
1

VDD15_3

I2CSEL1

U130
UPD61540

VNN

2
1

39

AGND_PLL

57

1
1

DO5

56

IFD_INP

40

26

IFD_INN

C208
100n
10V

DO4

GND2

C660
220p
50V

41

MCLK_PORT3

Q108
BC848B

42

55

R532
15k

R533
15k
1

GND3

27

46

RSTB

VRTO_AD1

3V3_DEMOD

S358

NEAR TO U130
C661
220p
50V

47

VDD15_5

R463
18k

1
1

10k
R278

10k
R604

1V5_DEMOD

R288
10k

3V3A_DEMOD

IFD_INN

IFD_INP

3V3A_DEMOD

54

22p
50V

28

R508
18k

C643

1V5A_DEMOD

VDD15_2

2
3

C697
100n
16V

22p
50V

X104

C647
10u
16V

VCC_5V

5V_LIMITED

Q169
FDN336P

TH101

1
2

20.48MHz

S339

TEST1

R206
560R

NTF_PORT2

VRB0_AD1

S143

GND4

53

2
1

R509
75R
R510
75R

C623
10p
50V

SCL1

30
29

VCOMO_AD1

TEST2

AVDD33_AD1

1V5_DEMOD

52

SCL

31

C392
100n
10V

SDA1

R147
4K7

C393
100n
10V

32

C362
100n
10V

TEST3

SLEEP

C359
100n
10V

ERR

50

Q163
BSN20

SLEEP
3V3_DEMOD

R146
4K7

C625
10p
50V

C358
100n
10V

C574
22u
6V3

49

DO3_MOLT

1V5_DEMOD

VDD33_3

1V5A_DEMOD

43

60R

48

C644
22u
6V3

DO0_MOP

MSTRT

MERR

1
1

C449
100n
10V

PORTN

Q162
BSN20

R390
10K

SCL_5V

60R

S280

C622
10p
50V

1.5V

SDA

VLD

10u
F122

SDA_5V

1
2

R271
33R

R732
2R2
F123

R391
10K

L113
1

DO2_MOCK

C258
100n
16V

R270
33R

R447
10k

C257
100n
16V

MD7

MD6

C451
10u
16V

MD5

3V3A_DEMOD
2

C113
100N
10V

MD4

R733
2R2

C441
100u
16V

MD3

MD2

60R

VCC_3V3

C578
10p
50V

1V5_DEMOD

C232
100n
16V

MD1

F121
1

C231
100n
16V

44

MD0

60R

STBY_5V

C230
100n
16V

VDD15_4

45

3.3V

3V3_DEMOD

60R

F119

DO1_MOQ

3V3_DEMOD

10u

MVAL

SCH NAME :

FRONT END

DRAWN BY :

UTKU GKKAYA

17MB30-1
SHEET:

A3
1

OF:

11

5-17-2007_9:14

AXM

5
D118
4
NUP4004M5 2
IO3_EXT_TVL

1u
16V

1
2
3
4

LINE_L_OUT

R185
100R

LINE_R_OUT

R794
10k
1

1u
16V

R852
33k

C460

AUD_OUT0_R

C
AUD_OUT0_L

NEAR TO PAULO

NEAR TO PAULO
1

R184
100R

R191
100R

1u
16V

1u
16V

10n
16V
R346
22k

220p
50V

C426

PND_SC1

75R
R554

1
1

10n
16V
R343
22k

220p
50V
R844
33k

C422
1

VCC_12V

C679
1u
16V

OUTA VDD 8
INAN OUTB 7
INAP INBN 6
VSS
INBP 5

C101
220p
50V

C714

U151
TDA1308T

C457

75R
R553
C103

C713
22u
16V

220p
50V
R843
33k

16V
22u

600R
1

R793
10k
1

C513
C683

R192
100R

1u
16V

R675
10k

SC1_AUD_L_OUT

1
1

STBY_3V3

600R

R552
75R

F184
1

F208

R845
33k

R851
33k

R676
10k

2
2

Q164
BSN20

1
2

50V
1n

C720
1

C508
C684

R189
100R

SC2_CVBS_OUT

R748
75R

TV_LINK

22u
16V
C715

CVBS1_OUT

R690
1k

1u
16V

R507
300R

16V
22u

CVBS_EXT1

R674
10k

2
1

C264

R626
100k

Q112
BC848B

C733

SC1_AUD_R_OUT

R625
100k
3

CVBS_EXT

C685
1u
16V

R334
470R

R555
75R

1
3

Q119
BC848B

C631
1n
50V

R846
33k

STBY_3V3

CVBS_EXT1

600R

STBY_5V

Q166
BC807

SUBW_OUT

3
1

5
D101
4
NUP4004M5 2

3
1

R186
100R

F185

C627
100n
16V

S105

C370

600R

GRN

R623
100k
R506
300R

1u
16V

600R

C368
50V
1n

R689
1k

R551
75R

SC1_CVBS_OUT

F183
1

C369

F203
1

600R

CVBS0_OUT

R624
100k

Q109
BC848B

VCC_5V

F182
1

C263

50V

R548
22k

470p

C686
1u
16V

50V
1n

3
3

1
2

50V

100p
50V

Q167
BC807

SPDIF_OUT

R142
150R

C579
1n
50V

5
D119
4
NUP4004M5 2

R188
100R

C105

220p
50V

C497

R179
100R

10

C626
100n
16V

3
1

YPBPR_AUD_L

470p

C344

100p
50V

F180
1

10n
16V

600R
5

1
1

220p
50V

C461

RCA_Y

C107

YPBPR_AUD_R

C343

600R
1

RCA_PR

6
7

C501

1
2

Q114
BC848B

R505
300R

F179

JK104

2
1

100n
16V

5
4

600R
1

600R

S118

VCC_5V

R333
470R

100p
50V

C498

100n
10V

RCA_PB

C104

220p
50V

RCA_VCOM

600R

C123

C342

F181
VCC_5V

RED

F202
F178
1

BLU

JK102

SC1_CVBS_IN
SC1_CVBS_OUT
C106

37

1
3

35

R212
22k

NUP4004M5
4
5

D103

34
33

D108
1

32

C22V

S283

TV_LINK

31

D151

SC2_B

3
1

12

SC1_B

F109
1

F104
1

27

26

25

24

23

22

1
1

F102
2

F101

5
D109
4
NUP4004M5 2

5
D110
4
NUP4004M5 2

3
1

C371

200R

R182
100R

AUD_OUT2_L

SUBW_L

1u
16V

R190
100R

AUD_OUT2_R

NEAR TO PAULO

NEAR TO PAULO
SUBW_R

16V
22u

1u
16V

LINE_L_OUT
SC1_AUD_R_IN

SC1_AUD_L_OUT

C500

200R

200R

F103

EXT_L_OUT
2

50V
100p

600R

R183
100R

1u
16V

C510
C678
C718

F149
1

200R
1n
50V

SC2_AUD_L_OUT
SC1_AUD_L_IN

C374

3
1

R181
100R

16V
22u

R187
100R

28

R545
75R

1u
16V

SC2_AUD_R_OUT

C361

C458

200R

1u
16V

10n
16V

29

F106
1

SC2_AUD_R_IN

30

600R

C372

200R

C494

1
1

F150

OUTA VDD 8
INAN OUTB 7
INAP INBN 6
VSS
INBP 5

C360

C459

F105

C512
C676

1n200R
50V

50V

1
2
3
4

220p
50V
R849
33k

1u
16V

U152
TDA1308T

10n
16V
R345
22k

LINE_R_OUT

C716

220p
50V
R850
33k

SC2_AUD_L_OUT

1n

R101
4k7

10

200R
R180
100R
50V
100p

16V
22u

D107

SC1_G
SC1_PIN8
1

11

C717

C511
C675

C22V

1u
16V

R344
22k

NUP4004M5 2

13

D102

SC2_AUD_R_OUT

C495

100p
50V

5
4

14

1u
16V 16V
22u

SC1_R
75R
R546
75R 1
2
R544
R211
22k 2
2

100p
50V

F110
1

SC2_AUD_L_IN

VCC_12V

C671
1u
16V

C5V6

EXT_R_OUT

SC1_FB

C491

R540
75R

C719

C5V6

R102
4k7

15

36

SC101

SC2_G
SC2_PIN8

SCART2 ( TOP )

75R
R539

75R
R541

16

SCART1 ( BOTTOM )

47R
R547

D125

33R
R543

22u
16V

C711
22u
16V

17
2

SC2_R

38

600R

R792
10k

47R
R542

18

100n
10V

SC2_FB

39

SC1_VCOM

F206

R848
33k

C5V6

C5V6

C721

1
2

19

33R
R538

40

R791
10k

220p
50V

D106

R847
33k
C734

C124

C5V6
1

20

R854
33k

C373

41

220p
50V
D117

C509
C677

SC1_AUD_R_OUT

1u
16V

1n
50V

C102

D112

21

R853
33k

42

SC2_CVBS_IN
SC2_CVBS_OUT

PROJECT NAME :

SCH NAME :

ANALOG IN

DRAWN BY :

UTKU GKKAYA

17MB30-1
SHEET:

A3
2

OF:

11

5-17-2007_9:15

AXM

HPD2

1N4148
VCC_5V

12

100R

8
7
6
5

R280
2

100R

R281

1
2
3
4

HD5V_B

CECA

S336

STBY_5V

S335

VCC_5V

D138

16

15

R197
100R
R196
100R

1 1OE

VCC 8

2 1A

2OE 7

3 1B

2B 6

4 A4

2A 5

CECB

TP119

TP118

RXB_CLKN

C126
100N
10V

2
1

12

SCL

TP117

A2
A1

U109
VCC

24LC02
WP

R697
22k

A0

TP120

Q101
2N7002

13

S155

VSS

11
7
1

100R

VGA_VSNC

VGA_HSNC

100R

50V

F199

3
2

PC_AUD_R
2

1 S1

RXB_1N

50V

D128

VGA_R

C125

200R
27P

JK103

F111

VGA_G

2 G1

RXB_1P

3 D2

G2 5
S2 4

SCL_HD2

3
RXB_2N
1

DOUBLE_LVDS

VCC_3V3

2
1

S341

VCC_3V3

S340

VCC_5V

LV_B_2P

LV_B_CLKN

LV_B_CLKP

LV_B_3N

LV_B_3P

S176

S180

S181
1

S183
S182

S179

LV_A_0P

LV_A_1N

LV_A_1P

LV_A_2N

LV_A_2P

LV_A_CLKN

LV_A_CLKP

LV_A_3N

LV_A_3P

LV_A_0N

C269
1U
16V

PROJECT NAME :

VCC_3V3

SINGLE_LVDS_CON
1

CN109

R678
10k

2
1

C268
1U
16V

CN105

CM2031
U116

C519
100N
10V

RXA_2P

R376
47K

C267
1U
16V

STBY_3V3

RXA_2N
2

SDA_HD1
2

10

R375
47K

12

14

RXA_2P

11

RXA_2P

SCL_HD1

13

S2 4

16

UPA672T

LV_A_CLKP
RXA_1P
RXA_2N

18

3 D2

RXA_1P
RXA_2N

G2 5

15

RXA_1P

U101

RXA_0P
RXA_1N

17

RXA_1N

2 G1

RXA_CLKP
RXA_0N

S178

20

D1 6

HPD1_OUT
SDA_HD1
SCL_HD1
CEC
RXA_CLKN

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1 S1

HP_DET_IN
DDC_DAT_IN
DDC_CLK_IN
CE_RMT_IN
TMDS_CK-_1
TMDS_GND_4
TMDS_CK+_1
TMDS_D0-_1
TMDS_GND_3
TMDS_D0+_1
TMDS_D1-_1
TMDS_GND_2
TMDS_D1+_1
TMDS_D2-_1
TMDS_GND_1
TMDS_D2+_1
GND_1
LV_SUPPLY
5V_SUPPLY

R681
10k

RXA_0P
RXA_1N

RXA_0P
7

HP_DET_OUT
DDC_DAT_OUT
DDC_CLK_OUT
CE_RMT_OUT
TMDS_CK-_2
TMDS_GND_5
TMDS_CK+_2
TMDS_D0-_2
TMDS_GND_6
TMDS_D0+_2
TMDS_D1-_2
TMDS_GND_7
TMDS_D1+_2
TMDS_D2-_2
TMDS_GND_8
TMDS_D2+_2
GND_2
CE_SUPPLY
N/C

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

19

SDA_A
SCL_A
CECA_ESD
RXA_CLKN
RXA_CLKP
RXA_0N

RXA_0N

TP126

S177

R373
47K
1

R374
47K
R217
4K7

PANEL_VCC
1

22

4K7
R214

24

TP123

21

DDC_WP

VCC_3V3

4K7
R213

23

26

R725
22k

VCC_3V3

28

C271
1U
16V

25

Q160
BC848B

27

RXA_CLKP
10

30

TP122

C270
1U
16V

29

VCC_3V3

11

A0

CN101

RXA_CLKN

VCC

LV_A_CLKN

12

C128
100N
10V

U108

VCC_5V

3
2

CECA

A1

SCL_A
SDA_A

24LC02
WP

CM2031
U117

VCC_3V3

DISP_EN/PWDN

A2

VCC_3V3

SCL

13

S156

5
2

VSS

SDA

S343

HPD1

CECA_ESD

TP124

TP125

PANEL_VCC

15

R195
100R
R194
100R

S342

LV_A_4N

C266
1U
16V

LV_A_4P

16

STBY_3V3
1

RXB_2P

VCC_12V

D142

17

RXB_2P

14

STBY_5V

LG_I/RQPDP

HD5V_A

RXB_1P
RXB_2N

CPU_GO/STBY

18

VCC_5V

S333

10

D141
1N4148

R520
1K

12

RXB_1P
RXB_2N

HD5V_A
S334
1

PDP_GO/BL_ON_OFF

19

VCC_5V

1N4148
2

11

HPLUGA

VCC_3V3

R218
4K7

14

RXB_0P
RXB_1N
SCL

HDMI_1

RXB_0P
RXB_1N

SDA

Q121
BC848B

RXB_CLKP
RXB_0N

13

1
3

RXB_CLKP
RXB_0N

16

R716
10k

15

HPD1_OUT

HPD2_OUT
SDA_HD2
SCL_HD2
CEC
RXB_CLKN

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

18

S159

HP_DET_IN
DDC_DAT_IN
DDC_CLK_IN
CE_RMT_IN
TMDS_CK-_1
TMDS_GND_4
TMDS_CK+_1
TMDS_D0-_1
TMDS_GND_3
TMDS_D0+_1
TMDS_D1-_1
TMDS_GND_2
TMDS_D1+_1
TMDS_D2-_1
TMDS_GND_1
TMDS_D2+_1
GND_1
LV_SUPPLY
5V_SUPPLY

17

47K
R381

HP_DET_OUT
DDC_DAT_OUT
DDC_CLK_OUT
CE_RMT_OUT
TMDS_CK-_2
TMDS_GND_5
TMDS_CK+_2
TMDS_D0-_2
TMDS_GND_6
TMDS_D0+_2
TMDS_D1-_2
TMDS_GND_7
TMDS_D1+_2
TMDS_D2-_2
TMDS_GND_8
TMDS_D2+_2
GND_2
CE_SUPPLY
N/C

20

HPD1

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

19

HPD2

SDA_B
SCL_B
CECB_ESD
RXB_CLKN

C520
100N
10V

S175 2
S173
1
S174
1

CN110
HDMI_2

SDA_HD2
2

R380
47K

LV_B_1P

50V

27P

C306

C5V6
1

D129

R379
47K

RXB_2P

LV_B_4N

PC_AUD_L

LV_B_2N

200R

LV_B_1N

F112
1

LV_B_0P

100N
10V

LV_B_4P

5
D104
4
NUP4004M5 2

3
1

VGA_VCOM

D1 6

U102

UPA672T

DDC_WP

60R

C302

RXB_0P
2

VGA_B

RXB_0N

CN115
VGA_CON

R726
22k

C5V6

27P

C304

50V

27P

50V

C303

2
1

27P

C305

Q161
BC848B

R283

CEC

S362

RXB_CLKP
10

R282

LV_B_0N

SCL_B
SDA_B

CECB_ESD

14

TP121

TP131

SDA

C293
100n
10V

R609
2K2

17

TP130
TP127
TP128

18

DDC_5V

100R

VCC
A0
WP
A1
SCL
A2
SDA GND

R610
2K2

10

5
D105
4
NUP4004M5 2

3
1

11

HD5V_B

D137
1N4148

R378
47K

U112
ST24LC21

S346

1N4148

13

R519
1K

HPLUGB

19

CECB

R215
4K7

14

U143
SN74CB3Q3305

D139
TP129

STBY_3V3

R279

DDC_5V

R216
4K7

R377
47K

C127
100N
10V

15

Q120
BC848B

1N4148

1
3

S154

R677
10K

R398
10K

R397
10K

D140

47K
R382
R717
10k

R698
22k

C462
10N
16V

HPD2_OUT

SCH NAME :

DIGITAL IN

DRAWN BY :

UTKU GKKAYA

17MB30-1
SHEET:

A3
3

OF:

11

5-17-2007_9:16

AXM

8
3.3V_D

3.3V_D

3.3V_D

C273
2

RESET_DVB

S307

S285

S104

SCLK

C406
100n
16V

2
1

RSTOUT

R605
1k

Q122
BC847B

REG

CI_5V_EN

INPACKB
3.3V_D

3.3V_D

SW_CTRL
SLEEP

S308

R221
4k7
R220
4k7

SDATA

R285
100R 2
R284
100R 2
R801
1
1k5
R464
1
1k5
R290
1
100R
R150
33R 2
R148
33R 2
C400
100n
16V
2

F130
3.3V

1
2

8
7
6
5

R128
100R
R1
R2
R3
R4
R289
100R
R512
100R
1

R151
33R
R400
10k
1

100R
1

C134
100n
10V

1
2
3
4

R291
100R

R149
33R
R287

TP134

1
2

C131
100n
10V

8
7
6
5

VCC
WC
SCL
SDA

RESET

E0
E1
E2
VSS

YCBCR[3]
YCBCR[2]
YCBCR[1]
YCBCR[0]

UART1_RX
UART1_TX

C133
100n
10V

RAM_VDD
R485
33R
1 R1
2 R2
3 R3
4 R4
R484
33R
1 R1
2 R2
3 R3
4 R4
R219
4k7 2
R401
10k 2
R357
330R 2

8
7
6
5

1
2
3
4
1

R286
100R

8
7
6
5
R127
100R
R1
R2
R3
R4

1k5
1

C135
2

1
2
3
4

10p
50V

C136
100n
10V

R292
100R

10

R522
1k 2 R523
R524 1
1k
1k 2 R521
R525 1
1k
1k 2

TP116

JTDI

C576
10p
50V

10p
50V

10V
100n

TP107

JTRST
1

C407
100n
16V

F_WE

R293
100R

TP115

100n
10V

U104
24C32

C454

4
TP114

JTMS

C453

47u
10V

R295
100R
R294
100R

JTDO

27_MHZ

JTRST
JTCLK
JTMS
JTDO
JTDI
TXD
RXD
3.3V_D
RESET
RSTOUT
PWMOUT
3.3V_D

TP113

JTCLK

C376

8
7
6
5

CN124

DQ12
DQ13
DQ14
DQ15
RAM_VDD

TP112

3.3V_D

R526
1k

F117

R403
10k

1.5V_D
UP_IRQ

1k5

F116

3.3V_D

SCLK
SDATA

4
YCBCR_HSNC
YCBCR_VSNC
ICLK
YCBCR[7]
YCBCR[6]
YCBCR[5]
YCBCR[4]

1.5V_D

3.3V_D

C141
100n
10V

2
1

DQ3
DQ2
C142
DQ1
100n
DQ0
10V
RAM_VDD

1
2
3
4

R488
33R
R1
R2
R3
R4

8
7
6
5

3.3V_D
2

2
1

C401
100n
16V

IDTV_SW_TX

1
2
3
4
8
7
6
5

R130
100R
R1
R2
R3
R4

R131
100R
R1
R2
R3
R4
2

C403
100n
16V

S351

100n
16V

10u

L117
1

2
1

C399
100n
16V

ENC_CVBS C272

L106

C322
10u
16V

1u
16V

C130
100n
10V

R329
220R

C321
10u
16V

2
1

R668
200R
R170
33R

3.3V_D

C377
220u
6V3

2
1

C738
1u
16V

C463

R299
100R

2
1

SPDIF_IN

2
2

10n
16V

C341
10p
50V

R408
10k

1.5V_D

1
1

60R
1

GRDYB

S352

F191
1

C146
100n
10V

ATX
1

RAM_VDD

60R

C748
22p
50V

100n
16V
C408

F132
1

100n
16V

C737
1u
16V

10u R399
1
10k
C378

10u

1.5V_D

2.5V

R174
1k
C398
100n
16V

L102

R670
200R
R669
200R

100n
16V

L118
1

100n
10V

C590
47u
6V3

10u
1

1
1

3.3V

R409
10k

C397

1
2

60R

F192
2

10u

C129

R143
150R

R175
1k
C396

100n
16V

1.5V_D

L112
1

60R

1.5V_D

R163
R162 1 33R 2
GCSB0
2
R161
33R
R_CHIP_EN
1
2
R160
33R
R_WRITE_EN
33R 2
R300
R_OUTPUT_EN
1
RADD22
33R 2 R169
1
RADD21
R168
33R 2
R494
2
33R
33R
RADD20
1 R1 8
RADD19
2 R2 7
RADD18
3 R3 6
RADD17
4 R4 5
RADD16

F148
1

60R
C565
IDTV_CVBS

2
1

C404
100n
16V

2
1

2
1

ENC_CVBS

22p
50V
C555
22p
50V

2
1

C554
22p
50V

C405
100n
16V

3.3V_D
RADD15
RADD14
RADD13
RADD12
RADD11
RADD10
RADD9
RADD8
1.5V_D

C402
100n
16V

RADD7
RADD6
RADD5
RADD4
RADD3
RADD2
RADD1
RADD0
RDATA15
RDATA14
RDATA13
RDATA12

1.5V

C409

F131

3.3V_D
IREQ

PROJECT NAME :
3.3V_D
RDATA11
RDATA10
RDATA9
RDATA8
RDATA7
RDATA6
RDATA5
RDATA4
RDATA3
RDATA2
RDATA1
RDATA0

1.5V_D
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
TS_STRT
TS_MERR
TS_VAL
TS_CLK

1
2
3
4

1
2
3
4

RXD

R511
100R

R495
33R
R1
R2
R3
R4

R129
100R
R1
R2
R3
R4
IDTV_SW_RX

1
2
3
4

VS_CI
2

GND_14
GND_13
VDD2_2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VDD2_1
GND_12
JTRST
JTCK
JTMS
JTDO
JTDI
TXD1B
RXD1B
NMI
RSTSWB
RSTOUT
PWMOUT
VDD3_4
GND_11
GND_10
CLK27IN
PAVDD
PAGND
VDD1_4
PPORT44
PPORT43
PPORT42
PPORT41
PPORT40
PPORT39
PPORT38
PPORT37
PPORT36
PPORT35
PPORT34
PPORT33
PPORT32
PPORT31
PPORT30
SCL0
SDA0
PPORT29
PPORT28
PPORT27
PPORT26
PPORT25
PPORT24
GND_9
VDD3_3
1
2
3
4

8
7
6
5

R559
100R

R404
10k

1
2

R699
300R

TXD

R296
100R
R166
33R

C145
100n
10V

8
7
6
5

100R

CARD_RESET
IOWR
IORD
CARD_DETECT
CI_3V_EN

R700
300R

R165
33R
R297
100R

1
2

RAM_VDD
1.5V_D

8
7
6
5

1
2
3
4

R167
33R
R164
33R
R298

8
7
6
5

S184

DQ7
DQ6
DQ5
DQ4

1
2
3
4

R502
33R
R1
R2
R3
R4

R152
33R

8
7
6
5

DQMO
LDQS

R153
33R

U103
UPD61115

108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

1
2
3
4

100n
10V

8
7
6
5

C442
100u
16V

PPORT23
PPORT22
PPORT21
PPORT20
PPORT19
PPORT18
PPORT17
PPORT16
PPORT15
PPORT14
PPORT13
PPORT12
DVDD_2
DGND_3
DGND_2
REF1
RSET1
AVDD_4
AGND_4
VAPB
AVDD_3
AGND_3
VAPR
DVDD_1
DGND_1
REF0
RSET0
AVDD_2
AGND_2
VACVBS
AVDD_1
AGND_1
VAY
TEST
GRDYB
ALRCK
ADO
ATX
ABCK
VDD1_3
GND_8
GND_7
AMCK
GCSB0
FCSB0
FWEB
FOEB
RADD22
RADD21
RADD20
RADD19
RADD18
RADD17
RADD16

R501
33R
R1
R2
R3
R4

R490
33R
R1
R2
R3
R4
R489
33R
R1
R2
R3
R4

R155
33R
R159
33R

8
7
6
5

2
1

C140

RAM_VDD

1
2
3
4

DCSB
DRASB
DCASB
DWEB

1
2
3
4

R154
33R

R499
33R
R1
R2
R3
R4

8
7
6
5

8
7
6
5

100n
10V

1
2
3
4

8
7
6
5

1
2
3
4

DADD3
DADD2
DADD1
DADD0
DADD10
DBA1
DBA0

1
2
3
4

R486
33R
R1
R2
R3
R4

R500
33R
R1
R2
R3
R4

RAM_VDD

R491
33R
R1
R2
R3
R4

8
7
6
5

8
7
6
5

C139

R487
33R
R1
R2
R3
R4

1
2
3
4

1
2
3
4

R498
33R
R1
R2
R3
R4

DADD12
DADD11
DADD9
DADD8
DADD7
DADD6
DADD5
DADD4

8
7
6
5

C138
100n
10V

R497
33R
R1
R2
R3
R4

R359
330R

8
7
6
5
1
2
3
4

R496
33R
R1
R2
R3
R4

R158
33R

8
7
6
5

RAM_VDD
1.5V_D
C144
100n
10V

R156
33R
R358
330R

GND_15
GND_16
DQ9
DQ8
DQS1
N/C_1
DQM1
N/C_2
DCLK
DCKE
DADD12
DADD11
VDD2_3
GND_17
VDD1_5
DADD9
DADD8
DADD7
DADD6
DADD5
DADD4
GND_18
GND_19
VDD2_4
DADD3
DADD2
DADD1
DADD0
DADD10
DBA1
DBA0
GND_20
VDD2_5
DCSB
DRASB
DCASB
DWEB
DQM0
N/C_3
DQ7
DQ6
DQ5
VDD2_6
GND_21
VDD1_6
DQ4
DQ3
DQ2
DQ1
DQ0
VDD2_7
GND_22
GND_23
VDD3_5

PPORT0
PPORT1
PPORT2
PPORT3
PPORT4
PPORT5
PPORT6
PPORT7
PPORT8
PPORT9
GND_1
GND_2
VDD1_1
PPORT10
PPORT11
RDATA0
RDATA1
RDATA2
RDATA3
RDATA4
RDATA5
RDATA6
RDATA7
RDATA8
RDATA9
RDATA10
VDD3_1
GND_3
RDATA11
RDATA12
RDATA13
RDATA14
RDATA15
RADD0
RADD1
RADD2
RADD3
RADD4
RADD5
RADD6
RADD7
GND_4
GND_5
VDD1_2
RADD8
RADD9
RADD10
RADD11
RADD12
RADD13
RADD14
RADD15
VDD3_2
GND_6

DQM1
NOTLCLK
LCLK
DCKE

C137
100n
10V

163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

R157
33R

DDR_REF

8
7
6
5

S185

C143
100n
10V

R492
33R
R1
R2
R3
R4

RAM_VDD
2

1
2
3
4

DQ11
DQ10
DQ9
DQ8
UDQS

162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109

60R

SCH NAME :

MPEG DECODER

DRAWN BY :

UTKU GKKAYA

17MB30-1
SHEET:

A3
4

OF:

11

5-17-2007_9:17

AXM

RAM_VDD
F186
3.3V_D

2
1

DQ3
DQ4
DQ5
DQ6
DQ7

C151
100N
10V

C150
100N
10V

2
1

LDQS

2
1

DQMO
DWEB
DCASB
DRASB
DCSB
DBA0
DBA1
DADD10
DADD0
DADD1
DADD2
DADD3

C147
100N
10V

DQ14
DQ13
DQ12
DQ11

2
1

RADD16
RADD15
RADD14
RADD13
RADD12
RADD11
RADD10
RADD9
RADD20
RADD21
FLASH_WE
RESET
RADD22
S188 2
1
S187
1
RADD20
RADD19
RADD18
RADD8
RADD7
RADD6
RADD5
RADD4
RADD3
RADD2

C149
100N
10V

DQ10
DQ9
DQ8

C152
100N
10V

2
1

UDQS

DQM1

2
1

C154
100N
10V

R363
15K

DDR_REF
2

2
1

C153
100N
10V

DCKE
DADD12
DADD11
DADD9
DADD8
DADD7
DADD6
DADD5
DADD4

C427
47u
16V

U115
M29W160B

DQ15

R362
15K

C156
100N
10V

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

C155
100N
10V

DQ1
DQ2

VSS_3
DQ15
VSSQ_5
DQ14
DQ13
VDDQ_5
DQ12
DQ11
VSSQ_4
DQ10
DQ9
VDDQ_4
DQ8
NC_5
VSSQ_3
UDQS
DNU_2
VREF
VSS_2
UDM
CK#
CK
CKE
NC_4
A12
A11
A9
A8
A7
A6
A5
A4
VSS_1

NOTLCLK
2

VDD_1
DQ0
VDDQ_1
DQ1
DQ2
VSSQ_1
DQ3
DQ4
VDDQ_2
DQ5
DQ6
VSSQ_2
DQ7
NC_1
VDDQ_3
LDQS
NC_2
VDD_2
DNU_1
LDM
WE#
CAS#
RAS#
CS#
NC_3
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD_3

R360
330R

DQ0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

600R

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A15
A14
A13
A12
A11
A10
A9
A8
A19
NC1
W
RP
NC2
NC3
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1

A16
BYTE
VSS2
DQ15A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS1
E
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

RADD17

RDATA15
RDATA7
RDATA14
RDATA6
RDATA13
RDATA5
RDATA12
RDATA4
RDATA11
RDATA3
RDATA10
RDATA2
RDATA9
RDATA1
RDATA8
RDATA0
R_OUTPUT_EN

2
1

C411
100n
16V

B
2
1

C410
100n
16V

R_CHIP_EN
RADD1

C148
100N
10V

U131
MT46V16M16

LCLK

S186

3.3V_D
RDATA0
RDATA1
RDATA2
RDATA3
RDATA4
RDATA5

X101
1
2
1

C485
2P2
50V

PWMOUT

X1
NC1
VIN
GND

27MHZ

2
1

C484
2P2
50V

X2
NC2
VDD
CLKOUT

RDATA8
RDATA9
RDATA10
RDATA11
RDATA12
RDATA13
RDATA14
RDATA15
ATX

F118

8
7
6
5

3.3V_D

1K5
R606
33k

C415
100n
16V

R469
22K
R471
22K

1
2
1
2

R473
22K

27_MHZ

C276
1U
16V

2
1

C440
10p
50V

R611
2K2
R612
2K2
R614
2K2
R613
2K2
R474
22K

R468
22K
R470
22K
R472
22K

RDATA6
RDATA7
1

R476
22K

U129
PI6CX100-27
1
2
3
4

R475
22K

1
2
1
2
1
2
1

R616
2K2
R615
2K2
R618
2K2
R617
2K2

E
U134
74V1G08
R_WRITE_EN
F_WE

1 A
5
2 B VCC
3 GND Y 4

3.3V_D
FLASH_WE
2
1

C522
100N
10V

PROJECT NAME :

SCH NAME :

MPEG MEMORY

DRAWN BY :

UTKU GKKAYA

17MB30-1
SHEET:

A3
5

OF:

11

5-17-2007_9:18

AXM

3.3V_BUF

C274
100n
10V

2
1

SW_CTRL_INV

1OE-

VCC

20

MD0

1A1

2OE-

19

MDI_7

2Y4

1Y1

18

MD1

1A2

2A4

17

U106

MDI_6

2Y3

MD2

1A3

MDI_5

MD3

MDI_4

9
10

74LCX244
2A3

15

2Y2

1Y3

14

1A4

2A2

13

2Y1

1Y4

12

GND

2A1

11

SW_CTRL_INV

1OE-

VCC

20

MCLK

1A1

2OE-

19

INPACKB

2Y4

1Y1

18

MVAL

1A2

2A4

17

SW_CTRL_INV

MD7

16

1Y2

MDI_0

MDI_1
MSTRT

MD6
MDI_2
MD5
MDI_3
MD4

U107

2Y3

1A3

1Y2

74LCX244

C292
100n
10V

2
1

SW_CTRL_INV

1OE-

VCC

20

MDO_0

1A1

2OE-

19

TS7

2Y4

1Y1

18

MDO_1

1A2

2A4

17

CI_POWER_CTRL
MDI_CLK
INPACKB_CI

16

MDI_VAL

2Y3
1A3

15

MDO_2

TS5

MDO_3

TS4

9
10

2Y2

1Y3

14

1A4

2A2

13

2Y1

1Y4

12

10

GND

2A1

11

MDI_STRT

U121

TS6

2A3

3.3V_BUF

3.3V_BUF

1Y2

74LCX244

16

2A3

15

2Y2

1Y3

14

1A4

2A2

13

2Y1

1Y4

12

GND

2A1

11

C328
100n
10V

2
1

SW_CTRL_INV
TS0
MDO_7

SW_CTRL_INV

1OE-

VCC

20

MDO_CLK

1A1

2OE-

19

REG_CI

2Y4

1Y1

18

MDO_VAL

1A2

2A4

17

RESET_CI

TS1
MDO_6
TS2
MDO_5
TS3

3.3V_BUF

U128

2Y3

1A3

1Y2

74LCX244
2A3

15

IOWR_CI

2Y2

1Y3

14

MDO_STRT

1A4

2A2

13

IORD_CI

2Y1

1Y4

12

10

GND

2A1

11

MDO_4

C329
100n
10V

2
1

CI_POWER_CTRL
CI_POWER_CTRL

RADD0
A7

TS_CLK
REG

16

3.3V_BUF

RADD1
A6

TS_VAL
CARD_RESET

RADD2
A5

TS_MERR
IOWR

RADD3

IORD

1OE-

VCC

20

1A1

2OE-

19

1Y1

18

2A4

17

2Y4

1A2

U142

2Y3

1A3

1Y2

74LCX244
2A3

15

2Y2

1Y3

14

1A4

2A2

13

2Y1

1Y4

12

10

GND

2A1

11

C364
100n
10V

2
1

CI_POWER_CTRL
CI_POWER_CTRL

RADD8
OE_CI

A0
RADD7

16

A4

TS_STRT

3.3V_BUF

RADD9
A14

A1
RADD6

RADD10
A13

A2
RADD5

RADD11
A12

A3
RADD4

1OE-

VCC

20

1A1

2OE-

19

2Y4

1Y1

18

1A2

2A4

17

1Y2

16

U145

2Y3

1A3

74LCX244
2A3

15

2Y2

1Y3

14

1A4

2A2

13

2Y1

1Y4

12

10

GND

2A1

11

C365
100n
10V

CI_POWER_CTRL

A8
R_OUTPUT_EN
A9
RADD14
A10
RADD13
A11
RADD12

3.3V_BUF
3.3V_BUF
3.3V_BUF

TS7

TS6

MD2

TS5

MD3

1A1

2OE-

19

2Y4
1A2

2A4

17

1Y2

16

U146
2Y3

74LCX244
2A3

15

2Y2

1Y3

14

1A4

2A2

13

1A3

SW_CTRL

18

1Y1

SW_CTRL

MCLK

2
3

GRDYB

TS0
MD7
TS1

MVAL

IREQ

MERR

TS2

CE_1_CI

MD5

MSTRT

MD6

1OE-

VCC

20

1A1

2OE-

19

2Y4

1Y1

1A2

2A4

17

1Y2

16

U147
2Y3

18

74LCX244
2A3

15

2Y2

1Y3

14

1A4

2A2

13

1A3

CI_POWER_CTRL

RDATA9

WAIT_CI

68
1

34

67

33

66

32

R414
10K

RDATA11

3.3V_BUF

RDATA12
MDO_2

TS_VAL

D2
D1

IREQ_CI

MDO_1

TS_MERR

MDO_0

64

30

D0

MDO_STRT

63

29

A0

65

31

RDATA13

2A1

11

10

MD4

2Y1

1Y4

12

GND

2A1

11

TS_STRT
INPACKB_CI
R416
1
10K
R418
2
10K

R_WRITE_EN

MDO_VAL

62

28

A1

REG_CI

61

27

A2

60

26

A3

59

25

A4

WAIT_CI

58

24

SW_CTRL

R411
10K

A5
IORD
R_OUTPUT_EN

3.3V_BUF

A6

57

23

56

22

A7

55

21

A12

54

20

A4

B3

16

U105
74LCX245

A5

B4

15

A6

B5

14

A7

B6

A8

B7

12

10

GND

B8

11

A0
B0
O0
A1
B1
O1
GND

VCC
A2
B2
O2
A3
B3
O3

14
13
12
11
10
9
8

CI_5V_EN
CI_3V_EN

D1
D2
D3
D4

D6
D7

2
1

C464
100n
10V

S353

CI_POWER_CTRL

MDI_VAL

CI_PWR

52

18

CI_PWR

51

17

50

16

IREQ_CI
R415
10K 1

C421
100n
16V

3.3V
R592
47K

MDI_1

48

14

A14

MDI_0

47

13

A13

MDI_STRT

46

12

A8

IOWR_CI

45

11

A9

IORD_CI

44

10

A11

43

OE_CI

R721
10k

15

R198
47k

12V

Q175
BC848B

2
1

5V
2

1
2

Q129
BC847B

E
F134
1

42

A10

MDO_7

41

CE_1_CI

MDO_6

40

D7

MDO_5

39

D6

MDO_4

38

D5

37

D4

36

D3

35

MDO_3
1

R413
10K

CD_1_CI

C277
1

CI_PWR

2
2

1u
16V

C444
10u
16V

2
1

C348
100N
25V

R722
10k

R383
47K

R384
47K

12V

CI_5V_EN

S127

R410
10K

Q127
BC847B

PROJECT NAME :

CN120

60R

R420
10K
R417
10K

S279

R719
10k

R225
4K7

Q165
BC848B
1

S278

VS_CI

CD_2_CI

C621
1u
16V

R590
1k
R591
1k

Q130
BC847B

Q155
BC847B

3.3V

CD_1_CI

CI_3V_EN

R718
10k

R224
4K7

Q103
BSH103

R720
10k

CARD_DETECT

49

WE_CI

10k
R796

MDI_2

S337

19

D5

CI_DIR

53

D0

Q170
BSH103

R421
10K

17

MDI_CLK
2

B2

MDI_4

MDI_3

A3

CI_POWER_CTRL

3.3V_BUF

B1

C465
100n
10V

3.3V_BUF

Q150
BSH103

MDI_5

1
2
3
4
5
6
7

GCSB0

C419
56p MDI_7
50V
MDI_6

A2

18

U113
74LVC00

Q126
BC847B

RESET_CI
MDO_CLK

GND

WE_CI

TS3

12

1Y4

19

13

RDATA15
SW_CTRL_INV

OE-

RDATA14

10

2Y1

GCSB0

A1

R223
4K7

TS4

RDATA10
CD_2_CI
R419
2
10K

TS_CLK

20

VCC

RDATA8
C428
47u
16V

MD1

20

DIR

VCC

CI_DIR

R795
10k

MD0

1OE-

3.3V_BUF

60R

5V

F133
1

3.3V_D

C413
100n
10V

SW_CTRL

R412
10K

C412
100n
10V

SCH NAME :

IDTV CI

DRAWN BY :

UTKU GKKAYA

17MB30-1
SHEET:

A3
6

OF:

11

5-17-2007_9:19

AXM

C177

R629
100K

SC_G

HPLUGB
SDA_HD2
SCL_HD2
RXA_CLKN
R780
1
RXA_CLKP
10R
R781
1
RXA_0N
10R
RXA_0P

SC_SNC

C175

RXA_2N
RXA_2P

R_PB

100N
10V

AVDDA

C380
1

VGA_HSNC
VGA_VSNC
C182

R_SNC

1N
50V
C200
RCA_Y

75R
R573

R_Y

C174
1

75R
R566

75R
R565

C189
SC1_VCOM

DTV_CVBS

C190
T_VCOM

75R
R567

100N
10V

F135
1

C204

C170

SIF_GND

C324

SVHS_Y

60R
1

AVDD_AU
10U
16V

2
1

100N
10V

10u
25V

AVDD_SIF
2

100N
10V

C285

C323

75R
R563

10U
16V

C169

60R
C294 SC_C/DMP_CVBS

SC2_C/DMP_CVBS

1U
16V

47N
16V

S189

100N
10V

C157

2
1

100N
10V

2
1

100N
10V
C159

100N
C158
10V

2
1

100N
10V
C161

2
1

100N
10V
C160

100N
10V
C164

2
1

100N
10V
C163

C162

LV_A_0N
LV_A_0P
LV_A_1N
LV_A_1P
LV_A_2N
LV_A_2P
LV_A_CLKN
LV_A_CLKP
LV_A_3N
LV_A_3P
LV_A_4N
LV_A_4P

2
1

100N
10V

2
1

100N
10V
C201

100N
10V
C165

100N
10V
C168

2
1

100N
10V
C167

C166

VDDP
VDDC

VDDP

VDDP

MDATA[0]
MDATA[1]
MDATA[2]
MDATA[3]

F136

MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]

VCC_3V3

C632
2

AUD_IN1_R
AUD_IN1_L
AUD_IN0_R
AUD_IN0_L
AVDD_AU

47N
16V

C633
10u
25V

100N
10V

2
1

2
1

2
1

100N
10V
C193

2
1

100N
10V
C198

100N
10V
C197

2
1

100N
10V
C199
2

100N 10V

S_SDA

UART0_RX
UART0_TX
SCL
SDA

C286

AUD_IN0_R

S190

SCL_2
SDA_2

1U
16V
R112
12K

C389
2
1

R425
10K 2
SC2_AUD_R_IN

C388
2
1

AUD_IN1_L

1U
16V
R110
12K

C387

AUD_IN2_R

1N
50V
R423
10K 2
YPBPR_AUD_R

1
1

1U
16V
R114
12K

C386
2
1

AUD_IN2_L

AVDD_MEMPLL
VDDM

1U
16V
R109
12K

C385
2
1

SEL_AUD_R
C384
1

SEL_AUD_L

1U
16V

C383

16V
C278
1
1

1N
50V

C287

MONO_IN

1U
16V

AUD_IN3_L

1N
50V

C279
AUD_IN3_R

1N
50V R422
1
10K 2
YPBPR_AUD_L

C280

WEZ
CASZ

C281

VDDM

1N
50V R424
1
10K 2
SC2_AUD_L_IN

C282

VDDC

RASZ
BA0
BA1
MCLK_DDR
MCLKZ

1N
50V

1U
16V
R111
12K

R426
10K 2
SC1_AUD_L_IN

MADR[7]
MADR[6]
MADR[5]
MADR[4]
MADR[3]
MADR[2]
MADR[1]
MADR[0]

1N
50V

C283
AUD_IN1_R

C390
2

NC

R176
R222 1 100R
1
2
100R
MADR[11]
MADR[10]
MADR[9]
MADR[8]

1U
16V
R113
12K

C284

VDDP

R427
10K 2
SC1_AUD_R_IN

1
1

AUD_IN0_L

NVM_WP
GPIO_15
CEC
IDTV_SW
UP_IRQ
GPIO_12
RGB_SW_1

C181

PWM_1
PWM_0
AFC
SC2_PIN8
SC1_PIN8
KEY_PAD

C180

100u
16V

VDDM
UDQM
LDQM
DQS[0]

VDDM

SVHS_C

MDATA[8]
MDATA[9]
MDATA[10]
MDATA[11]
VDDM
MDATA[12]
MDATA[13]

MDATA[14]
MDATA[15]
DQS[1]
VDDC

75R 1
R582 2 75R
R581

75R 1
2
R562 2 75R
R580
R302
1
R305
100R
2
R303
100R
1
R304
100R
100R 2
SDO
SCZ
SDI
SCK

S_SCL

C202
10V
100N

MCLKE

VDDP
GPIO_8
SPDIF_OUT
GPIO_7
LED2
LED1
LG_I/RQPDP
GPIO_3
AC_INFO
MUTE_AMP
PANEL_VCC_ON/OFF
AUD_OUT0_R
AUD_OUT0_L
AUD_OUT1_R
AUD_OUT1_L
AUD_OUT2_R
AUD_OUT2_L
AUD_OUT3_R
AUD_OUT3_L
MONO_IN
AUD_IN3_R
AUD_IN3_L
AUD_IN2_R
AUD_IN2_L

C295

C194

75R
R561
75R
R560

100N
10V

47N
16V

FAV_C

75R
R568

VDDM

75R
R570

C327

128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

VCC_3V3

LV_B_0N
LV_B_0P
LV_B_1N
LV_B_1P
LV_B_2N
LV_B_2P
LV_B_CLKN
LV_B_CLKP
LV_B_3N
LV_B_3P
LV_B_4N
LV_B_4P

YCBCR[3]
YCBCR[2]
YCBCR[1]
YCBCR[0]
YCBCR_VSNC
YCBCR_HSNC
GPIO_23
ICLK
GPIO_22
GPIO_21
PWDN_VD
RESET_EXT
S191
S192

AV_CVBS

C296

C191
1

AVDD_SIF

47N
16V

FAV_Y

UART1_TX
UART1_RX

VDDP
IR
IO3_EXT_TVL

STBY_3V3

1
1

VDDC

10V
100N
2

RGB_SW_2

MCLKE
MVREF
UDQM
LDQM
DQS[0]
MDATA[0]
MDATA[1]
MDATA[2]
MDATA[3]
VDDM1
MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]
VDDM2
GND4
MDATA[8]
MDATA[9]
MDATA[10]
MDATA[11]
VDDM3
MDATA[12]
MDATA[13]
GND15
MDATA[14]
MDATA[15]
DQS[1]
VDDC2
GND11
VDDP2
GPIOF[9]
GPIOF[8]
GPIOF[7]
GPIOF[6]
GPIOF[5]
GPIOF[4]
GPIOF[3]
GPIOF[2]
GPIOF[1]
GPIOF[0]
AUOUTR0
AUOUTL0
AUOUTR1
AUOUTL1
AUOUTR2
AUOUTL2
AUOUTR3
AUOUTL3
AUMONO
AUR3
AUL3
AUR2
AUL2
AUCOM
AUR1
AUL1
AUR0
AUL0
AVDD_AU
AUVREF
AUVRADP
AUVRADN
GND1
SIFM

75R
R564

AVDDA
R727
1
100R

C297

FAV_CVBS

SIF

47N
16V

R405
100R

SC2_CVBS

T_CVBS

CVBS1_OUT
CVBS0_OUT

C298

SC2_CVBS_IN

100N
10V

47N
16V

75R
R569

SC1_CVBS

R859
75R

C299

SC1_CVBS_IN

100N
10V

47N
16V

R_PB
R_SNC
R_Y
R_PR
SVHS_C
SVHS_Y
SC_C/DMP_CVBS
SC2_CVBS
DTV_CVBS
AV_CVBS
SC1_CVBS

22p
50V

C300

IDTV_CVBS

SC_G
SC_SNC
SC_R
R769
R301 1 100R
2
R667
100R
1
100R

T_CVBS
C749

47N
16V

100N
10V

SC_B

AVDDA
SC2_C/DMP_CVBS
ADC_OPT
SC_FB

100N
10V

100N
10V

100N
10V

C301

TUN_CVBS

100N
10V

C186

PC_B
PC_SOG
PC_G
PC_R

C188

C187
RCA_VCOM

R_PR

75R
R572

S194

100N
10V

VGA_VCOM
RCA_PR

2
1

C185

100N
10V

S193

R140 HPLUGA
390R 2
SDA_HD1
SCL_HD1

100N
10V

R786
10R

U118
MST6W82BL

2
1

60R

F140

1N
50V
S329 2

PC_AUD_R

1U
R193
12k 2

R723
10k

IF_MONO

R784
10R
R785
10R

2
1

C382
1N
50V

PROJECT NAME :

17MB30-1

A3

75R
R571

R782
10R
R783
10R

VCC_2V5
2

100N
10V
R429
1
10K

RCA_PB
2

AVDDA
RXA_1N
RXA_1P

STBY_1V2

C594 60R
47u
6V3

AVDDA

PWM_3
PWM_2

100N
10V
R428
10K

75R
R575

SC_R

1
2

100N
10V

R779
10R

SCART_R

C176 1N
50V

R774
10R

192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129

C171

PWM3/MCUCFG3
PWM2/MCUCFG2
NC
NC1
GPIOB[6]
GPIOB[5]/UART1_TX
GPIOB[4]/UART1_RX
VDDC
GND9
VDDP3
IRIN
INT
DDCA_CK
DDCA_DA
DDCR_CK
DDCR_DA
PWM1/MCUCFG1
PWM0/MCUCFG0
SAR3
SAR2
SAR1
SAR0
SDO
SCZ
SDI
SCK
GND5
VDDP5
ALE
RDZ
WRZ
AD[7]
AD[6]
AD[5]
AD[4]
AD[3]
AD[2]
AD[1]
AD[0]
MADR[11]
MADR[10]
MADR[9]
MADR[8]
VDDC1
GND13
VDDM
MADR[7]
MADR[6]
MADR[5]
MADR[4]
MADR[3]
MADR[2]
MADR[1]
MADR[0]
WEZ
CASZ
AVDD_MEMPLL
VDDM4
GND10
RASZ
BARD[0]
BARD[1]
MCLK
MCLKZ

C195

RXB1N
RXB1P
GND12
RXB2N
RXB2P
HPLUGB
DDCDB_DA
DDCDB_CK
RXACKN
RXACKP
GND
RXA0N
RXA0P
AVDD_DVI
RXA1N
RXA1P
GND8
RXA2N
RXA2P
HPLUGA
REXT
DDCDA_DA
DDCDA_CK
HSYNC1
VSYNC1
VCLAMP
REFP
REFM
BIN1P
SOGIN1
GIN1P
RIN1P
VCOM3
BIN0P
VCOM2
GIN0P
SOGIN0
RIN0P
AVDD_ADC1
GND14
HSYNC0
VSYNC0
VSYNC2
BIN2P
SOGIN2
GIN2P
RIN2P
C1
Y1
C0
Y0
CVBS3
CVBS2
CVBS1
VCOM1
CVBS0
VCOM0
AVDD_ADC
CVBSOUT1
CVBSOUT0
GND2
SIF0P
AVDD_SIF
SIF1P

75R
R578

R773
10R

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

R772
10R

100N C379
10V

2
1

RXB_2N
RXB_2P

C330
100n
10V

R771
10R

SCART_G

RXB_1N
RXB_1P

100N
10V
C178

HW_RESET

C203

75R
R574

SC_B

100N
10V

60R

F141

100N
10V

SCART_B

A
2

C591
47u
6V3

VDDM
C196

100n
10V
3
VCC
U132
GND RST MAX809LTR
1
2
R666
1
100R 2

R778
10R

R121
1M

100N
10V

27P
50V

C192

75R
R577

VDDC3
VDDP6
LVA4P/NC
LA4M/NC
LVA3P
LVA3M
LVACKP
LVACKM
LVA2P
LVA2M
LVA1P
LVA1M
LVA0P
LVA0M
VDDP4
GND3
LVB4P/NC
LVB4M/NC
LVB3P
LVB3M
LVBCKP
LVBCKM
LVB2P
LVB2M
LVB1P
LVB1M
LVB0P
LVB0M
VDDP1
GND7
LCK/GPIOE[3]
LDE/GPIOE[2]
LVHSYNC/GPIOE[1]
LVSYNC/GPIOE[0]
ICLK
IDE
IHSYNC
IVSYNC
DI[0]
DI[1]
DI[2]
DI[3]
VDDP
DI[4]
DI[5]
DI[6]
DI[7]
VDDC4
GND6
DI[8]
DI[9]
DI[10]
DI[11]
DI[12]
DI[13]
HWRESET
XOUT
XIN
AVDD_MPLL
RXBCKN
RXBCKP
AVDD_DVI1
RXB0N
RXB0P

C414
STBY_3V3

PC_R

C634
100u
16V

F142

193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256

60R

VDDC
VDDP

R777
10R
AVDDAR776
1
R775
10R
10R 2

C179

VGA_R

F139
1

X102

2
1

100N
10V

C172

C308

14.31818MHz

75R
R579

27P
50V

C325

PC_G

100N
10V

C63660R
100u
16V

10U
16V

VGA_G

AVDD_MPLL

VDDP

YCBCR[7]
YCBCR[6]
YCBCR[5]
YCBCR[4]

C173
STBY_3V3 F137

STBY_3V3

C307

PC_SOG

1N
50V
C184

C332

C381

10U
16V

C326

VDDC

60R

100N
10V

10U
16V

VCC_3V3

PC_B

AVDD_MEMPLL
2

100N
10V

75R
R576

F138
1

HW_RESET
RESET_DVB
AUD_SW_2
AUD_SW_1
GPIO_27
GPIO_26
SPDIF_IN

C183

VGA_B

4
RXB_CLKP
RXB_CLKN
AVDD_MPLL

RXB_0P
RXB_0N

AUD_COM

SCH NAME :

SCALER

DRAWN BY :

UTKU GKKAYA

SHEET:

OF:

11

5-17-2007_9:20

AXM

CASZ
RASZ

F190
1

R319
100R

CE#
VDD 8
SO
HOLD# 7
WP#
SCK 6
VSS
SI 5

100R
2
C747 R320
1p
50V

C746
1p
50V

2
1

R254
4K7
R232
4K7
R231
4K7
R255
4K7
R228
4K7

IDTV_SW

VDD_2V5_DMC

60R

C209
100N
10V

C506
220u
6V3

GPIO_15

S229

PROTECT

NVM_WP
LG_I/RQPDP

F114

SCK
1

VDD_2V5_DMQ

60R

SDI

C750
22p
50V

2
1

2
1

LED1

C736
100N
10V

C210
100N
10V

2
1

C420
220u
6V3

MVREF_D

S234

GPIO_8

S235

VCC_5V

VDD_2V5_DMQ

R439
10K

STBY_5V

2
1

C211
100N
10V

2
1

C391
1N
50V

RGB_SW_1
DISP_EN/PWDN

CN116

GPIO_7

PDP_GO/BL_ON_OFF
VDD_2V5_DMC

S349

C214
100N
10V

C213
100N
10V

2
1

C212
100N
10V

2
1

2
1

C218
100N
10V

C219
100N
10V

2
1

2
1

C215
100N
10V

C216
100N
10V

2
1

2
1

C217
100N
10V

PWM_2

S312

2
2

S311

R440
10K

S213

IR

Q132
BC848B

GPIO_22

AUD_SW_2

GPIO_23

RESET_DVB

GPIO_27

R659
4k7

S314

IO1_EXT

S315

IO2_EXT

DMP_IR_SW STBY_5V

R310
100R

IR_IN

CN108

S_SCL

S_SDA

SW_VER_SEL

R314
100R
R313
100R

R664
4k7

2
1

2
2

R658
4k7

AUD_SW_1

C5V6

S_SDA

RS232

PROJECT NAME :

17MB30-1

A3

R583
75R
R584
75R

IDTV_SW_RX

C5V6
D132

Q137
BC848B

2
S_SCL

R385
47K

SERVICE_CON
2

D131

R311
100R
R312
100R

C5V6
D114

STBY_5V S210
1

IDTV_SW_TX

NC

DMP_IR

C5V6

CN117

R724
22k

SDA

R125
4K7

C431
1u
16V

D115

1
2
1

100N
10V

C333

10U
16V

C221

R126
4K7

R352
22K

RS232

S199

STBY_3V3

4
2

C288
22u
25V

STBY_5V

S289

DMP_IR_SW

SCH NAME :

SCALER MEMORY / IO

DRAWN BY :

UTKU GKKAYA

SHEET:

BRT_CNTL

F167

R655
4k7

75R

VCC_12V
SCL

S200

R259
4K7
R258
4K7
R257
4K7

SDA_2
2

S206

STBY_3V3

SCL_2

R341
4k7

VCC_5V

S288

S205

2
1

R430
10K

2
1

R432
10K

R434
10K
1

R435
10K

2
1

UART0_TX

STBY_3V3
CN125

R244
4K7
R243
4K7
R242
4K7
R656
4K7
1

GPIO_21

MOTOR_CONT

CN121

UART0_RX

SW_VER_SEL

D111

C5V6
D113

C5V6

PWDN_VD

GPIO_26

Q133
BC848B

C630
100p
50V

LED2

LED1

R348

22K

R256
4K7

S313

NC

Q134
BC848B

R622
4k7
R653
4k7

RESET_EXT

GPIO_24/25

ADC_OPT

PWM_1

S202
S201

NC

R441
10K
1

R431
10K
1

YCBCR_HSNC
YCBCR_VSNC

SW_VER_SEL

PWM_3

VCC_5V

C629
100p
50V

2
2

R433
10K
1

R436
10K

C5V6

NC

PWM_0

D130

100N
10V

2
1

C205

22K

R350

R437
10K

R227
4K7
R229
4K7

CN111

KEY_PAD

D
2

R338
1K

S216

STBY_3V3

NC

SCL

STBY_3V3

R349
22K

STBY_3V3

PWM_0

RGB_SW_2

C638
10p
50V

STBY_3V3

Q135
BC848B

Q139
BC848B

2
1

C639
10p
50V

R331
220R

4K7
R230

22K
R351

SDA

2
3

S215

S348

R330
220R

Q136
BC848B

2
1

100N
10V

C206

STBY_5V

R226
4K7

STBY_3V3

IR_IN

STBY_5V

STBY_3V3

LED2

STBY_5V

F113
1

VCC_2V5

R317
100R

UP_IRQ

VDD_2V5_DMC

STBY_3V3

STBY_3V3

MADR[7]
MADR[6]
MADR[5]
MADR[4]

1
2
3
4

STBY_3V3

R316
100R

Q131
BC848B

MADR[11]
MADR[10]
MADR[9]
MADR[8]

SDO

U110
SST25VF512A

R315
100R

SCZ

STBY_3V3

C222
100N
10V

R318
100R

200R

1
2
3
4

1
2
3
4

CS#
VCC
SO
HOLD#
WP#
SCLK
GND
SI

R132
100R
R1
R2
R3
R4

8
7
6
5

R685
22K

8
7
6
5

8
7
6
5

MCLKE

R136
100R
R1
R2
R3
R4

1
2
3
4

TP101

1
2
3
4

R236
4K7
R239
4K7
R238
4K7
R237
4K7

U127
MX25L512

R133
100R
R1
R2
R3
R4

MCLK_DDR
R742
100R

8
7
6
5

MADR[0]
MADR[1]
MADR[2]
MADR[3]

DDC_WP

Q138
BC848B

22K
R347

2
2

R741
4K7

C744
1p
50V

S219

C745
1p
50V

TP102

GPIO_3
2

R745
100R

1
1

TP103

R602
150R

LDQM

R743
100R

MCLKZ
2

BA0
BA1

CPU_GO/STBY
3

MVREF_D
R307
100R

R104
22R

1
2

AC_INFO

TP104
TP105
TP106
TP108

S226

WEZ

R103
22R
R105
22R

IO3_EXT_TVL
GPIO_12

DQS[0]

R309
100R

SCL_2

PANEL_VCC_ON/OFF

MUTE_AMP
R306
100R

SDA_2

UDQM

U135

MDATA[3]
MDATA[2]
MDATA[1]
MDATA[0]

VDD_2V5_DMC

8
7
6
5

VDD_2V5_DMQ
2

VDD_2V5_DMQ

STBY_3V3

MDATA[7]
MDATA[6]
MDATA[5]
MDATA[4]

R308
100R

1
2
3
4

STBY_3V3

8
7
6
5

DQS[1]

VDD_2V5_DMQ

R134
100R
R1
R2
R3
R4
R135
100R
R1
R2
R3
R4

1
2
3
4

VDD_2V5_DMQ

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

VSS3
DQ15
VSSQ5
DQ14
DQ13
VDDQ5
DQ12
DQ11
VSSQ4
DQ10
DQ9
VDDQ4
DQ8
NC8
VSSQ3
UDQS
NC7
VREF
VSS2
UDM
/CK
CK
CKE
NC6
NC5
A11
A9
A8
A7
A6
A5
A4
VSS1

R249
4K7
R253
4K7
R251
4K7
R250
4K7

TP109
TP110
TP111
TP132

TP133

NVM_WP
SCL_2
SDA_2

VDD1
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ2
DQ5
DQ6
VSSQ2
DQ7
NC1
VDDQ3
LDQS
NC2
VDD2
NC3
LDM
/WE
/CAS
/RAS
/CS
NC4
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD3

8
7
6
5

VCC
WC
SCL
SDA

VDD_2V5_DMQ

8
7
6
5

R248
4K7
R235
4K7
R241
4K7
R240
4K7
R234
4K7
R252
4K7

E0
E1
E2
VSS

1
2
3
4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

1
2
3
4

MDATA[12]
MDATA[13]
MDATA[14]
MDATA[15]

STBY_3V3

200R

100n
10V

8
7
6
5

1
2
3
4

R245
4K7
R247
4K7
R246
4K7
R233
4K7
R665
4k7

F188
1

MDATA[8]
MDATA[9]
MDATA[10]
MDATA[11]

4
HY5DV281622DT-5

VDD_2V5_DMC

R438
10K

C618

U144
24C32

3
R137
100R
R1
R2
R3
R4
R138
100R
R1
R2
R3
R4

OF:

11

5-17-2007_9:21

AXM

F200
1

U122
PI5V330

FAV_Y_VD

SC1_CVBS_IN

R550
300R

C227
2
1

100N
10V

R353
22K
2

C229
2
1

S260

S237

TUN_VD

100N
10V

R199
100R

R335
100R
1

2
1

16
15
14
13
12
11
10
9

C224
2

SC2_CHR
DMP_CVBS
SC2_C/DMP_CVBS
SC2_B
DMP_B
S261

C223

R556
300R

C235

2
1

FAV_C

75R
R599

FAV_C_VD

100N
10V

(SC1/SC2/DMP)_ RGB_SW

FAV_VD

100N
10V

R389
100R

FAV_CVBS

VCC
EN
S1D
S2D
DD
S1C
S2C
DC

R549
300R

R598
75R

S259

IN
S1A
S2A
DA
S1B
S2B
DB
GND

TUN_CVBS

2
1

SC2_G
DMP_G

1
2
3
4
5
6
7
8

SC2_R
DMP_R

100N
10V

U123
PI5V330

SC2_VD

100N
10V

C248

R528
1K

R558
300R

SC2_CVBS_IN

RGB_SW_2

R860
4k7

DMP_VS

SC1_VD

100N
10V

S363

Q178
BSN20

C233
2

R204
100R

STBY_5V

SCART_B

R557
300R

FAV_Y

SCART_G

100N
10V

SC_FB

SC1_B

SC2_CHR

SC1_FB
SC2_FB

C237

Q186
FDN336P

SC2_R

SCART_R
SC1_G

16
15
14
13
12
11
10
9

C225

VCC
EN
S1D
S2D
DD
S1C
S2C
DC

R327
100R

R354
22K

SC1_R

IN
S1A
S2A
DA
S1B
S2B
DB
GND

VCC_5V

1
2
3
4
5
6
7
8

60R
10V
100N

RGB_SW_1

VCC_5V

R527
1K

F146
VCC_5V

18

17

20

19

IO3_EXT_TVL
DMP_IR

VCC_5V_EXT

S354

25

EXT_R_OUT
EXT_L_OUT

SDA

28

27

IO1_EXT

SCL

30

29

IO2_EXT

SDA
SCL

VDD_1V8_VD

2
1

R504
33R
R1
R2
R3
R4

8
7
6
5

U133
ADV7180

VDA_1V8_VD
1

C236
2
1

PWDN_VD

VDD_1V8_VD

100N
10V

C486
1

VDD_1V8_VD

2
1

R171
1
33R
C481
10P
50V

C487
1

ICLK
2
1

47P
50V

47P
50V

C482
10P
50V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

C469
10N
16V

YCBCR[7]
YCBCR[6]
YCBCR[5]
C243 YCBCR[4]
100N
10V

1
2
3
4

AGND1
PVDD
ELPF
PWRDWN
NC2
NC1
P0
P1
DGND3
DVDD1
XTAL
XTAL1
LLC
P2
P3
P4

S355

RESET_EXT
R173
R172 1 33R
2
33R

AIN6
NC8
RESET
ALSB
SDATA
SCLK
GPO3
GPO2
DGND4
DVDD2
P15
P14
P13
P12
FIELD
VS

27MHZ

23

10N
16V
R340
1K6

X103

S356

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

26

CVBS_EXT

S249

24

21

UART0_TX

22

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

FAV_C_VD
UART0_RX

C466

S258

R122
1M

VCC_5V_EXT

C244
100N
10V

15

16

DMP_AUD_R

13

C470
10N
16V

11

14

100N
10V

12

VCC_3V3
2

100N
10V

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

S255

R260
4K7

RESET_EXT

C238

DMP_AUD_L

10

C239

DMP_IR_SW

DMP_B

DMP_CVBS

R819
2k2

R600
75R

R813
1k

100N
10V

DMP_VS

VDA_1V8_VD

TUN_VD
SC1_VD

DMP_G

CN106

FAV_Y_VD
SC2_VD
FAV_VD

C240

C334

10U
16V

75R 1
R588
75R 1
R589
75R 1
R585
DMP_R

AIN5
AIN4
AIN3
NC7
NC6
AGND3
NC5
NC4
AVDD
VREFN
VREFP
AGND2
AIN2
AIN1
TEST_0
NC3

60R

INTRQ
HS
DGND1
DVDDIO_1
P11
P10
P9
P8
SFL
DGND2
DVDDIO_2
GPO1
GPO0
P7
P6
P5

VCC_5V_EXT

1
2
3
4

R503
33R
R1
R2
R3
R4

8
7
6
5

VCC_3V3_VD
F143
VCC_1V8

VCC_3V3_VD
2

VDD_1V8_VD

60R
2
1

C245
100N
10V

C467
10N
16V

2
1

C241
100N
10V

C242
100N
10V

2
1

C468
10N
16V

2
1

F144
1

2
1

C246
100N
10V

2
1

C523
100N
10V

2
1

C524
100N
10V

YCBCR[0]
YCBCR[1]
YCBCR[2]
YCBCR[3]

VDA_1V8_VD

60R

F145
VCC_3V3

VCC_3V3_VD

60R
2
1

C247
100N
10V

PROJECT NAME :

SCH NAME :

VIDEO

DRAWN BY :

UTKU GKKAYA

17MB30-1
SHEET:

A3
9

OF:

11

5-17-2007_9:22

AXM

MAIN_GND
22K
R802

C437

2
1

C435
1u
16V

1u
16V
16V
10u
2

C584
220n
16V

D158

VCC_3V3
SDA

R481
22K

SCL

S317

S318

S319

S325

S322
S324
1

8
7
6
5

F212
2

60R
D161
VCC_24V

C255

Q148
BC848B

100n
50V
1

F193

R601
39K

R322
100R

22u
16V
S323
1

R386
47K

Q168
BC807

C436
22u
35V

2
1

C349
100n
50V

2
1

SK24

220n
16V

2
1

C666
1n
50V

R368
20R

R263
4K7

2
1

MAIN_GND

R264
4K7

24V_VPA
1

C475
220U
40V

2
1

C659
100n
50V

2
1

470N
16V

C476
220U
40V

R124
1M
C490

C315

2
1

C439
330P
50V

2
1

C353
100n
50V

2
2
1

C445
330n
50V

C316
1000U
35V

2
1

C663
1n
50V

15N
50V

C357
100n
50V

C356
100n
50V

C665
1n
50V

L110
2
1

C656
100n
50V

2
1

C346
470P
50V

2
1

22u
2
1

C355
100n
50V

1
2
1

C446
330n
50V

C317
1000U
35V

CN113
2
1

C664
1n
50V

2
1

470N
16V

C658
100n
50V

CN112

22u

R715
15R

C345
470P
50V

C314

24V_VP

22u

2
3

MAIN_L

L109

L111

60R

C662
1n
50V

15N
50V

F194
CN118

C350
100n
50V

60R

C569

C546
22u
50V

SUBW_OUT

C585
1

C5V1

C620

100n
10V

1
2

R453
10K

2
1

R364
15K

C331
1

470N
16V

R123
1M
C489

R672
1k8

24V_VPA

1u
16V

24V_VP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

24V_VP

R702
1k

R663
12k

SUBW_L

C313

470N
R529 16V
1K 2

24V_VPA

C570

R619
2K2

VSSD/HW4
OSCIO
HVP1
VDDP1
BOOT1
OUT1
VSSP1
STAB1
STAB2
VSSP2
OUT2
BOOT2
VDDP2
HVP2
DREF
VSSD/HW3

R531
1K

MUTE_AMP

C312

R262
4K7

VSSD/HW1
IN1P
IN1N
DIAG
ENGAGE
POWER_UP
CGND
VDDA
VSSA
OSCREF
HVPREF
INREF
TEST
IN2N
IN2P
VSSD/HW2

1u
16V
16V
10u

100n
10V

R106
4k7

C687

OUTA VDD 8
INAN OUTB 7
INAP INBN 6
VSS
INBP 5

R671
1k8

C433
1u
16V

R691
10k

U125
TDA1308T
1
2
3
4

2
1

PND_MUTE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

S332

U126
TDA8933

R339
20R

C438
330P
50V

AC_INFO

470N
16V

C352
100n
50V

R337
20R

S262

C434

R370
10k

R714
15R

VCC_3V3

MAIN_GND

C351
100n
50V

C311

R261
4K7

D144

S263

MAIN_R

C354
100n
50V

24V_VPA
2

VCC_5V

S264

VCC_12V

1N4148

SUBW_R

R701
1k

C693
1u
16V

10k
R442
C335

C544
1u
16V

Q177
BC848B

600R
F210

VCC_3V3

600R

100n
10V
R693
1
22k

R661
12k

F218

F173
1

C690

600R
2

1u
16V

4
3
2
1

S360

PND_MUTE

C5V6

CN104

Q176
BC848B

C337

R770
100R

R369
10k

FAV_C
1

1u
16V

FAV_Y

5V_ANALOG

600R

F168
10k
R798

2
3

AUD_COM

VCC_12V

SHDN
SDA
PVSS
SCL

C1N
PGND
C1P
VDD

22K
R807

C5V6

MAIN_R

22K
R808

FAV_CVBS
2

C488

R683
47k

PND_SC1

C228

100n
10V
R692
22k

R797
10k

U119
MAX9723

R480
22K
1

R817
33k

R763
220k

C336

STBY_3V3
MAIN_R

C669
220p
50V

C5V6

FAV_AUD_R

5
4

1u
16V

C472
10N
16V

470n
16V

R662
12k

2
1

C559
1

PND_M
R754
10k

SGND
9
INL
10
INR
11
SVSS
12

470n
16V

1u
16V
1

R478
22K

S357

OUTA VDD 8
INAN OUTB 7
INAP INBN 6
VSS
INBP 5

C691

U149 16V
TDA1308T

D120

R200
4k7

C722
1

C474
10N
16V

D121

BBR
OUTR
OUTL
BBL

200R
D122
1

FAV_AUD_L
50V
1n

2
2

R684
47k

1u
C471
16V
10N
16V

1u
16V
22K
R806
22K
R803

F107

C667
220p
50V

R477
22K

100u
16V
C689

R816
33k

R815
33k
1

1u
16V
22K 1
R805
22K 1
R804

8
2

R753
10k

C692

C226

C558

F108

60R

1u
16V

R799
10k

1u
16V
C688

1u
C670
220p
50V
1
2
3
4

R325
100R

PND_M

200R

AUD_OUT1_R

R323
100R

C694

C723

R479
22K
AUD_SW_1

50V
1n

10

F151
1

33k
R818

R800
10k

1
PND_MUTE
Q180
C443
BSN20

100u
16V

13
14
15
16

R356
22K

R820
100k

C473
10N
16V

C668
220p
50V

AUD_OUT3_R

S359

MAIN_L

C110
220P
50V

11

60R

R324
100R

Q179
BSN20

F152
1

C108

600R
C707

R265
4K7

C726
470p
50V

GND 5

12

100u
16V
C430

DMP_AUD_R

AUD_OUT3_L

F211
5V_ANALOG

4 INR+

OUTB 6

C5V6

220p
50V

Q146
Q147
BC848B
BC848B
1

AUD_OUT1_L

1U
16V

OUTA 7

3 INR-

1
1

VP 8

2
2

D133
1

C429

TDA7050T

R366
15K

R530
1K
1

C291

U136

1 INL+
2 INL-

R355
22K

AUD_SW_2

1u
16V

PC_AUD_R

Q149
BC848B

C109
220P
50V

S266

2
2

470p
50V R456
1
10K

R452
10K

AUD_COM

R450
10K

1U
16V

C727

S265

4K7
R267

10u
16V
C432

1U
16V

FAV_AUD_R

R117
12K

S347

C729
470p
50V
3

R321
100R

R365
15K

1
1

100N
10V

C256

1
2
1

R652
100K

2
1

R650
100K

R649
100K
1

C290

AUD_COM

MUTE_AMP
3

C696

R118
12K

R643
100K

R644
100K

R646
100K

Q187
BC848B

2
1

R266
4K7

VCC_5V

1U
16V
C251

SEL_AUD_R

R448
10K

1
1

1U
16V

1U
16V
C250

SEL_AUD_L

DMP_AUD_L

R654
100K

2
1

1U
16V
C254

470p
50V

R651
100K

R648
100K
1
1

VCC
1Y2
1Y1
1Z
1Y0
1Y3
S0
S1

470p
50V
R454
10K
R115
12K
R455
10K
R116
12K

R642
100K

C249

16
15
14
13
12
11
10
9
2

1U
16V
C253

2Y0
2Y2
2Z
2Y3
2Y1
E
VEE
GND

10k
R863
C728

PC_AUD_L

1
2
3
4
5
6
7
8

R645
100K

C252
1

U120
M74HC4052

FAV_AUD_L

R647
100K

470p
50V
R451
10K
R120
12K
R449
10K
R119
12K
C730

2
3

MUTE_AMP
2

R534
1K

10k
R862

60R

C731

S364

1
1

10k
R864

STBY_3V3

S316

IO1_EXT
F153
1

R861
10k

5V_ANALOG

5V_ANALOG

STBY_3V3

R268
4K7

5V_ANALOG

PROJECT NAME :

SCH NAME :

AUDIO

DRAWN BY :

UTKU GKKAYA

17MB30-1
SHEET:

A3
10

OF:

11

5-17-2007_9:23

AXM

4
1

S296

S295

F161
2

PANEL_VCC_ON/OFF

2
1

C607
4n7
50V

Q151
BC848B

1
2

R686
22k

2
1

C581
100n
16V

C577
10u
16V

R336
4k7
D155

Q154
BC848B

C564

C701

1N4148
F213
1

STBY_5V

60R

3 IN

R831
15R

R835
15R

R826
15R

R830
15R

R834
15R

R824
15R

R825
15R

R829
15R

R833
15R

1
1

C646
1u
16V

2
1

C699
100n
16V

5V_ANALOG

60R
1

2
2

PDP_GO/BL_ON_OFF

C709
100u
16V

2
1

C695
1u
16V

2
1

CPU_GO/STBY

C700
100n
16V

R839
22k

CPU_GO/STBY

VCC_33V
VCC_12V_SB

C706
100n
16V

2
1

11

2
1

BA159

C550
1u
16V

Q152
BC848B

2
1

C548
1u
16V

1 FB

3 SW

D159

C613
22u
16V

PVIN 4

C615
22u
16V

C603
100u
16V

F217

STBY_3V3

12V

60R

2
2

STBY_1V2

S326

C610
470u
6V3

2
1

C338
100n
10V

C595
47u
6V3

2
1

C540
1u
16V

2
1

C541
1u
16V

C534
100n
10V

2
1

R688
22k

CPU_GO/STBY

R687
22k

C571
10u
16V

Q156
BC848B2

R696
22k

3.3V
C588
220u
16V

2
1

PLAZMA OPT

U140
LM1117
3 IN

VCC_3V3
STBY_3V3
1

C605
100u
16V

OUT 2
1

R460
10k

R703
2k2

C339
100n
10V

C611
470u
6V3

2
1

VCC_3V3

3 IN

VCC_3V3
1

STBY_5V
2

C606
100u
16V

OUT 2
1

VCC_33V

C340
100n
10V

C612
100u
6V3

S294

F171

R535
18k
2

60R

R332
4k7

10n
16V

10k
R680

C572

F166

GND VOUT

1N4148
D148

L108

VCC_1V8
1

C597
47u
6V3

2
1

C545
1u
16V

2
1

C536
100n
10V

60R
F170
1

22u
2

C616
22u
16V

2
1

C617
22u
16V

STBY_3V3

60R

C592
22u
16V

1N4148

R444
10k

R459
10k

C549
1u
16V

10n
16V

8
7
6
5

SS
EN
COMP
FB

R682
7k5

U141
LM1117

1N4148
D147
2

BS
IN
SW
GND

Q153
BC848B

SS33

R458
10k

VCC_5V

1N4148
D146

PROTECT

C573
1

C560
470u
16V

D157

R461
10k

1
2

U137
MP1593

D145
1

R695
160k

100n
10V

PLAZMA OPT

1
2
3
4

STBY_5V

BC807
Q158

C538
22n
16V

1.5V

R443
10k

GND VOUT

R457
10k

C537
1

C551
1u
16V

R673
150k

60R

F175
1

VCC_3V3

R856
100k

4
1

C552
1u
16V

60R

VCC_12V

F164

OUT 2

GND VOUT

F176

U139
LM1117
3 IN

Q102
FDC642P

VCC_3V3
6

C553
1u
16V

C741
1u
16V

5V
C589
100u
16V

60R

C593
22u
16V

60R
VCC_24V

2
1

60R

F215
2

60R

1
1

F172
1

STBY_3V3

F177
VCC_5V

Q185
BC848B

22k
R858

STBY_3V3

R857
22k

VCC_12V

C725
10u
16V

1
1

D162

C614
22u
16V

Q184
BC848B

VCC_5V

R841
22k

C739
1u
16V

C5V1

VIN 5

FAN2012

22u
2

EN

U138

2 PGND

60R
BA159

C567
220u
6V3

L107

CPU_GO/STBY
1

D160
F174

VCC_2V5

100n
16V

13

F169

R202
4k7

12

60R

C704

C568
220u
6V3

2.5V

R201
4k7

AC_INFO

S123

S270

C587
100u
16V

STBY_3V3

9
10

R679
10k

60R

R694
22k

S293

R203
4k7

C705
100n
16V

F198

S292

60R

R842
22k

VCC_3V3

R713
100k

S275

1
2

C732
100u
16V

S361

S274

VCC_3V3

F216
1

VCC_5V

PROTECT

S273

C740
1u
16V

Q182
FDC642P

S269

VCC_12V

100n
16V

R838
10k

DIM_SEL

60R

VCC_12V_SB

C703

S272

F214

BRT_CNTL

DIG_DIM_PWM

S271

R660
10k

A_DIM_PWM

C724
10u
16V

Q183
BC848B

R764
100R

R823
15R

C649
100u
16V

R840
22k

R814
300R

C708
100u
16V

1
2
2

C702
100n
16V

60R

CN107

5V_TUN
F204

C563
100u
16V

F160
2

OUT 2

R827
15R

R822
15R

STBY_5V

NEAR TO TUNER

GND VOUT

1000u
16V

60R

U150
LM1117

R836
15R

R855
100k

VCC_12V

R832
15R

R828
15R

Q181
FDC642P

C609

60R

R821
15R

STBY_3V3

VCC_5V

12

100n
16V

C742
1u
16V

470u
16V

60R
F159

F201

11

13

VCC_33V

C608
4n7
50V

R837
10k

F158
1

10

C628
3u3
50V

R446
1R

C619
68n
50V

1N4148

R445
47R
C582
33n
50V

1N4148

D156

2
2

33n
50V
C547
820p
50V

C33V

150u

150u

C710
100u
16V

D153

D116

L104
2

100n
16V

2
1

C424

C562
470u
16V

60R

VCC_3V3

F157

C602
100u
16V

60R

L105
2

60R

R107
22R

VCC_3V3
2

F156

C743
1u
16V

R712
100k

F163

R657
10k

100n
16V

60R

Q128
FDC642P

C423

60R

VCC_12V

PANEL_VCC

60R
6

VCC_12V

F154

C561
470u
16V

F162

VCC_5V

60R

C583
F205

60R

F155
1

5V_PANEL

1N4148

5V_PANEL

CN114

D154

17MB30-1

A3

PROJECT NAME :

SCH NAME :

POWER

DRAWN BY :

UTKU GKKAYA

SHEET:

11

OF:

11

5-17-2007_9:24

AXM