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  • Sandesh V Borgaonkar

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    Sandesh V. Borgaonkar has over 10 years of experience in design and verification. He currently works as a Design Engineer at AMD, where he is responsible for SOC level verification of Display Control Engines in GPUs. Previously, he has worked on formal verification projects at Oski Technology, including modules for packet rewriting and port statistics in routers. He holds a B.Tech in Electrical Engineering from IIT Kharagpur and has published papers on formal verification techniques.

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    Sandesh V. Borgaonkar has over 10 years of experience in design and verification. He currently works as a Design Engineer at AMD, where he is responsible for SOC level verification of Display Control Engines in GPUs. Previously, he has worked on formal verification projects at Oski Technology, including modules for packet rewriting and port statistics in routers. He holds a B.Tech in Electrical Engineering from IIT Kharagpur and has published papers on formal verification techniques.

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    89 Ansichten2 Seiten

    Sandesh V Borgaonkar

    Hochgeladen von

    cooldocsv
    Sandesh V. Borgaonkar has over 10 years of experience in design and verification. He currently works as a Design Engineer at AMD, where he is responsible for SOC level verification of Display Control Engines in GPUs. Previously, he has worked on formal verification projects at Oski Technology, including modules for packet rewriting and port statistics in routers. He holds a B.Tech in Electrical Engineering from IIT Kharagpur and has published papers on formal verification techniques.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    Markieren Sie unangemessene Inhalte
    von 2

    SandeshV.

    Borgaonkar
    Cellular:(+91)9582761211 Email:sandy.vb@gmail.com

    Experience

    Sept11PresentDesignEngineerAdvancedMicroDevices(AMD),Hyderabad, India
    SOClevelverificationoftheDisplayControlEngineofAMDsGPUs. VerificationofDCEIPatSOClevelusingOVMMethodology.

    Feb10Aug11 VerificationEngineerOskiTechnology,Gurgaon,India ProjectsDone:


    FormalverificationofPacketRewriteModule(PRM) The routers PRM implements various functions like insertion, removal and update of the packets, and insertion/removal of the header fields of packet descriptors. It consists of 5 submodules: Subcell Reformat FIFO, Flex Extract, FlexStrip,FlexInsertandFlexReplace. EachsubmodulewasverifiedindependentlyusingCadenceIFV. VerificationsetupwasbuiltinSystemVerilog. FormalverificationofPortStatisticsModule(PSM) PSM records and reacts to multiple statistics in real time across all the router paths in a router. All records are stored in dedicated memories. In case of frequentupdates,PSMcombinesmultipleaccessesandmakeasingleupdatein memorywhileallowingCPUtoreadandpossibleresetthestatisticsatrandom times.VerificationofthisblockwasdoneusingCadenceIFV. WorkdoneduringthisprojectwaspresentedinDAC,2011asposterundertitle How Formal Methodology Shrank the Verification Schedule of a Complex StatisticsBlockby6x VerificationsetupwasbuiltinSystemVerilog. FormalverificationofPowermanagementandResetmodule Both the modules were verified using OneSpin 360MV tool and Gap Free Verification(GFV)methodology. Verification involved the construction of conceptual state machine (CSM) referringtothedescriptionofstatemachineinspecificationsalongwithvarious designproperties. The RTLs for this project were written in VHDL. However, the verification infrastructurewasbuiltwithSystemVerilog.

    May09Dec09 ResearchAssistantIITKharagpur,India ProjectsDone:


    Speechrecognitionoverhandhelddevicesinvaryingbackgroundnoises Familiarizedwithstateofthearttechniquesusedforspeakerrecognition.

    Proposedatechniquefortheenhancementofspeechcontaminatedwithbabble noise for improved performance of the existing speaker recognition system. ProposedschemewasimplementedinMATLAB.

    Jul08Oct08 ResearchAssistantPangea3LLC,Mumbai,India
    ProjectsDone: Work involved prior art searches for various electronic technology companies to checkforpossiblepatentinfringements.

    Education

    20042008B.Tech,ElectricalEngineering,2008,IITKharagpur,India
    CGPA : 8.08/10 ProjectsDone: Undergraduateproject:Implementationofcurrentmodecontrolofabuck converter.WonbestundergraduateprojectawardfromDepartmentofElectrical Engineering,IITKharagpur. SummerInternship:DoneatConexantSystems,Pune.ImplementationofReed SolomonencoderinVHDLandC.

    Publications
    HowFormalMethodologyShranktheVerificationScheduleofaComplex StatisticsBlockby6x,DesignandAutomationConference(DAC),SanDiego, 2011

    Skills

    Design Verification FormalVerification Simulation Debugging Script Others

    : : : : : : :

    Verilog,VHDL SystemVerilog,SVA IFV(Cadence),360MV(OneSpin) NCVerilog SimVision,Verdi Shell MATLAB,C

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