Experiment No: 2 Interfacing with 8255A Programmable Peripheral Interface (PPI)

Background 8255A is a general purpose programmable I/O device designed for use with all Intel and most other microprocessors. The functional configuration of the 8255A is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures. The 8255A has 24 I/O pins grouped into 3 Ports of 8 pins each, namely Port A, Port B and Port C respectively. Each of the ports can be configured either as an input port or an output port. Port C is further divided into two four bit ports. The functional configuration of each port is defined by writing a control word in the control register. The control word contains information such as mode, bit set, bit reset, etc., that initializes the functional configuration of the 8255A. 8255A can be programmed in three different modes: Mode 0 (Basic Input/Output):-This functional configuration provides simple input and output operations for each of the three ports. No handshaking is required; data is simply written to or read from a specified port. Mode 1 (Strobe Input/Output):-This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or handshaking signals. In mode 1, Port A and Port B use the lines on Port C to generate or accept these handshaking signals. Mode 2 (Strobe Bidirectional Bus I/O):-This functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O).Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to Mode 1. Single Bit Set/Reset Feature: - Any of the eight bits of Port C can be Set or Reset using a single Output instruction. This feature reduces software requirements in Control-based applications. When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports. Interrupt Control Functions When the 8255A is programmed to operate in Mode 1 or Mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. This function allows the Programmer to disallow or allow a specific I/O device to interrupt the CPU without affecting any other device in the interrupt structure. INTE flip-flop definition: a) BIT-SET => INTE is SET => Interrupt enable b) BIT-RESET => INTE is RESET => Interrupt disable Figures below show Control Word format and Interrupt Control of 8255A

Mode Definition Format

Description of Lab Kit

Microprocessor Kit and 8255 expansion Card The kit available in the lab is based on the processor 8085. It is a versatile microprocessor trainer used as an instructional aid in colleges and universities. It is a complete single board microcomputer used for software and hardware development in research institutions and R&D labs. The board contains the following peripherals which are useful in interfacing lab. 8255: Two 8255 are available to give 48 programmable I/O lines. One of them is located at base address 40H and another is located at base address 00H (nearer to battery socket). Using these two ports, the external devices such as 7 segment displays, ADC, DAC etc. can be interfaced. 8253: Three programmable interval timers - Timer 0 is used for implementing single step facility, Timer 1 is used for generating baud clock and Timer 2 is available to the user. 8251: One 8251 is available in kit for serial communication. It supports all standard bauds rates from 110 to 19200. Bus Expansion: Fully de-multiplexed and buffered TTL compatible bus signals brought out through two 26 pin ribbon cable connectors for expansion. This bus expansion is used to monitor and control the external devices which are interfaced with this kit. 8255 Expansion Kit: Expanded using J3 and J4 connectors of MPS 85-3 microprocessor Kit which is mapped at base address 80H. For lab work we can use 48 I/0 lines, 24-bit I/O lines are connected to 24 LEDs within 8085 microprocessor kit which is mapped at base address of 40H. These set of I/O lines can be used as output lines only. Other 24 bit I/O lines are available in expansion card which is mapped at base address of 80H.These set of I/O lines can be used as input as well output lines. Description of the 8255A Expansion Kit The interface has 4 Dip switches mentioned as SWl, SW2, SW3 and SW4. The 8255A port A and port B can be configured in software as output by using the control word and keeping the switches SW1 and SW3 in O/P position and switches SW2 and SW4 will have no effect. 8255A port A can be configured in software as input by using control word and keeping SW1 in I/P position. After executing the program it reads the status of SW2 position. Similarly port B can be configured as input in software while keeping SW3 in I/P position. After executing the program it reads the status of SW4 position.

 8 RED LEDs are provided to read the status of port A and 8 GREEN LEDs are provided to read the status of port B and YELLOW LEDs are provided to read the signal status mentioned on the interface. Switches S1, S2 and S3 are provided to simulate STB* or ACK* signals in Mode1 and in Mode 2. Provision made for connecting buffered external interrupt (RST 7.5 etc.,) to J5 and keeping the jumper JP2 at PC0 or PC3 depending on the type of Mode. The interface has got 4 connectors named as J2, J3, J4 and P1. J3 and J4 are reserved for MPS85-3 trainer. All the 24 I/O lines are brought out to the J2 connector. But port C lines are used as handshake signals so user cannot use those lines. (Only port A and port B lines are available to user). For MPS 85-3 trainer kits there are two 26 pin J3 and J4 connectors which can be connected to 26 pin J3 and J4 connectors on 8255 study card. Switch off the power to the Trainer while connecting the Study Card. Press Reset after giving power to the Trainer. Before Coming into the lab, your initial report should contain the programs (mnemonics with opcodes) and circuit diagrams (if applicable) of all given problems. Problems: 1. For the 8255 which is within 8085 microprocessor kit (mapped at base address of 40H), initialize Port A in output mode 0, Port B in output mode 0, Port C-Upper in output and Port C-Lower in input mode. a. Display AAH in Port A and 55H in Port B. b. Using BSR mode try to set PC6, PC4, PC2 and PC0 and observe the result. c. Also configure the all bits of Port C in output mode and observe the result by repeating 1b. d. Comment upon the results of 1b and 1c. 2. Initialize the 8255 expansion kit (mapped at base address of 80H) as: - Port A in mode 0 input, Port B in mode 0 output and Port C in output mode (all bits of C-port may not be visible in your lab kit). a. Output 0FFH in all ports .Note down the result and comment on it. b. There are only five LEDs connected to five pins of Port C. Find out the missing bits of Port C. 3. For the following cases write down the appropriate program and note down the result a. Read data from Port A of expansion kit and display the data to Port A of microprocessor board. b. Read data from Port B of expansion kit and display it to Port A of same kit. c. Read data from Port A and Port B of expansion kit and display the sum to Port A and carry to Port C of microprocessor board. d. Read data from Port C-lower of expansion kit and display it to Port C-upper of same expansion kit as well as microprocessor board.

4. The following program initializes 8255A Port A as Input in Mode 1 and Port B as an Output in Mode 0. Read through Port A and Output to Port B as well as data field of the trainer display. Press S2 switch to simulate STBA* signal. Note: Put the jumper at PC3 to connect external interrupt from pin3 of J3 (i.e. RST6.5) to J5 of interface. 8000 MVI A, B0 OUT 83 MVI A, 09 OUT 83 MVI A, 0D SIM EI JMP 800C JMP 9000 IN 80 OUT 81 MVI B, 00 STA 8FF1 CALL 044C JMP 9000 ; Initialize 8255A Port A as Mode 1 i/p & Port B as Mode 0 o/p ; Set INTEA (Bit Set Control word of PC4) ; Enable RST 6.5 ;Set Interrupt Mask ;Enable Interrupts ;Wait for interrupt ; ISR of RST 6.5 should start from 8FB9 ; Read through Port A and display in Port B ;Display the content of accumulator on data field of the trainer ; display

800C 8FB9 9000

900C

Note: For RST 5.5, the connection of Jumper is similar as in case of RST 6.5 but ISR of RST 5.5 should begin from 8BF3 and 0E should be used as interrupt mask instead of 0D. Run the above program, observe the result and comment upon it. Also write down the pins of Port C used for the handshaking with their appropriate functions. 5. Initialize 8255A Port B as Input in Mode 1 and Port A as an Output in Mode 0. Read through Port B and Output to Port A. Use S1 switch to simulate STBA* signal and put the jumper at PC0 to connect external interrupt from pin3 of J3 to J5 of interface. Comment on output. Also write down the pins of Port C used for the handshaking with their appropriate functions.