Week 10

Procedure and Interrupts

Electrical and Computer Engineering

EE3612 Microprocessor Systems Instructor: Li Bai, PhD

Week 6 Slide 1

Stack Pointers and Subroutines

POP
Bottom of stack SS:FFFEh SS:FFFDh

SS

Top of Stack

SS:SP

SP

PUSH
End of Stack

SS:0001h SS:0000h

Electrical and Computer Engineering

EE3612 Microprocessor Systems Instructor: Li Bai, PhD

Week 8 Slide 2

Calling procedures and using the stack

call proc_name
Pushes the instruction pointer (IP) Pushes CS to the stack if the call is to a procedure outside the code segment Unconditional jump to the label proc_name

ret
Pop saved IP and if necessary the saved CS and restores their values in the registers
Electrical and Computer Engineering EE3612 Microprocessor Systems Instructor: Li Bai, PhD Week 8 Slide 3

Procedure example
STACK_SEG SEGMENT STACK 'STACK' DB 64 DUP(?) STACK_SEG ENDS MATLAB DATA_SEG SEGMENT TOTAL DW 1234H DATA_SEG ENDS CODE_SEG SEGMENT EX612 'CODE' BL=12H SQUARE(BL) function y=SQUARE(x) y=x*x;

PROC FAR ASSUME CS:CODE_SEG, SS:STACK_SEG, DS:DATA_SEG PUSH DS MOV AX, 0 PUSH AX MOV AX, DATA_SEG MOV DS, AX

MOV BL, 12H CALL SQUARE RET EX612 ENDP SQUARE PROC NEAR PUSH AX MOV AL, BL IMUL BL MOV BX, AX POP AX RET SQUARE ENDP CODE_SEG ENDS

Electrical and Computer Engineering

EE3612 Microprocessor Systems Instructor: Li Bai, PhD

Week 8 Slide 4

Direct access to the stack

PUSH/POP/CALL/RET modify the SP When you need to access variables in the stack you need to manipulate the BP
Example: access the third word from the top of stack p p and return result in AX PUSH BP ; Can you tell why ? MOV BP SP BP, ADD BP, 4 MOV AX, [BP]

When you need to allocate/deallocate memory in the stack you manipulate directly the SP
Electrical and Computer Engineering EE3612 Microprocessor Systems Instructor: Li Bai, PhD Week 8 Slide 5

Procedures at a glance g
Procedures can access global variables declared at the beginning of the program Procedures can access global variables stored in registers Procedures may have parameters passed to them
Registers with global variables is a form of parameter passing Pushing parameters to the stack is another form of parameter passing i

Procedures may need to preserve registers Procedures may return results to the caller in registers or write results in memory

Electrical and Computer Engineering

EE3612 Microprocessor Systems Instructor: Li Bai, PhD

Week 8 Slide 6

Guidelines for MP1

There should be a one-to-one match between push and pop The first pop is matched with the last push y p Some of the functions you need to implement return values to memory and some return values in registers
PlayerStats [player1], [player2],[player3] NewPlay, bx=1,2, or 3 of 3 player created

D not push and pop registers th t will store Do t h d i t that ill t return values
Electrical and Computer Engineering EE3612 Microprocessor Systems Instructor: Li Bai, PhD Week 8 Slide 7

Macros
Procedures have some extra overhead to execute (call/ret statements, push/pop IP, CS and data from the stack) A macro is a piece of code which is macroexpanded whenever the name of the macro is encountered Note the difference, a procedure is called, while a macro is just , p , j expanded/inlined in your program Macros are faster than procedures (no call instructions, stack management etc.) g ) But they might
Significantly increase code size Hard to debug

Electrical and Computer Engineering

EE3612 Microprocessor Systems Instructor: Li Bai, PhD

Week 8 Slide 8

Position MACRO Row, Column PUSH AX PUSH BX PUSH DX MOV AH, 02H AH MOV DH, Row MOV DL, Column MOV BH, 0 INT 10H POP DX POP BX POP AX ENDM

Position 8, 6

Electrical and Computer Engineering

EE3612 Microprocessor Systems Instructor: Li Bai, PhD

Week 8 Slide 9

Organizing your program

Create a block diagram or pseudocode of your program in paper g
Control flow Data flow

Break the program into logical components that can be easily translated to procedures in your code d Use descriptive names for variables
N Noun_type f types t for t Nouns for variables Verbs for procedures
Electrical and Computer Engineering EE3612 Microprocessor Systems Instructor: Li Bai, PhD Week 8 Slide 10

Organizing your program

Modular program organization helps debugging
M k it easier t i l t th b i a single Makes i to isolate the bug in i l procedure

All (Microsoft) programs contain bugs!

This is overstated It really means that you shouldnt expect y y y p your program to work the first time you run it but you shouldnt feel bad about it either, relax and trace the bug t th b

Tracing bugs
The debugging process:
Set breakpoints in your programs and use them as checkpoints for checking the contents of registers/memory Comment out code, this might help you find out whether the commented out code contains the bug

Use print statements (and you might not need the debugger!)
Display the values of critical data Display the status of the program

Tracing bugs
Force registers and variables to test the output of the procedure
Helps you debug the procedure using as many inputs as possible

If everything else fails

Test your logic Ch Change your algorithms l ith

Procedures
Labeled sections of code that you can jump to or return from any point in your program A procedure in your assembler is merely a non-dotted non dotted label Use dotted labels if you want to set jump points within a procedure (l i t ithi d (local l b l ) l labels)

Example of program structuring

;====== Procedures =========================================== KbdHandler <Your code here> MouseHandler <Your code here> DisplayResult <Your code here> ;====== Program Initialization =============================== .start: mov ax, cs ; Use common code & data segment mov ds, ax mov sp, stacktop ; Initialize top of stack

Map of the First Megabyte of PC Memory.

FFFFF F0000 C0000 B8000 B0000 A0000 9FFFF (end of address space) ROM BIOS Reserved Color Text Buffer MDA Text Buffer Video Graphics Buffer Transient Part of COMMAND.COM

(Available RAM for Transient Programs)

640K RAM Resident part of COMMAND.COM DOS Kernel, Device Drivers, etc. Software BIOS 00400 00000 DOS Data Area Interrupt Vector Table

Map of the BIOS p Data Area.

Offset (Segment 0400) 0000 - 0007 0008 000F 0010 - 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 003D 003E 0048 0049 004A 004B 004C 004D 004E 004F 0050 005F 0060 0061 0062 0063 - 0064 0065 0066 0067 006B 006C 0070

Description Port addresses, COM1 COM4 Port addresses, LPT1 LPT4 Installed hardware list Initialization flag Memory size, in Kbytes Memory in I/O channel Keyboard status flags Alternate key entry storage Keyboard buffer p y pointer (head) ( ) Keyboard buffer pointer (tail) Keyboard typeahead buffer Diskette data area Current video mode Number of screen columns Regen buffer length, in bytes Regen buffer starting offset Cursor positions, video pages 1 - 8 Cursor end line Cursor start line Currently displayed video page number Active display base address CRT mode register (MDA, CGA) Register for CGA Cassette data area Timer data area

Interrupts
Provide a mechanism for immediate changing of the program environment. Transfers program control to what is called an interrupt-service routine. 8088 & 8086 can i l implement any of 256 t f different types of interrupts.

Electrical and Computer Engineering

EE235 Microprocessor Systems Instructor: Frank P. Higgins, PhD

Week 15 Slide 18

Interrupts
Main program Instruction N Instruction N + 1
When the interrupt p service routine is finished, a return from interrupt instruction will return program p g control to instruction N + 1 of the main program. Interrupt X occurs during p g the execution of instruction N in the main program. Before going to instruction B f i t i t ti N+1, program control is passed to the first instruction for interrupt X.

First instruction Interrupt service routine for Interrupt X Interr pt X. Return from Int.

Interrupts
How does it know where to go, i.e., where this g , , interrupt service routine is located?
an Interrupt Vector Table

There are 256 interrupt vectors that correspond to the 256 interrupt types. The vector table is located in memory starting at address 0 Each vector is 4 bytes (2 words) in length and contains the CS and IP values of its respective interrupt service routine.

Interrupt Vector Table

3FE 3FC CS 255 IP 255 Vector 25510 82 80 7E 7C CS 32 IP 32 CS 31 IP 31

User Available
Vector 3210 Vector 3110

Reserved
16 14 12 10 0E 0C 0A 08 06 04 02 00 CS 5 IP 5 CS 4 IP 4 CS 3 IP 3 CS 2 IP 2 CS 1 IP 1 CS Value Vector 0 (CS 0) IP Value Vector 0 (IP 0) Vector 5 Vector 4 Overflow Vector 3 Breakpoint Vector V t 2 NMI Vector 1 Single-Step Vector 0 Divide Error

Interrupts
Divided into 5 groups (in order of priority)
Reset (highest priority) Internal interrupts and exceptions Software interrupts Non maskable interrupt Non-maskable External hardware interrupts (lowest priority)

The above is the first level of priority

Interrupt Priority
Hardware, software and internal interrupts are serviced on a priority basis. The second level of priority is based on the type number:
0 highest p g priority y 255 lowest priority

If an interrupt service routine is running, p g, only devices with a higher priority are allowed to interrupt this service routine.

Interrupt Priority (cont.) (cont )

Hardware interrupts this priority scheme is implemented in the external hardware. Examples:
high priority power failure routine medium priority k b d routine (t k di i it keyboard ti (to keep buffer flushed) l low priority di k controllers i it disk t ll

Review: Status Register (SR)

Control bits:
Trap Flag (TF): used by debugging programs; if set goes into a single step mode of operation; if cleared, normal operation Interrupt Flag (IF): if set, the external interrupt signal is watched and processed; if cleared the interrupt cleared, signal is ignored Direction Flag (DF): determines the direction of string operations; if set, the string instruction decrements the address; if cleared, it increments the address

Interrupt Flag
Affects only external hardware interrupts interrupts. Does not and can not mask out the other 4 interrupt groups:
software interrupts non-maskable i t k bl interrupt t internal interrupt reset

Review: Status Register Format

15 14 13 12 11 10 9 8 7 6 5 4 AF 3 2 PF 1 0 CF

OF DF IF TF SF ZF

Intel Reserved

Review: Flag-Control Instructions Flag Control

7 instructions (have no operands):
clc clear carry flag stc set carry flag cmc complement carry flag (toggle) cli clear interrupt flag li sti set interrupt flag cld clear di ti fl ld l direction flag std set direction flag

Software Interrupt Instruction

Syntax: int n Operation:
1. 1 The following are pushed on the stack:
a) Flags, i.e., Status Register b) CS c) IP of next instruction

2. IF & TF are cleared in the Status Register 3. New CS & IP are loaded from Vector Table location defined by n. (This results in an unconditional jump to CS:IP)

Return from Interrupt Instruction

Syntax: iret Operation the following are popped from the stack:
a) IP b) CS c) Flags, i.e., Status Register

This results in the program continuing with the next instruction that would have occurred without an interrupt.

Interrupt Service Interrupt-Service Routine Structure

isr_name proc ; this starts like a subroutine push ax ; save all the registers push bx ; that you will be using ... pop b bx pop ax iret isr_name endp ; and recall them when d ll h h ; you are done ; but use return from ; interrupt rather than ret ; end of isr procedure

Interrupts:
Hardware interrupt: in response to a request by a hardware device that needs attention. Hardware interrupts occur at "unexpected" times. Software interrupt: A call to DOS or BIOS in response to a interrupt instruction (INT) in the program being processed processed. Exception: An automatically generated trap in response to an exceptional condition such as division by zero.
32

Hardware Interrupts
Device Program
0 4 1 1

Interrupt table
3

Interrupt Code

2 5
7

Stack
33

Hardware Interrupt Steps

0. The program is executing in the CPU 1. The hardware device needs attention q p and requests an interrupt. 2. The CPU finishes processing the current instruction. It the saves its "state" instruction state (flags and CS:IP) on the stack. 3 The address of the interrupt handler is 3. obtained from the Interrupt Vector Table (located in the first 400h bytes of memory) memory).
34

Hardware Interrupt Steps

4 The CPU loads the address of the 4. interrupt handler into the IP. 5 The interrupt handler code is 5. processed. 6 When the i t 6. Wh th interrupt handler i fi i h d t h dl is finished, the CPU pops the "state" (CS:IP and Flags) b k f Fl ) back from th stack. the t k 7. Execution of original program continues beginning at the next instruction. 35

Hardware Interrupt Comments

Some interrupt operations are so critical that the interrupt driver may disable other interrupts until the critical operation is completed. In IBM terminology, hardware interrupts are known as an IRQ Each device is assigned a IRQ. number which determines the Interrupt Vector entry of the appropriate interrupt handler.

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Software Interrupt
Software interrupt. Software interrupts are something like a S ft i t t thi lik procedure call except the name of the procedure is not known to the caller caller. Works much the same way as hardware interrupts but steps 1 and 2 are replaced by an INT xx instruction in the code. The number xx determines the table entry specifying location of the interrupt handler desired. d i d
37

Software Interrupt
In many respects interrupts are like procedure calls. Difference - In procedures, the address of the procedure i specified i th program. I i t d is ifi d in the In interrupts, t the address is specified in the interrupt vector table. In IBM design, the interrupt vector table is stored in design the lowest 1K of memory. Each entry is a 4 byte segment/offset address (That allows 100h = 256d address. entries.)
38

Interrupt Table
Stored in bytes numbered 0-1023 0 1023 256 four byte entries E t i are th segment/offset address of Entries the t/ ff t dd f the interrupt handler (the code used to process th t interrupt) that i t t)

39

Interrupts
0 , 2, 4, 6, 7 Processor and memory errors 1, 1 3 used by debuggers 5 print screen 8-0Fh Hardware interrupts ( p (IRQ0 IRQ7) ) 10h-20h Various BIOS interrupts 20h 33h, 3F-7F MS-DOS 34-3E Floating point emulation 80-F0 Reserved for ROM BASIC F1-FF F1 FF A il bl f application programs Available for li ti

40

Common Software Interrupts

INT INT INT INT INT INT 10h 16h 17h 1Ah 1Ch 21h Video services Keyboard services Printer services Time of day User Timer Interrupt DOS services - "DOS function calls"

Most interrupts have multiple functions and use AH to specify the desired operation (function)
41

I/O Model
Programs

Languages

DOS operating system

Normally restricted in multitasking machines

BIOS

Hardware
42

I/O Model
DOS: Redirectable slow device Redirectable, slow, independent, easiest to use, treats I/O in a g generic fashion BIOS: Not redirectable, faster, device independent, provides much more control, understands video output Hardware: Not redirectable, fastest device redirectable fastest, dependent, hardest to use. Inappropriate use p can cause serious problems.
43

.code code main PROC ; set up data segment g mov ax, @data mov ds, ax ; print the string "Hello" Hello mov dx, OFFSET outBuffer Uses function 9h of interrupt mov ah, 9h 21h int 21h ; terminate exit mov ax, 4C00h C int 21h main ENDP 44 END main

Simple 16 bit program (con t) (cont)

MS-DOS Function Calls (int 21H)

Function 09h: F nction 09h String o tp t output

prints "$" terminated string DX holds offset of string to be printed
aString BYTE "String", 0Dh, 0Ah, "$" ... mov dx, OFFSET aString mov ah, 09h int 21h

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Hardware Interrupts
Minimum-mode 8086 Minimum mode
ALE M/IO* /O RD* WR* 8086 MPU AD0-AD15 AD INTR INTA INTA* DT/R* DEN* External Hardware H d Interrupt Circuitry INT32 INT33 INT34 INT35

INT255

Hardware Interrupts
The microprocessor samples the INTR input signal during the last T state of each y instruction cycle. The INTRs active level (1) must be held y p until tested by the microprocessor. It must be removed before returning from p its Interrupt Service Routine, otherwise the same interrupt may get processed a second time.

Hardware Interrupts (cont.) (cont )

Before all of this happens, the IF flag (status pp , g( register) must be set to 1 for the microprocessor to respond to the interrupt. Th microprocessor acknowledges the i The i k l d h interrupt with a double INTA pulse as shown in the following timing diagrams diagrams. From the data vector placed on the bus, the microprocessor goes to the appropriate interrupt service routine defined in the Interrupt Vector Table.

Hardware Interrupts Minimum Mode

T1 CLK ALE AD7-AD0 AD7 AD0 INTA* DEN* DT/R DT/R* T2 T3 T4

1st ALE Cycle

Note: RD*, WR* = 1; BHE* = 0 RD*

Hardware Interrupts Minimum Mode

T1 CLK ALE AD7-AD0 AD7 AD0 INTA* DEN* DT/R DT/R* Interrupting Device Supplies Data Note: RD*, WR* = 1; BHE* = 0 RD* T2 T3 T4

2nd ALE Cycle

Vector no. = 0-255 no 0 255

NMI Non-Maskable Interrupt Non Maskable

A transition from 0 to 1 on the NMI pin signals the non-maskable interrupt p procedure. The signal must remain high for 2 clock y cycles. The Interrupt Vector is 2. This is non-maskable and as such is used non maskable for handling things such as power loss or y ( p y ) memory failure (i.e., parity error).

RESET Initializing the Microprocessor Mi

The RESET pin must be held at logic 1 for a minimum of 4 clock cycles. The microprocessor sets its signals to either the high impedance or inactive states (see textbook or manual for details) details). When the RESET pin transitions to 0, the microprocessor starts with CS=0xFFFF i t t ith CS 0 FFFF and IP=0x0000.

Initializing the Microprocessor (cont.)

Therefore program execution starts at Therefore, 0xFFFF0. This location contains code that initializes the microcomputers system resources, known as a boot strap program boot-strap program. This is typically stored in a ROM which is unmapped f d from the memory space when th h initialization is complete.

Basic Features
8086 announced in 1978; 8086 is a 16 bit microprocessor with a 16 bit data bus p 8088 announced in 1979; 8088 is a 16 bit microprocessor with an 8 bit data bus Both manufactured using High-performance Metal Oxide Semiconductor (HMOS) technology Both contain about 29000 transistors Both are packaged in 40 pin dual-in-line package (DIP)

8086/8088 Pinout Diagrams

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8086

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8088

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET

BHE has no meaning on the 8088 and has been eliminated

Multiplex of Data and Address Lines in 8088

Address lines A0 A7 A0-A7 and Data lines D0-D7 p are multiplexed in 8088. These lines are labeled as AD0-AD7.
By multiplexed we mean that the same pysical pin carries an address bit at one time and the data bit another time
GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET

8088

Multiplex of Data and Address Lines in 8086

Address lines A0-A15 and Data lines D0-D15 are multiplexed in 8086 These lines are 8086. labelled as AD0-AD15.
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

8086

Minimum-mode and Maximummode Systems

8088 and 8086 microprocessors can be configured to work in either of the two modes: the minimum mode and the maximum mode Minimum mode:
Pull MN/MX to logic 1 Typically smaller systems and contains a single microprocessor Cheaper since all control signals for memory and I/O are generated by the p microprocessor.
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

8086

Maximum mode
Pull MN/MX logic 0 Larger systems with more than one processor (designed to be used when a coprocessor (8087) exists in the system)

Lost Signals in Max Mode

Minimum-mode and Maximummode Signals

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET

8086

Vcc

8086

GND

Min Mode

Max Mode

8086 System Minimum mode

PCLK

+5V RES
Clock generator
AEN2 AEN1 F/C

CLK READY RESET

M/IO INTA RD WR MN/MX +5V

Control Bus

Wait-State Generator

ALE

STB OE

A0 - A19 Address Bus

8086 CPU C

AD0-AD15 A16-A19 BHE

8282 Latch

BHE

D0 - D15 8286 DT/R DEN T OE 16

8086 System Maximum Mode

+5V
CLK Clock generator MN/MX S0 S1 S2 Gnd S0 S1 S2 CLK MRDC MWTC AMWC IORC IOWC AIOWC INTA

RESET DEN DT/R

Wait-State Generator

ALE

8086 CPU C

STB OE

8288 Bus Controlle er A0 - A19 Address Bus BHE

RES

READY

AD0-AD15 A16-A19

8282 Latch

T OE
8286 Transceiver

DATA

Description of the Pins

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8086

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

Vcc

GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8086

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET

GND

Min Mode

Max Mode

RESET Operation results

CPU component Contents Flags Instruction Pointer CS DS, DS SS and ES Queue Cleared 0000H FFFFH 0000H Empty

AD0 - AD15: Address Data Bus

Data AD0 AD15 Address

A17/S4, A16/S3 Address/Status

A17/S4 A16/S3

Function
Extra segment access Stack segment access Code segment access Data segment access

0 0 1 1

0 1 0 1

A19/S6, A18/S5 Address/Status

A18/S5: The status of the
interrupt enable fl bit i updated i t t bl flag is d t d at the beginning of each cycle. The status of the flag is indicated through thi pin fl i i di t d th h this i

A19/S6: When Low, it indicates that 8086 is in

control of the bus. During a "Hold acknowledge" g g clock period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus.

S0, S1 and S2 Signals

S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Characteristics Interrupt acknowledge Read I/O port Write I/O port Halt Code access Read R d memory Write memory Passive State