THE TECHNOLOGICAL FRAMEWORK the word technology when used in connection with computer design refers to the e lectronic,

physicochemical, or mechanical means for the physical implementation of processor and other components. the wor d is used to denote the entire range of implementation techniques as well as to specific methods, in the latter case, one may legitimat ely speak of different technologies. The relationship of computer architecture to technology is somewhat analogous to that of say, structural engineering to structural and building materials. it is absolutely imperative for the structural engineer to be fully cognizant of the strengthsa nd limitations of materialss o that the structuresh e or she realizable. conversely, knowledge of some particular properties of materials so that the structures he or she design are be exploited by the engineer and brought to bear in a particular structural desi gn. This knowledge used by the engineer is highly selective: metals, alloys,concrete , wood, and other materials have many different kinds of characteristics, only a few of which are of interest to the structural engineer, notably their mechani cal properties and the factors that affect these properties. the (building) architec t, in contrast, may be interested in very different kinds of properties their textures. for example,or how they symbolize some aesthetic or functional aspect of the bui lding as a whole. We make these preliminary observations to emphasize t at in discussing the technological framework of computer architecture one is (once a gain) posed apro blem of abstraction: Among the many features and characteristics of the various available technologies,which are the ones relevant to the computerarchit ect and why? And in what fashion can such technological knowledge influence architectural des ign or styles. influence architectural designs or styles? The aim of this chapter,then, is to discuss those a spects of the technologies of processors( logic technology) and memory systems( memory or storage technolog y) that are relevant to computer architecture. 2.2 LEVELS OF INTEGRATION Certainly the dominating evolutionary theme in both logic and memory technology has been the remarkable increase in the number of logic gates or components per integrated circuit (IC) chip sinc e about 1950 when the first discrete transitrors were used in digital computers. this growth in circuit density has b een succiently described in terms of what has come to be known as Moore's Law. this law in its original form states simply that the number of components per ci rcuit doubles every year. This trend was first predicted in 1964 by Gordon E. Moore and, as Figure 2.1 ind icates, the growth for the period 1959-1975 followed this prediction. this rate of growth, however,has tended to decelerate from the mid 1970s onward.

Moore (1979) himself noted this and suggested that the component countwould doub le every 2 years rather than every year. This is shown in Figure 2.1 by the slight flattening of the curve from about 197 5 onward. It is further obvious that even this growth rate cannot continue indefinitely, s ince there are physical imitations to the size of circuits. technological basis for this growth in the density of IC chips is essentially tw o fold,reduction in feature size and increase in chip area. the future size is the width of the smallest dimension to be fabricated in silic on and determines the size of the transistors and width of the wires.Feature size has d ropped from about 37 microns in 1960 to'2 microns in 1984,although Burger and colleague s (1984) have pointed out that laboratory devices with 0.3-micron feature size h ave been developed. Similarly, over the past two decades, chip size (chip area) has increased by an order of magnitude-from about 4 mm in 1965 to 40 mm in l992 (Burgeral., 1984). For many years now, it has become customary to partition ICs among the following classes according to the extent of integration: Small-scale integration( SSI). Medium-scale integration (MSI). Iarge-scale integration (LSI). Very-large-scalein tegration (VLSI). To these,a fifth class,ultra large scale integration (ULSI), has sometimes been added. Unfortunately,there is considerable discrepancy among different authorities as t o the range of circuit densities for each of these classes, as Table 2.1 shows. The matter is further confused in that the scale of integration is sometimes qu antified according to the number of gates (the first and second column table 2.l ), the number of devices (transistors, resistors, etc.), or the number of component s (without further explanation, see the third column of Table 2.1 per chip. In general, the device count per chip can be obtained from the gate count by mul tiplying the latter by from 3 to 5 (Muroga, 1982). Rather than relying too much on the numbers, you can better appreciate these scales of integration by considering the functional power( or "functionality") o f the circuits when viewed as building blocks in digital systems and computer design.Table 2.2 lists examples from each of the classes of ICs. Again, because the boundaries are somewhat fuzzy, you may disagree about the placement of some of the circuits in one class rather than another. 2.3 TECHNOLOGIES AND THEIR CHARACTERISTICS the properties of IC chips are intimately connected to the technology used to fa bricates the chips. ICs are basically built from conducting material deposited on a substrate (usual ly) of silicon. the different technologies arise because of the diferent kinds of materials that may be used to form the layers and the different methods used to deposit them. The actual details of materials and fabrication underlying these technologies ar

e beyond the scope of this book; however,the bibliographic section at the end of this chapter discusses several references for further reading. our perspective and understanding of technologies will, instead, be based on a f ew key features that are of immediate interest to the computer architect. We will therefore attempt to provide a characteristic "profile" of each of the m ore well known technologies, with minimal reference to the internal physical cau ses underlying these profiles. the most widely used ICs fall into two main categories according to the transist or type. The first uses the pnp or npn junction transistor, which are commonly known as bipolar transistors since charge carriers of both po larities electrons and holes that are, respectively,the negative and positive charge carr iers) are involved. The second categoryis based on the unipolar of field effect transistor (FET) inv olving a single charge carrier. These are more commonly referred to as metal-oxide semiconductor (MOS) devices b ecause of the used in their fabrication. Bipolar devices can be from one of several technology or logic families. of these, the most widely used are the transistor-transistor logic (TTL) and emi ttercoupled logic (ECL) technologies. A third, more recently developed bipolar family is integrated-injection logic (i 2L). Several other bipolar technologies that we will not be considering here have als o been developed. MOS devices fall principally into three classes, called p-channel MOS (PMOS),n-channel MOS (NMOS), and complementary MOS (CMOS) depending, respectivel y, on whether the charge carriers are positive (holes) or negative (electrons) or w hether the devices include both types of transistor. PMOS technology, although used in the past, has been largely replaced by the fas ter NMOS technology and will not be further discussed here. We will consider,rather,a high-performance version of NMOS, called HMOS. The properties that are most likely to be of interest to the architect are summarized in Table2 .3 for the three principal bipolar technologies (TTL,ECL and IL) and the three most significant MOS technologies(NMOS, HMOS and CMOS). It is important to note that the values of the different parameters are "typical" and there are higher and lower performance versions of each of the te chnology families that yield different values for these parameters. furthermore, whenever there is a sharp discrepancyin values given by different a uthorities for a given parameter,these variants are listed. The sources for all the data are cited at the bottom of Table 2.3. Based on the data of Table 2.3 and other considerations, the following, very gen eral, statements can be made. l. The most attractive characteristics of NMOS and HMOS devices are their high packing density and low power consumption (relative to bipolar devices). Compared to NMOS, HMOS yields even better density and power consumption characte ristics. because of these basic properties, MOS technology has been traditionally used fo r semiconductor memories and most microprocessors. NMOS was used in the 8-bit microprocessors whereas HMOS has been employed in bot h l6-bit and 32-bit microprosessor. the low speed (high gate propagation delay) characteristics of NMOS have also be en circumvented in HMOS technology.

2. CMOS technologyg ivess till lower power consumption.It has other advantages not shown in Table 2.3. namely, a wider operating range with respect to power supply voltage and operating temperatures. As Table 2.3 shows, the speed of CMOS devices and the achievable density of chips are low compared to NMOS and HMOS logic. However, these problems are being resolved by continuous improvements in CMOS technology . 3. ECL is the fastest of the currently prevalent commercial technologies, althought his speed is accompanied by high power consumption and low chip densit y. ECL technology is mostly used to achieve small scale integration building blocks and also gate arrays and, because of its speed characteristic is employed in high perfomance processor. some bit slices are also based on ECL technology. 4. because of its overall set of characteristics, TTL is the most widely used technology for a large variety of medium-range processors and bit-slice componen ts. It provides the basic technology for medium-scale integration. IL is a much more recent bipolar technology, the most attractive features of which are low power consumption and relatively high density. Thus, it is used for the low to medium end of large-scale integration. 5. the delay power product of a gate defined as (delay time) X (power dissipatio n) and measured in picojoules( pj) is a metric that is used to denote the amount of energy required to change the state of a device. It is used to compare different logic technologies as well as variants within a given technology. Generally speaking, the smaller the delay power product, the better is technolog y. However the delay power product is usually measured under the best conditions( usinga ring counter consisting of a ring oflogic gates where each gate has only one fan out connection).It turns out that when networks are constructed with gates having relativley large fanouts a lower power-based the technology such as MOS shows a much greater delay power product. Thus, the latter as normally measured does not properly reflect the influence of the number of fan out connections. because of this, the delay power product is considered a reasonable but not very precise metric f or comparing technology.