8051 I/O and 8051 Interrupts

Class 7 EE4380 Fall 2002

Pari vallal Kannan

Center for Integrated Circuits and Systems University of Texas at Dallas

Agenda
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8051 I/O Interfacing

Scanned LED displays LCD displays Keypads IVT, ISR Interrupt enable and priority External interrupts

8051 Interrupts

19-Sep-02

Scanned 7-seg LED display

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LED displays are

power-hungry (10ma per LED) Pin-hungry (8 pins per 7seg display)

D3

Vcc

Scanned displays

D2

D1

D0

Only one 7-seg display is enabled at a given time Inputs a-h are connected together respectively 8 + # of digits 8 + 4 for this figure

Total Port pins needed

19-Sep-02

Scanned 7-seg display

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Algorithm to display a 4 digit value. The scanning frequency should be high enough to be flicker-free

start: again:

disable [D3:D0] enable D3

[a:h] pattern for Digit3 delay disable D3. Enable D2 [a:h] pattern for Digit2 delay disable D2. Enable D1 [a:h] pattern for Digit1 delay disable D1. Enable D0 [a:h] pattern for Digit0 delay disable D0 Goto again

At least 30HZ Time one digit is ON

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1/30 seconds

Higher values give better flicker reduction (60Hz)

19-Sep-02

Keypad Interfacing
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16 Keys arranged as 4x4 Algorithm:

Vcc

Drive a 0 on a row Read all the columns If any key had been pressed, its column will be 0, else 1 Keep repeating in a loop for each successive row Switch 4 is pressed
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R1

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

R1

R2 R3 R4

8051

R2

C1 C2 C3

Example:

C4

R3

R1 0, C1:C4 = 1111 R2 0, C1:C4 = 0111 R1 0, C1:C4 = 1101

R4 C4

Switch 2 is pressed
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C1

C2

C3

19-Sep-02

LCD Interfacing
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LCDs are cheap and easy way to get text display for an embedded system

Various configurations (1x20 to 8x80), starting from $5 Graphics LCDs are also available

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Intelligent LCDs have internal ASCII decoders, Character Generators and LCD control circuitry Some also have custom character generation capacity

User defined character RAM Program this RAM with the character pattern Then use it like ordinary ASCII characters Usually MSB decides between std ASCII and custom characters

19-Sep-02

Alphanumeric LCD Interfacing

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Pinout

8 data pins D7:D0 RS: Data or Command Select RW: Read or Write E: Enable (Latch data) Vee : contrast control
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Vcc P1.0 D0

LCD
Vee P1.7 D7 RS P3.3 P3.5 RW E

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RS=0 Command,

RS=1 Data RW=1 Read

RW=0 Write

E=1Enable (H-L pulse) LCD Command Codes

Mfrs. Data sheet Clear screen, move cursor, shift display

19-Sep-02

Alphanumeric LCD - Algorithm

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Algorithm
mov A, command call cmd delay mov A, another_cmd call cmd delay mov A, #A call data delay mov A, #B call data delay .

Command and Data Write Routines

cmd: mov P1, A clr P3.3 clr P3.4 setb P3.5 clr P3.5 ret ;A has the cmd word ;RS=0 for cmd ;RW=0 for write ;H->L pulse on E

data:

mov P1, A ;A is ascii data setb P3.3 ;RS=1 data clr P3.4 ;RW=0 for write setb P3.5 ;H->L pulse on E clr P3.5 ret

19-Sep-02

Alphanumeric LCD - Algorithm

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Busy checking: After a read from the LCD, the D7 will contain the busy flag. Check this before sending any new command to the LCD, or use a big delay.
ready: setb P1.7 ;D7 as input clr P3.3 ;RS=0 cmd setb P3.4 ;RW=1 for read setb P3.5 ;H->L pulse on E clr P3.5 jb P1.7, again ret

again:

19-Sep-02

8051 Interrupts
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What are interrupts ?

A way to stop the processor from whatever it was doing and make it do another task Service multiple interfaced devices Multi-tasking systems 2 external, two for the timers and one for the serial port

Why and where do we need them ?

Interrupts in 8051

19-Sep-02

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Polling Vs Interrupts
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Polling:

CPU monitors all served devices continuously, looking for a service request flag Whenever it sees a request, it serves the device and then keeps polling CPU is always busy with polling doing the while any request loop If and when a device is ready and needs attention, it informs the CPU CPU drops whatever it was doing and serves the device and then returns back to its original task CPU is always free, when not serving any interrupts

Interrupts

19-Sep-02

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Interrupt Service Routine

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CPUs have fixed number of interrupts Every interrupt has to be associated with a piece of code called Interrupt Service Routine, or ISR.

If interrupt-x is received by CPU, the ISR-x is executed

CPU architecture defines a specific code address for each ISR, which is stored in the,

Interrupt vector Table (IVT)

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ISRs are basically subroutines, but they end with the RETI, instruction instead of RET When an interrupt occurs, the CPU fetches its ISR code address from the IVT and executes it.

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Interrupt Execution
1.

2.

3.

4. 5.

CPU finishes the instruction it is currently executing and stores the PC on the stack CPU saves the current status of all interrupts internally Fetches the ISR address for the interrupt from IVT and jumps to that address Executes the ISR until it reaches the RETI instruction Upon RETI, the CPU pops back the old PC from the stack and continues with whatever it was doiing before the interrupt occurred

19-Sep-02

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8051 Interrupts
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Vendors claim 6 hardware interrupts. One of them is the reset. So only 5 real interrupts in the 8051. Clones may differ. Two external interrupts INT0 and INT1, two timer interrupts TF0 and TF1 and one serial port interrupt S0 Interrupts can be individually enabled or disabled. This is done in the IE (Interrupt Enable Register) External interrupts (INT0 and INT1) can be configured to be either level or edge triggered.

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8051 - IVT
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Each Interrupt has 8 bytes for its ISR. If ISR is too big to fit in 8bytes, then use a ljmp
ORG 0

rom_start: LJMP main_code ORG 13H int1_vec: LJMP int1_isr ORG 30H main_code: ; . int1_isr: ;bla bla ;bla bla

Interrupt ROM Location Reset 0000H INT0 0003H TF0 000BH INT1 0013H TF1 001BH S0 0023H
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Pin 9 P3.2 P3.3

19-Sep-02

IE Register
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EA = 0, disable all interrupts

EA -ET2 ES ET1 EX1 ET0 EX0

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Other bits if set to 1, enable the corresponding interrupt, if set to 0, disable it. EX0 = enable INT0 ET0 = enable Timer0 EX1 = enable INT1 ET1 = enable Timer1 ES = enable serial port interrupt ET2 = (for 8052 clones only) enable Timer2

19-Sep-02

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Simple Example
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INT1 pin is connected to a switch that is normally high. Whenever it goes low, an LED should be turned on. LED is connected to port pin P1.3 and is normally OFF
org 0H ljmp MAIN org 13H INT1_ISR: setb P1.3 mov r3, #255 BACK: djnz r3, BACK clr P1.3 RETI org 30H MAIN: HERE: mov IE, #1000 0100B sjmp HERE end
19-Sep-02

;INT1 ISR ;turn on LED

;keep the led ON for a while ;turn OFF the LED ;use RETI, ***NOT RET***

;enable INT1, EA=1, EX1=1 ;stay here until interrupted

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External Interrupts
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INT0 and INT1

Level triggered : a low level on the pin causes interrupt Default mode Edge triggered : a high-to-low transition on the pin causes interrupt (IT1) TCON.2 = 1 INT1 is edge triggered (IT0) TCON.0 = 1 INT0 is edge triggered

Configuration in TCON register

IE0 (TCON.1) and IE1 (TCON.3)

In edge triggered mode, if interrupt INTx occurs, the CPU sets the IEx bit, which is cleared only after a RETI is executed Prevents interrupt within interrupt

Setup and Hold times for Edge triggered external interrupts

One machine cycle each

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Interrupt Priority
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Default Priority

INT0 > TF0 > INT1 > TF1 > S0

The ISR of an interrupt can be interrupted by a higher priority interrupt. The Default Priority can be changed by programming the IP register
--PT2 PS PT1 PX1 PT0 PX0

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To set higher priority to an interrupt, set its bit in IP to 1 If more than one 1 in IP, the default priority is used for all the interrupts that have 1 in IP

19-Sep-02

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Next Class
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8051 Timers Timers and Interrupts Applications

19-Sep-02

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