Kuwait

University

College of Engineering & Petroleum Electrical Engineering Department P.O. Box 5969 Safat 13060, Kuwait

CE 264 Lab Project

Completed by:
Name of student 1 ID

Instructor:
Dr. .

Fall 2011

Kuwait University

Computer Engineering Department

Fall 2011

Abstract
In this project we designed a digital circuit that is able to make a multiplication operation and display the result in seven segment display after converting binary back to decimal. This design require some implementation to do the operations like memory banks ,adders and some multiplexers to chose the immediate value or direct value and also the other selection line for the operation of multiplier, to be able to perform the shift-and-add technique. In theoretical simulation we can check the waveform data to show the multiplication operation and observe the output in the LED display in practicality.

EE 264

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Kuwait University

Computer Engineering Department

Fall 2011

Table of Contents
Table of Contents......................................................................................................................3 1 Introduction.............................................................................................................................4 2 Example Circuit.......................................................................................................................4 3 Implementation and discussion...............................................................................................5 4 Conclusion .............................................................................................................................9 5 References : ............................................................................................................................9

EE 264

3/9

Kuwait University

Computer Engineering Department

Fall 2011

1 Introduction
Multiplication is heavily used in arithmetic and array indexing. Practical designs often include commonly used circuit blocks such as adders, subtractors, multiplexers, decoders, and shifters. Altera provides efficient implementations of such blocks in the form of library modules that can be instantiated in Verilog designs. The compiler may recognize that a standard function specified in Verilog code can be realized using a library module, in which case it may automatically infer this module. However, many library modules provide functionality that is too complex to be recognized automatically by the compiler. These modules have to be instantiated in the design explicitly by the user. A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders. A variety of computer arithmetic techniques can be used to implement a digital multiplier. Most techniques involve computing a set of partial products, and then summing the partial products together. Using this system we will be able to use coding and chip programming to do the simple function of multiplication, which can be used in various higher-order design systems using digital logic.

2 Example Circuit
As an example, we will use the multiplier circuit shown in Figure 1.

The theoretical technique for multiplier and multiplicand in twos compliment is as shown below as an example:

EE 264

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Kuwait University

Computer Engineering Department

Fall 2011

Shift Multiplier x Doublewidth partial product p Shift Multiplicand a 0

0

(j)

Mux 1
k

xj

xj a cout

Adder
k

The figure above shows the general design of the desired Multiplier Algorithm.

3 Implementation and discussion

This project design can be divided into two parts: Software (Using Quartus II and Verilog HDL) Hardware (For real-time simulation)

EE 264

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Kuwait University

Computer Engineering Department

Fall 2011

Software: The software part can be further sub-divided into the Verilog HDL programming and the Schematic Block Design. Verilog HDL: This programming language uses modules with command lines inside that when run, the complier creates functions based on which the schematic system runs on. The code can be seen as below: module faddv(x,y,ci,s,cout); input x,y,ci; output cout,s; assign s= x^y^ci; assign cout = (x&y)|(x&ci)|(y&ci); endmodule Schematic Block Design: The design steps to successfully design the functionality for this project are as below: Create the circuit design, for the Verilog HDL code shown above, as shown below.

Figure 1. Basic Multiplier Circuit Convert this schematic to a block diagram so as to conveniently apply it as many times as required in the other design schematics. This block diagram using the multiplier circuit is as shown in Figure 2.

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Kuwait University

Computer Engineering Department

Fall 2011

Figure 2. Multiplier Block Diagram Now as per design specifications required in phase 1, we use this block diagram to design the entire Multiplier Circuit, and this can be seen below in Figure 3. This schematic uses six of the fadder block diagrams to be able to enact together with the single 3-bit inputs (3x2 bits) to give us the 6-bit final output to be later displayed on the LED display. As shown in the figure below we can see the two pairs of 3 fadder are connected in sequence with the starting Cin having digital value 0 and the other two connected to the Cout of the previous fadder. This sequence is required for us to obtained the desired 6-bits of the output. In turn this system must be also converted into a Block diagram for use in the Phase 2 part of the design as shown in Figure 4.

Figure 3. The Multiplier Design Schematic

EE 264

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Kuwait University

Computer Engineering Department

Fall 2011

Figure 4. Block Diagram Schematic for Figure 3. Now we can use this circuit to complete the phase one design by connecting the output to the LED display as shown below, with an output of 16 bit from the LED screen as shown in Figure 5.

Figure 5. Final design of Phase 1 Now to design the final part for the phase 2 design schematic, we need to just connect a flip-flop device (16-bit MUX), with an input voltage source selector, to give the output as desired specification. This can be seen in Figure 6.

Figure 6. The addition of the flip-flop into the phase 1 schematic design

EE 264

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Kuwait University

Computer Engineering Department

Fall 2011

4 Conclusion
This phase 1 implementation allowed us to learn how to design circuits that use 3-bit input multiplication of the digital numbers. When implemented for any digital circuit, it requires a verilog code, block diagram design and to verify the result we need timing diagram obtained after simulation. Phase 2 used a flip-flop with the input of two 16-bit inputs and a selector input voltage to obtain the desired output based on design specifications. Finally, during the run of this Quartus II design schematic, we can realize how this software can be downloaded into hardware, to give us the desired results as shown in the waveform output in the figure below. We can improve the project by using a ripple adder or full adder implementation and other design to implement this multiplication operation for higher order applications .

In/out = 0 1x2 = 02 In/out = 1

0 =3 5x6 ut = 1 In/o

Figure 7. Output Waveform

5 References :
1- Digital logic text book second edition with Verilog HDL design 2- Digital logic lab manual.

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