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Chapter 2

Programming Model, Addressing Modes and Instruction Set

An assembly language programmer should at least be familiar with the following features of the processor:

Register set

Instruction set

Addressing modes

Memory organization

CPU Registers

An MPU’s programming model shows only those internal registers that the programmer can directly control via the MPU’s instruction set.

can directly control via the MPU’s instruction set. Programming Model of the 68HC11 Accumulators A,B and

Programming Model of the 68HC11

Accumulators A,B and D:

- There are two 8-bit accumulators (ACCA and ACCB)

- Each may be a source or destination operand for 8-bit instructions.

- ACCD is the concatenation of A and B and instructions that modify ACCD actually modify ACCA and ACCB.

e.g.

LSLA

LSLD

modify ACCD actually modify ACCA and ACCB. e.g. LSLA LSLD b7 … b0 0 ACCA  

b7… b0 0

b7

b0

b7 … b0 0
0
0

ACCA

 
 
 

b7… b0 b7 … b0

b7

b0

b7 … b0 b7 … b0

b7

b0

ACCA

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ACCB

0
0

Index registers X and Y: The two 16-bit index registers are used primarily for indexed addressing (will be studied in addressing modes). There are also some arithmetic instructions involving the index registers.

e.g. INX (increments the contents of index register X, i.e., (IX) (IX)+$0001)

Stack pointer (SP): The 16-bit stack pointer maintains a program stack (will be studied later in detail) in RAM and must be initialized to point to RAM area before use.

Program counter (PC): Although it is shown in the programming model, the programmer does not have direct control over it like the other registers. It is usually given to show the amount of memory that can be directly addressed by the processor (the number of bits in the PC indicate the address range).

Condition code register (CCR): The 8-bit condition code register consists of individual bits, called flags, with different meanings. Each flag is used to indicate the status of a particular MPU condition and the logic value of the flags can be examined under program control to determine what sequence of instruction to follow. The flags in CCR are carry, overflow, zero, negative, interrup mask, half-carry, X-interrupt mask and stop disable.

e.g. Zero flag indicates whether the result of the previous operation is zero or not CLRA instructions clears ACCA and sets the zero (Z) flag.

Instruction Set

An MPU instruction usually has two parts, the opcode and the operand.

- the opcode tells the CPU what operation to perform

- the operand tells the CPU what data to operate on

e.g. 86 5A (LDAA #$5A in assembly language) opcode operand
e.g.
86 5A
(LDAA #$5A in assembly language)
opcode
operand

In 8-bit microprocessors, the instructions usually have one-byte opcodes but in 68HC11 there are also two byte opcodes (called the prebyte system) for increasing the number of possible instructions (because of having an additional 16-bit IY register).

e.g.,

instruction

mnemonic

machine code

operation

increment X

INX

$08

(IX) (IX)+$0001 (IY) (IY)+$0001

increment Y

INY

$18 $08

Addressing Modes

An addressing mode specifies how to find/locate the data. The addressing modes available for the 68HC11 are; inherent, immediate, direct, extended, indexed and relative modes.

Inherent addressing mode: used by instructions that do not need to access memory or I/O addresses (since all data for the instruction is within the CPU). The operand is obvious from the instruction mnemonic (assembly language representation).

e.g.,

instruction

mnemonic

machine code

operation

clear ACCA

CLRA

$4F

(A) $00

15

increment X

INX

$08

(IX) (IX)+$0001

set carry flag

SEC

$0D

C 1

add B to A

ABA

$1B

(A) (A)+(B)

transfer A to B

TAB

$16

(B) (A)

Immediate addressing mode: actual data follows the opcode.

-

used to initialize the registers with constants known at the time the program is written

-

requires a # prefix in the assembly language

 

-

can have both 8 or 16-bit operands

 

e.g.,

instruction

mnemonic

machine code

operation

load Acc.A with 64 load Acc.A with $64 add Acc.B $02 load X with #$01FF

LDAA #64

$86 $40 $86 $64 $CB $02 $CE $01 $FF

(A) $40 (decimal 64) (A) $64 (hexadecimal 64) (B) (B)+$02 (IX HIGH ) $01, (IX LOW ) $FF

LDAA #$64

ADDB #$02

LDX #$01FF

Direct addressing mode (also known as base-page addressing mode): single-byte data following the opcode is not the actual data but the address of the operand.

- 2 byte instructions (one byte opcode + one byte address) enables one to address only the first 256 locations between $00 and $FF (base-page)

e.g.,

memory location

$E000

$E001

machine code

mnemonic

operation (A) ($64)

$96

$64

machine code mnemonic operation (A) ← ($64) $96 $64 LDAA $64 : $0064 $C5 When executed

LDAA $64

:

$0064

$C5

When executed ACCA contains $C5

The above instruction is executed as follows:

- PC contains the $E000 (the address of the location where the opcode is stored).

- The opcode $96 is fetched from memory first.

- The instruction is then decoded as a direct mode one and another byte is read from the memory loc. $E001 as the address of the operand.

- When the address information $64 is read from the memory, full address information $0064 is formed in the memory address register.

- Another memory read operation is performed from the address location $0064.

- The contents of the corresponding location, i.e, $C5, is then stored in ACCA.

Extended addressing mode: similar to direct addressing but uses two bytes as the address of the operand

- 3 byte instructions (one byte opcode + two bytes address) enables one to address the entire 64Kbyte (2 16 = 65,536 = 64K) address space between $0000 and $FFFF.

e.g.,

memory location

$E000

$E001

$E002

machine code

mnemonic

operation

(A) ($6400)

$B6

$64

$00

LDAA $6400 $E001 $E002 machine code mnemonic operation (A) ← ($6400) $B6 $64 $00 : $6400 $F5 When

:

$6400

$F5

When executed ACCA contains $F5.

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e.g.,

memory location

machine code ($)

mnemonic

operation

$0000

FC 12 34

LDD $1234

ACCD ($1234:$1235)

 

{ ACCA ($1234), ACCB ($1235) }

 

$0003

FF 12 34

STX $1234

($1234:$1235) IX

 

{ ($1234) IX HIGH , ($1235) IX LOW ) }

 

:

$1234

$F5

$1235

$00

When executed with ACCA=$FF, ACCB=$FF and IX=$2345, the register and memory contents will change as follows ACCA=$F5, ACCB=$00, IX=$2345, ($1234)=$23, ($1235)=$45

Indexed addressing mode: makes it easy to handle tables and blocks of data in memory.

-

an indexed instruction format is as follows:

 
 

Operation

Offset, Index_register

(e.g. LDAA $05,X)

where Offset is an unsigned 8-bit value and Index_register is either X or Y.

-

the effective address of the operand in indexed mode is calculated by the CPU as the sum of the offset and the contents of the IX or IY register. i.e.,

operand address = (IX) + offset

or

operand address = (IY) + offset

e.g.,

machine code ($)

mnemonic

comment

A6 05

LDAA $05,X

effective address = (IX) + $05

A6 05 LDAA $05,X effective address = (IX) + $05 opcode offset if (IX) = $C500

opcode

offset

if (IX) = $C500 then the effective address (address of the operand) is $C505 and

A ($C505)

Examples:

(address of the operand) is $C505 and A ← ($C505) Examples: Contents of memory location $C505

Contents of memory location $C505 is loaded into ACCA

(address of the operand) is $C505 and A ← ($C505) Examples: Contents of memory location $C505

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Relative addressing mode: is used for branch instructions.

-

Branch instructions often do not jump very far from the current location.

-

M68HC11 branch instructions use relative addressing while jump instructions use extended addressing.

-

a relative addressing mode instruction adds the offset to PC to find the address of the next instruction to execute.

e.g.,

(extended mode jump instruction)

 

address

ADDA $50 JMP $02 $00 . . . LDAB $40
ADDA
$50
JMP
$02
$00
.
.
.
LDAB
$40
ADDA $50 JMP $02 $00 . . . LDAB $40
ADDA $50 JMP $02 $00 . . . LDAB $40

0100

0101

0102

0103

0104

0200

After this instruction is executed, PC is updated to have $0200, which is the address of the next instruction to be executed.

0201

 

e.g.,

(relative mode branch instruction) (forward jump)

address opcode offset 0100 ADDA 0101 $50 0102 BRA 0103 $03 0104 PC points to
address
opcode
offset
0100
ADDA
0101
$50
0102
BRA
0103
$03
0104
PC points to $0104 after the fetch cycle and also the
operand fetch. Following the execution, $03 is added
to the PC and the next instruction to be executed
.
becomes the one located at address $0107.
.
.
0107
STAA
jump forwards
$20
Since it is designed to branch in either direction, the 8-bit address byte (offset) is interpreted as a
signed 7-bit value (in 2’s complement). Hence the branching range is;

(PC + 2) – 128 Destination (PC + 2) +127

PC – 126 Destination PC+129

≤ (PC + 2) +127 PC – 126 ≤ Destination ≤ PC+129 Location of the current

Location of the current instruction

Location of the instruction to jump

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Effectively, one can branch to locations between 126 bytes backwards and 129 byte forwards relative to the address of the branch instruction.

e.g.,

(relative mode branch instruction) (backward jump)

address

0100

0101

0102

0103

0104

0107

ADDA $50 BRA $FC . . . STAA $20
ADDA
$50
BRA
$FC
.
.
.
STAA
$20
0102 0103 0104 0107 ADDA $50 BRA $FC . . . STAA $20 jump backwards PC

jump backwards

PC points to $0104 after the fetch cycle and the operand fetch. Following the execution, PC is updated and $FC (-4) is added to the low byte of PC

and the next instruction to be executed becomes the

one located at address $0100.

Instruction Set

68HC11 has 329 instructions but counting only the different operations there are 153 instructions, which can further be categorized into 14 different sets.

Learning a new instruction set is easier if one first learns the categories of instructions and then learns what instructions are in each category.

1) Load registers

e.g.,

LDAA

(A) (M)

(10 instructions)

LDAB

(B) (M)

LDX

(IX) (M:M+1)

2) Store registers

e.g.,

STAA

(M) (A)

(10 instructions)

STAB

(M) (B)

STY

(M:M+1) (IY)

3) Transfer registers

e.g.,

TBA

(A) (B)

(8 instructions)

TAB

(B) (A)

TSX

(IX) (SP)

XGDY

(D) ←→ (IY)

4) Decrement/Incremen t

e.g.,

DEC

(M) (M) - 1

(12 instructions)

DECA

(A) (A) - 1

INX

(IX) (IX) + 1

5) Clear/Set

e.g.,

CLR

(M) 0

(5 instructions)

CLRA

(A) 0

BSET

set bits (M)

6) Arithmetic

e.g.,

ABA

(A) (A) + (B)

(21 instructions)

ABX

(IX) (IX) + (B)

SUBA

(A) (A) - (M)

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MUL

(D) (A) * (B)

NEGA

(A) 2’s complement of (A)

7) Logic

e.g.,

ANDA

(A) (A) AND (M)

(9 instructions)

EORB

(B) (B) XOR (M)

COMB

(B) 1’s complement of (B)

8) Rotates/Shifts

e.g.,

RORA

rotate right A

(21 instructions)

LSR

logic shift right (M)

9) Data test

e.g.,

TSTA

test if (A) = 0

(11 instructions)

CMPA

(A) – (M)

CPX

(X) – (M:M+1)

10) Conditional branch

e.g.,

BMI

branch if minus

(16 instructions)

BEQ

branch if equal to zero

BCC

branch if carry clear

11) Jump and branch

e.g.,

JMP

unconditional jump

(9 instructions)

BRA

unconditional branch (short jump)

JSR

jump to subroutine

12) Condition code

e.g.,

CLC

(C) 0

(6 instructions)

CLV

(V) 0

TAP

(CCR) (A)

TPA

(A) (CCR)

13) Interrupts

e.g.,

CLI

(I) 0

(5 instructions)

SEI

(I) 1

RTI

return from interrupt

SWI

software interrupt

WAI

wait for interrupt

14) Misc.

e.g.,

NOP

no operation

(3 instructions)

STOP

stop clocks

TEST

special test mode

Load register instructions

no operation (3 instructions) STOP stop clocks TEST special test mode Load register instructions 20

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Note that it is possible to use the same instruction in different addressing modes.

e.g., use of LDAA instruction in different addressing modes

Code

Mnemonic

Addressing Mode

Operation

86

40

LDAA #$40

immediate

(A) $40 (A) ($40) (A) ($4000) (A) ((IX) + $40) (A) ((IY) + $40)

96

40

LDAA $40

direct

B6 40 00 A6 40

LDAA $4000

extended

LDAA $40,X

indexed

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A6 40

LDAA $40,Y

indexed

Note that these instructions affect the Z and N flags according to the value that is loaded, reset the V flag and do not effect the C flag in the condition code register (CCR).

Note: At this stage it is helpful to study the full instruction set of the 68HC11 (Appendix A)

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