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Prepared by: Laxman Arram Reviewed by: Srinivasa Kakumanu Approved by: NG Raju
JG-004-DTF
Document Amendments Ver. No 1.0 Date 20/01/2009 Sec No Amendments made Initial Version Prepared by Reviewe d by Laxman Srinivas Approv ed by NG Raju
JG-004-DTF
Table of Contents
1 2. 3. 4. 5. 6 Introduction............................................................. Error! Bookmark not defined. DFT Flow Charts 6 EDA Tools . 9 Test Requirements and goals . 10 Test Features and Limitations 10 DFT Planning & Implementation 11 6.1 Test Modes .. 11 6.2 JTAG/BSCAN. 11 6.2.1 JTAG Interface ...................................................................................... 11 6.2.2 JTAG Instructions .................................................................................. 11 6.2.3 JTAG ID Code....................................................................................... 11 6.2.4 Non-BSCAN pins .................................................................................. 11 6.2.5 Test Compliance pin values ................................................................... 12 6.2.6 Bond pins .............................................................................................. 12 6.2.7 Pad Order .............................................................................................. 12 6.2.8 Description of used BSCAN Cells ......................................................... 12 6.2.9 BSDL .................................................................................................... 12 6.2.10 Disabling Mechanism for JTAG/BSCAN ............................................... 12 6.2.11 Use of JTAG for Scan/Test Mode signal generation ............................... 12 6.2.12 Use of JTAG for MBIST Interface ......................................................... 13 6.3 MBIST .......................................................................................................... 13 6.3.1 Introduction ........................................................................................... 13 6.3.2 Algorithm selection................................................................................ 13 6.3.3 Memory Grouping ................................................................................. 13 6.3.4 Slow-Speed/At-speed MBIST ................................................................ 13 6.3.5 MBIST Interface .................................................................................... 14 6.3.6 MBIST SDC .......................................................................................... 14 6.4 MACROTEST............................................................................................... 14 6.4.1 Introduction ........................................................................................... 14 6.4.2 Scan & Clocking Information for Macrotest........................................... 14 6.4.3 Algorithm .............................................................................................. 14 6.5 SCAN ............................................................................................................ 14 6.5.1 Design Information ................................................................................ 14 6.5.2 Scan Mode design changes .................................................................... 15 6.5.3 Scan Configuration ................................................................................ 15 6.5.4 Scan DRC and fixes ............................................................................... 15 6.5.5 Scan Chain Information ......................................................................... 15 6.5.6 Scan SDC .............................................................................................. 16 6.6 ATPG ............................................................................................................ 16 6.6.1 Stuck-at Fault Test ................................................................................. 16 6.6.2 Transition Delay Fault (TDF) Test ......................................................... 16 6.6.3 Path Delay Fault (PDF) Test .................................................................. 17
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6.6.4 Bridge Fault Test ................................................................................... 17 6.6.5 IDDQ Test ............................................................................................. 17 6.6.6 Burn-In Test...177 DFT Verification18 DFT Pattern Handoff19
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1. Introduction
As always, the primary objective of DFT is to provide the capability to generate and apply a high quality test set in an efficient and cost effective manner. Understand design description from the test perspective 1. Components to be tested such as IOs, RAM/ROM, PLL/DLL, IPs, Analog blocks and the core logic. Mention the Full Chip block diagram highlighting test requirements. 2. List of Hard and soft IPs 3. Functional clock domains and maximum frequency of operation 4. Existing test structures 5. Physical partitioning information 6. Clocking and Flop count information for each physical block Understand test features recommended for the targeted process technology 1. stuck-at fault test 2. transition fault test 3. path delay test 4. bridging fault test
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NO
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Formal Verification
NO
YES ATPG Setup for EDT and BYPASS modes and Design Hand-off for Physical Design
ATPG
NO
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3 EDA TOOLS
We use industry standard sign off tools from Mentor, Synopsys and Cadence
LogicVision) )
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5 Tester Features/Limitations
Understand the following which helps in defining the DFT architecture for Scan. - Tester Memory configuration (memory per scan chain) - Maximum number of scan chains and IOs supported - Maximum frequency that ATE can support
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6.2 JTAG/BSCAN
This section describes the JTAG interface and its application in the full chip. It also describes how the already existing TAP controllers are configured. 6.2.1 JTAG Interface Describes 5 top levels pins and corresponding pads used. Mention whether required PU/PD pads are used for each pin Describe the JTAG pin sharing with the existing JTAG Controller and mention the values of the BSCAN Compliance pins. Describe the JTAG interface to the embedded TAP Controllers using diagrams JTAG Instructions Instructions and their opcodes Instruction executed when unused-opcode is selected? Is it Byapss? What is the default JTAG instruction up-on JTAG reset? JTAG ID Code This section describes the JTAG ID code value as mentioned by the client. Non-BSCAN pins Mentions the Non-BSCAN pins - Power and Ground pins - Test Compliance pins - Analog pins - Bonded pins.? Test Compliance pin values Mention the Test Compliance pins and their values which are generally used to generate JTAG/BSCAN mode control signals.
Bond pins
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Mention the list of BOND pins for each package to decide on BSCAN Chain. If the BOND pins are less, same BSCAN chains can be used with separate pattern generation in the BSDL flow. If BOND pins are more, we may need to go with separate BSCAN chain for each package with MUX logic. Pad Order Mentioned the pad pin order which has to be followed for BSCAN chain insertion Description of used BSCAN Cells This section describes the BSCAN cells used in the design with diagrams. This helps immensely while simulation debug. BSDL Mentioned the BSDL desicription. - Full package - Other packages Disabling Mechanism for JTAG/BSCAN Mention various mechanisms to disable the JTAG during functional mode of operation. It will give clear information if mentioned with diagrams and signal waveform sequence. Use of JTAG for Scan/Test Mode signal generation This section describes the JTAG sequence and operation for scan/test mode signal generation and state of JTAG FSM during that mode. Mention with signal waveform sequence. Use of JTAG for MBIST Interface This section describes the following mechanisms Description of the JTAG interface to MBIST with diagrams Enabling MBIST controllers through JTAG Memory Fail status capture and Shift-out MBIST Diagnostic support
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MBIST
6.3.1 Introduction
This section describes memory types and their clocking in the design to decide the MBIST algorithm, memory grouping, register pipe-lining, etc., Information has to be mentioned here why/why not memory diagnostic/repair is required. Information regarding Shadow-Logic testing can be mentioned here. Explain the pin description of each memory type with diagram which would be helpful in MBIST insertion (though the documentation is available in the memory datasheets)
6.3.4
Slow-Speed/At-speed MBIST
This section mentions the test logic support for slow/at-speed MBIST such as clock muxing, register-pipelining, etc., with diagrams.
6.4 MACROTEST
6.4.1 Introduction
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6.4.3 Algorithm
This section describes the source of pattern file which is going to be translated by fastscan to create Macrotest patterns. Mention the steps of the algorithm.
6.5 SCAN
6.5.1 Design Information
This section contain the following information for each physical block and full chip - Functional clocks (clock diagrams with clock generation logic) and their clock crossing information to help in addressing clock skew issues - Reset generation diagrams - Flip-flop count for each functional clock. Helpful in scan chain balancing and estimating the scan IO requirements. - Scan Information of the embedded Hard IP and their connectivity; scan chain length in the Hard IP generally decides the internal scan chain length for Scan Compression and hence the Compression Ratio. - Measures to avoid clock skew issues during Scan mode
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Scan Methodology Scan Control Signals such as Scan Enable, Scan Clocks, Test Resets, Scan Mode Scan IO/Channels Lock-Up Latch and Terminal Lock-up Latch usage Test point insertion Scan Chain lengths and compression ratio Non-Scan modules/instances and mention how they will be tested. Mention EDT/Scan Compression interface to the internal chains with diagram and describe the pins
6.6 ATPG
This section describes the ATPG flow for each of the targeted fault model.
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Load the Net pairs as the targeted fault sites Add all the faults and create the patterns which targets bridging faults. This method is more accurate in targeting the net pairs that are likely to bridge because of their physical characteristics
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y y
For the input pins that are not permitted to toggle, constrain it to 0 or 1 For the bidi pins that are not permitted to toggle, constrain it to Z to avoid generating patterns with contention. For the bidis chosen to be in the group of toggling pins, ensure bidis are always in input mode. Define scan chains, groups, clocks etc to enable DRC and enter ATPG mode. Clocks should not exceed the number Compute the number of patterns that will fit vector memory based on that set the limit on the ATPG patterns o Generate the patterns and order the patterns so that the most coverage comes first. This will help in reaching the coverage requirement with memory limitation in place. Save the patterns in tester format
7 DFT Verification
This section documents the verification status of each of the test features implemented TEST NAME NO-DELAY (or) ZERO-DELAY Pass/Fail WORSTCASE(MAXDELAYS) Pass/Fail BEST-CASE(MINDELAYS) Pass/Fail
ATPG: Stuckat(Compression Bypassed) ATPG: Stuck-at (Compression Enable) ATPG: Transition(Compression Bypassed) ATPG: Transition(Compression Enabled) ATPG: Pathdelay(Compression Bypassed) ATPG:Pathdelay(Compression Enabled) ATPG: Iddq (Compression Bypassed) ATPG: Burn-in (Compression Bypassed) MBIST: Production
Pass/Fail Pass/Fail
Pass/Fail Pass/Fail
Pass/Fail Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
Pass/Fail
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Pass/Fail Pass/Fail
Pass/Fail Pass/Fail
Pass/Fail Pass/Fail