VHDL

Practical Exam Guide

1
Contents
1. 2. 3. 4. 5. 6. Multiplier 4*4 Multiplier 8*8 RAM 128*8 RAM 16*4 ROM 128*8 ROM 8*2 1. 2. 3. 4. 5. 6.

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TLC Sequence Detector Vending Machine EDL Smart Door Suez Canal

1
Contents

1. 2. 3. 4. 5. 6.

Multiplier 4*4 Multiplier 8*8 RAM 128*8 RAM 16*4 ROM 128*8 ROM 8*2

Multiplier 4 bit * 4 bit

C:\FPGAdv52\Libraries\S\src\@mult\@r@t@l.vhd 11/03/11 13:45:45 -- hds header_start --- VHDL Architecture S.Mult.RTL --- Created: -by - Pharaoh.UNKNOWN (S) -at - 13:07:36 11/03/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Mult IS -- Declarations Port ( x,y : In STD_Logic_Vector ( 3 downto 0 ); z : Out STD_Logic_Vector (7 downto 0)); END Mult ; -- hds interface_end ARCHITECTURE RTL OF Mult IS signal pp1: unsigned (3 downto 0); signal pp2: unsigned (4 downto 0); signal pp3: unsigned (5 downto 0); signal pp4: unsigned (6 downto 0); signal ppp1: unsigned (5 downto 0); signal ppp2: unsigned (7 downto 0); signal pppp1: unsigned (7 downto 0); BEGIN pp1 pp2 pp3 pp4 <= <= <= <= unsigned unsigned unsigned unsigned (x) when y(0)='1' else (others => '0'); (x&'0') when y(1)='1' else (others => '0'); (x&"00") when y(2)='1' else (others => '0'); (x&"000") when y(3)='1' else (others => '0');

ppp1 <= ("00"&pp1) + ('0'&pp2); ppp2 <= ("00"&pp3) + ('0'&pp4); pppp1 <= ("00"&ppp1) + ppp2; z <= STD_Logic_Vector(pppp1); END RTL;

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Mult 4.4 Simulation Code force -freeze sim:/mult/x 1111 0 force -freeze sim:/mult/y 1010 0 add wave sim:/mult/* run run run run run

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/mult/x 15

/mult/y 10

/mult/z 150

/mult/pp1 0000 /mult/pp2 11110 /mult/pp3 000000 /mult/pp4 1111000 /mult/ppp1 011110 /mult/ppp2 01111000 /mult/pppp1 10010110

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Entity:mult Architecture:rtl Date: Fri Dec 30 13:45:41 HDS 2011 Row: 1 Page: 1

Multiplier 8 bit * 8 bit

C:\FPGAdv52\Libraries\S\src\@mult_8\@r@t@l.vhd 12/30/11 13:55:20 -- hds header_start --- VHDL Architecture S.Mult_8.RTL --- Created: -by - Pharaoh.UNKNOWN (S) -at - 14:09:52 11/16/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Mult_8 IS -- Declarations PORT ( x,y : IN STD_Logic_Vector (7 Downto 0); z : OUT STD_Logic_Vector (15 Downto 0)); END Mult_8 ; -- hds interface_end ARCHITECTURE RTL OF Mult_8 IS Signal p1: unsigned (7 Downto 0); Signal p2: unsigned (8 Downto 0); Signal p3: unsigned (9 Downto 0); Signal p4: unsigned (10 Downto 0); Signal p5: unsigned (11 Downto 0); Signal p6: unsigned (12 Downto 0); Signal p7: unsigned (13 Downto 0); Signal p8: unsigned (14 Downto 0); Signal Signal Signal Signal pp1: pp2: pp3: pp4: unsigned unsigned unsigned unsigned (9 Downto 0); (11 Downto 0); (13 Downto 0); (15 Downto 0);

Signal ppp1: unsigned (11 Downto 0); Signal ppp2: unsigned (15 Downto 0); Signal pppp1: unsigned (15 Downto 0); BEGIN p1 p2 p3 p4 p5 p6 p7 p8 pp1 pp2 pp3 pp4 <= <= <= <= <= <= <= <= <= <= <= <= unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned ("00" ("00" ("00" ("00" & & & & (x) ( x ( x ( x ( x ( x ( x ( x p1) p3) p5) p7) when y(0) = '1' else (others => '0'); & '0') when y(1) = '1' else (others => '0'); & "00") when y(2) = '1' else (others => '0'); & "000") when y(3) = '1' else (others => '0'); & "0000") when y(4) = '1' else (others => '0'); & "00000") when y(5) = '1' else (others => '0'); & "000000") when y(6) = '1' else (others => '0'); & "0000000") when y(7) = '1' else (others => '0'); + + + + ('0' ('0' ('0' ('0' & & & & p2); p4); p6); p8);

ppp1 <= ("00" & pp1) + pp2; ppp2 <= ("00" & pp3) + pp4; pppp1 <= ("0000" & ppp1) + ppp2; z <= STD_Logic_Vector(pppp1); END RTL;

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Mult 8.8 Simulation Code force -freeze sim:/mult_8/x 01100100 0 force -freeze sim:/mult_8/y 00001100 0 add wave sim:/mult_8/* run run run run run run

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/mult_8/x 100

/mult_8/y 12

/mult_8/z 1200

/mult_8/p1 00000000 /mult_8/p2 000000000 /mult_8/p3 0110010000 /mult_8/p4 01100100000 /mult_8/p5 000000000000 /mult_8/p6 0000000000000 /mult_8/p7 00000000000000 /mult_8/p8 000000000000000 /mult_8/pp1 0000000000 /mult_8/pp2 010010110000 /mult_8/pp3 00000000000000 /mult_8/pp4 0000000000000000 /mult_8/ppp1 010010110000 /mult_8/ppp2 0000000000000000 /mult_8/pppp1 0000010010110000

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Entity:mult_8 Architecture:rtl Date: Fri Dec 30 13:56:15 HDS 2011 Row: 1 Page: 1

RAM 128 * 8 1024 bit 128 Byte

C:\FPGAdv52\Libraries\S\src\@r@a@m_128_8\rtl.vhd 12/30/11 12:10:54 -- hds header_start --- VHDL Architecture S.RAM_128_8.rtl --- Created: -by - Pharaoh.UNKNOWN (S) -at - 11:42:32 12/30/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY RAM_128_8 IS -- Declarations PORT (din: IN STD_Logic_Vector (7 downto 0); dout: OUT STD_Logic_Vector (7 downto 0); addr: IN STD_Logic_Vector ( 6 downto 0); wr,clk: IN STD_Logic); END RAM_128_8 ; -- hds interface_end ARCHITECTURE rtl OF RAM_128_8 IS type mem_type is array (0 to 127) of STD_Logic_vector (7 downto 0); signal mem: mem_type; BEGIN Process (clk) begin if(rising_edge(clk)) then if(wr='1') then mem(conv_integer(unsigned(addr))) <= din; end if; end if; End Process; dout <= mem(conv_integer(unsigned(addr))); END rtl;

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RAM 128.8 Simulation Code force -freeze sim:/ram_128_8/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/ram_128_8/wr 1 0 force -freeze sim:/ram_128_8/addr 0000000 0 force -freeze sim:/ram_128_8/din 00000000 0 force force force force force force force force force force force force force force force force force force force force -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/din sim:/ram_128_8/din sim:/ram_128_8/din sim:/ram_128_8/din sim:/ram_128_8/din sim:/ram_128_8/din sim:/ram_128_8/din sim:/ram_128_8/din sim:/ram_128_8/din sim:/ram_128_8/din 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 01100100 01100101 01100110 01100111 01101000 01101001 01101010 01101011 01101100 01101101 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000

force -freeze sim:/ram_128_8/wr 0 1100 force force force force force force force -freeze -freeze -freeze -freeze -freeze -freeze -freeze sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr sim:/ram_128_8/addr Page 1 0000000 0000001 0000010 0000011 0000100 0000101 0000110 1200 1300 1400 1500 1600 1700 1800

RAM 128.8 Simulation Code force -freeze sim:/ram_128_8/addr 0000111 1900 force -freeze sim:/ram_128_8/addr 0001000 2000 force -freeze sim:/ram_128_8/addr 0001001 2100 add wave sim:/ram_128_8/* run run run run run run run run run run run run run run run run run run run run run run run

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/ram_128_8/din 0 /ram_128_8/dout X /ram_128_8/addr 0 /ram_128_8/wr /ram_128_8/clk /ram_128_8/mem

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101 101 1

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107 107 7

108 108 8

109 109 9 100 0 101 1 102 2 103 3 104 4 105 5 106 6 107 7 108 8 109 9

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Entity:ram_128_8 Architecture:rtl Date: Fri Dec 30 12:17:46 HDS 2011 Row: 1 Page: 1

RAM 16 * 4 64 bit 8 Byte

C:\FPGAdv52\Libraries\S\src\@r@a@m_16_4\@r@t@l.vhd 12/30/11 12:19:28 -- hds header_start --- VHDL Architecture S.RAM_16_4.RTL --- Created: -by - Pharaoh.UNKNOWN (S) -at - 17:25:54 11/16/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY RAM_16_4 IS -- Declarations PORT (addr,din: IN STD_Logic_Vector (3 downto 0); dout: OUT STD_Logic_Vector (3 downto 0); wr,clk: IN STD_Logic); END RAM_16_4 ; -- hds interface_end ARCHITECTURE RTL OF RAM_16_4 IS type mem_type is array (0 to 15) of STD_Logic_vector (3 downto 0); signal mem: mem_type; BEGIN Process (clk) begin if(rising_edge(clk)) then if(wr='1') then mem(conv_integer(unsigned(addr))) <= din; end if; end if; End Process; dout <= mem(conv_integer(unsigned(addr))); END RTL;

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RAM 16.4 Simulation Code force -freeze sim:/ram_16_4/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/ram_16_4/wr 1 0 force -freeze sim:/ram_16_4/addr 0000 0 force -freeze sim:/ram_16_4/din 0000 0 force force force force force force force force force force force force force force force force force force force force force force force force force force force force force -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din sim:/ram_16_4/din Page 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300

RAM 16.4 Simulation Code force -freeze sim:/ram_16_4/din 0010 1400 force -freeze sim:/ram_16_4/din 0001 1500 force -freeze sim:/ram_16_4/din 0000 1600

force -freeze sim:/ram_16_4/wr 0 1700 force force force force force force force force force force force force force force force force -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze -freeze sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr sim:/ram_16_4/addr 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300

add wave sim:/ram_16_4/* run run run run run run run run run run run Page 2

RAM 16.4 Simulation Code run run run run run run run run run run run run run run run run run run run run run run run run run

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/ram_16_4/addr 0

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/ram_16_4/din 0

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/ram_16_4/dout X 15 14 13 12 11 10 9

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/ram_16_4/wr

/ram_16_4/clk

/ram_16_4/mem

{1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000}

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Entity:ram_16_4 Architecture:rtl Date: Fri Dec 30 13:27:44 HDS 2011 Row: 1 Page: 1

ROM 128 * 8 1024 bit 128 Byte

C:\FPGAdv52\Libraries\S\src\@r@o@m_128_8\@r@t@l.vhd 12/30/11 12:19:53 -- hds header_start --- VHDL Architecture S.ROM_128_8.RTL --- Created: -by - Pharaoh.UNKNOWN (S) -at - 16:39:55 11/16/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY ROM_128_8 IS -- Declarations PORT (addr: IN STD_Logic_Vector (6 downto 0); dout: OUT STD_Logic_Vector (7 downto 0); clk: IN STD_Logic); END ROM_128_8 ; -- hds interface_end ARCHITECTURE RTL OF ROM_128_8 IS type rom_type is array (0 to 127) of STD_Logic_Vector(7 downto 0); constant rom: rom_type:= ("00000001","00000010","00000011","00000100", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "10101010","10101010","10101010","10101010","10101010","10101010","10101010","10101010", "00000001","00000010","00000011","00000100"); BEGIN Process (clk) Begin if (rising_edge(clk)) then dout <= rom(conv_integer(unsigned(addr))); end if; End Process; END RTL;

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ROM 128.8 Simulation Code force -freeze sim:/rom_128_8/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/rom_128_8/addr 0000000 0 force -freeze sim:/rom_128_8/addr 0000001 200 force -freeze sim:/rom_128_8/addr 0000010 400 force -freeze sim:/rom_128_8/addr 0000011 600 force -freeze sim:/rom_128_8/addr 0000100 800 force -freeze sim:/rom_128_8/addr 1111011 1000 force -freeze sim:/rom_128_8/addr 1111100 1200 force -freeze sim:/rom_128_8/addr 1111101 1400 force -freeze sim:/rom_128_8/addr 1111110 1600 force -freeze sim:/rom_128_8/addr 1111111 1800 add wave sim:/rom_128_8/* run run run run run run run run run run run run run run run run run run run

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/rom_128_8/addr 0000000

0000001

0000010

0000011

0000100

1111011

1111100

1111101

1111110

1111111

/rom_128_8/dout

XXXXXXXX

00000001

00000010

00000011

00000100

10101010

00000001

00000010

00000011

00000100

/rom_128_8/clk

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Entity:rom_128_8 Architecture:rtl Date: Fri Dec 30 13:34:57 HDS 2011 Row: 1 Page: 1

ROM 8*2 16 bit 2 Byte

C:\FPGAdv52\Libraries\S\src\@r@o@m_8_2\rtl.vhd 12/30/11 13:38:58 -- hds header_start --- VHDL Architecture s.ROM_8_2.rtl --- Created: -by - Pharaoh.UNKNOWN (S) -at - 13:38:41 12/30/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY ROM_8_2 IS -- Declarations PORT (addr: IN STD_Logic_Vector (2 downto 0); dout: OUT STD_Logic_Vector (1 downto 0); clk: IN STD_Logic); END ROM_8_2 ; -- hds interface_end ARCHITECTURE rtl OF ROM_8_2 IS type rom_type is array (0 to 7) of STD_Logic_Vector(1 downto 0); constant rom: rom_type:= ("00","01","10","11","00","01","10","11"); BEGIN Process (clk) Begin if (rising_edge(clk)) then dout <= rom(conv_integer(unsigned(addr))); End if; End Process; END rtl;

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ROM 8.2 Simulatin Code force -freeze sim:/rom_8_2/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/rom_8_2/addr 000 0 force -freeze sim:/rom_8_2/addr 001 200 force -freeze sim:/rom_8_2/addr 010 300 force -freeze sim:/rom_8_2/addr 011 400 force -freeze sim:/rom_8_2/addr 100 500 force -freeze sim:/rom_8_2/addr 101 600 force -freeze sim:/rom_8_2/addr 110 700 force -freeze sim:/rom_8_2/addr 111 800 add wave sim:/rom_8_2/* run run run run run run run run run run run

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/rom_8_2/addr 000

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010

011

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111

/rom_8_2/dout UU

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01

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11

/rom_8_2/clk

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Entity:rom_8_2 Architecture:rtl Date: Fri Dec 30 13:41:54 HDS 2011 Row: 1 Page: 1

2
Contents

1. 2. 3. 4. 5. 6.

TLC Sequence Detector Vending Machine EDL Smart Door Suez Canal

TLC

S_TLC\TLC\struct

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

Declarations Ports: Start : std_logic clk : std_logic rst : std_logic Green : std_logic Red : std_logic Yellow : std_logic Diagram Signals: SIGNAL finish_r : std_logic SIGNAL finish_y : std_logic Project: <enter project name here>

<company name>
Title: Path: Edited: <enter diagram title here> S_TLC/TLC/struct by Pharaoh on 16 Dec 2011

<enter comments here>

rst

rst

clk

clk

S_TLC TLC_FSM I2

Green

Green

Yellow

Start

Start

Yellow

finish_y Red finish_r Red

clk Yellow rst

clk en rst

S_TLC Counter_2bit I0

finish_y

clk Red rst

clk en rst

S_TLC Counter_4bit I1

finish_r

Printed by Pharaoh on 12/29/2011 at 05:12:47 PM

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S_TLC\TLC_FSM\fsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status SIGNAL SCOPE Green OUT Red OUT Yellow OUT State Register Statements DEFAULT RESET STATUS '0' COMB '0' COMB '0' COMB Process Declarations

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

<company name>
Title: Path: Edited: <enter diagram title here> S_TLC/TLC_FSM/fsm by Pharaoh on 16 Dec 2011

Project:

<enter project name here>

<enter comments here>

s0

Green <= '1'; Yellow <= '0'; Red <= '0';

finish_r = '1'

Start = '1'

Green <= '0'; Yellow <= '0'; Red <= '1';

s2

finish_y = '1'

s1

Green <= '0'; Yellow <= '1'; Red <= '0';

Printed by Pharaoh on 12/29/2011 at 05:13:23 PM

Page 1 of 1

Simulation view signals # .signals force -freeze sim:/tlc/clk 1 force -freeze sim:/tlc/rst 1 force -freeze sim:/tlc/rst 0 force -freeze sim:/tlc/start force -freeze sim:/tlc/start force -freeze sim:/tlc/start add wave sim:/tlc/* run run run run run run run run run run run run run run run run run run run run run run run run run run run run run 0, 0 {50 ns} -r 100 0 200 0 0 1 300 0 400

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Simulation run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run Page 2

Simulation run run run run run run run

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/tlc/start /tlc/clk /tlc/rst

/tlc/green

/tlc/red

/tlc/yellow

/tlc/finish_r

/tlc/finish_y /tlc/yellow_internal /tlc/red_internal

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Entity:tlc Architecture:struct Date: Fri Dec 16 20:17:15 HDS 2011 Row: 1 Page: 1

C:\FPGAdv52\Libraries\S_TLC\src\@counter_2bit\rtl.vhd 12/16/11 18:20:57 -- hds header_start --- VHDL Architecture S_TLC.Counter_2bit.rtl --- Created: -by - Pharaoh.UNKNOWN (S) -at - 18:12:46 12/16/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Counter_2bit IS -- Declarations PORT (rst, en, clk: IN Std_Logic; q : OUT Std_Logic); END Counter_2bit ; -- hds interface_end ARCHITECTURE rtl OF Counter_2bit IS Signal count_sig: unsigned (1 downto 0); BEGIN Process(rst,clk) Begin if (rst ='1') then count_sig <= (Others => '0'); elsif (rising_edge(clk)) then if (en = '1') then count_sig <= count_sig +1; end if; end if; end process; q <= count_sig(0) and count_sig(1); END rtl;

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Simulation 2bit view signals # .signals force -freeze sim:/counter_2bit/rst 1 0 force -freeze sim:/counter_2bit/rst 0 200 force -freeze sim:/counter_2bit/en 0 0 force -freeze sim:/counter_2bit/en 1 400 force -freeze sim:/counter_2bit/clk 1 0, 0 {50 ns} -r 100 add wave sim:/counter_2bit/* run run run run run run run run run run run run run run run run run run run run run run

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/counter_2bit/rst /counter_2bit/en /counter_2bit/clk /counter_2bit/q /counter_2bit/count_sig 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10

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Entity:counter_2bit Architecture:rtl Date: Fri Dec 16 18:25:50 HDS 2011 Row: 1 Page: 1

C:\FPGAdv52\Libraries\S_TLC\src\@counter_4bit\rtl.vhd 12/16/11 18:28:19 -- hds header_start --- VHDL Architecture S_TLC.Counter_4bit.rtl --- Created: -by - Pharaoh.UNKNOWN (S) -at - 18:27:22 12/16/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Counter_4bit IS -- Declarations port(clk,en,rst:IN Std_Logic; q:OUT Std_Logic); END Counter_4bit ; -- hds interface_end ARCHITECTURE rtl OF Counter_4bit IS signal count_sig:unsigned(3 downto 0); BEGIN process(rst,clk) begin if(rst='1') then count_sig<=(others=>'0'); elsif(rising_edge(clk)) then if (en='1') then count_sig<=count_sig+1; end if; end if; end process; q<=count_sig(0) and count_sig(1) and count_sig(2) and count_sig(3); END rtl;

Page: 1

Simulation 4bit view signals # .signals # .signals force -freeze sim:/counter_4bit/rst 1 0 force -freeze sim:/counter_4bit/rst 0 200 force -freeze sim:/counter_4bit/en 0 0 force -freeze sim:/counter_4bit/en 1 400 force -freeze sim:/counter_4bit/clk 1 0, 0 {50 ns} -r 100 add wave sim:/counter_4bit/* run run run run run run run run run run run run run run run run run run run run run run run run run run run Page 1

/counter_4bit/clk /counter_4bit/en /counter_4bit/rst /counter_4bit/q /counter_4bit/count_sig 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101

500

1 us

1500

2 us

Entity:counter_4bit Architecture:rtl Date: Fri Dec 16 18:30:05 HDS 2011 Row: 1 Page: 1

Sequence Detector
Non-Overlapping

S_Sequence_Detector\Seq_Det_10010\struct
Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Declarations Ports: Clk : std_logic Rst : std_logic din : std_logic Seq_Ok : std_logic Diagram Signals: Project: <enter project name here>

<company name>
Title: Path: Edited: <enter diagram title here> <<-- more -->> by Pharaoh on 17 Dec 2011

<enter comments here>

Clk Rst

Clk Rst

din

din

S_Sequence_Detector Seq_Det_FSM_10010 I2

Seq_Ok

Seq_Ok

Printed by Pharaoh on 12/19/2011 at 12:35:28 PM

Page 1 of 1

S_Sequence_Detector\Seq_Det_FSM_10010\fsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Signals Status State Register Statements SIGNAL SCOPE DEFAULT RESET STATUS Seq_Ok OUT '0' COMB Process Declarations

<company name>
Title: Path: Edited: <enter diagram title here> <<-- more -->> by Pharaoh on 17 Dec 2011

Project:

<enter project name here>

<enter comments here>

s0

din = '0' 1

din = '1'

Seq_Ok <= '1';

s5

din = '1'

s1

din = '0' 2 1 din = '1'

din = '0'

din = '0' din = '1' 1

s4 1 din = '0' din = '1' 2 s3 2

s2

Printed by Pharaoh on 12/19/2011 at 12:35:56 PM

Page 1 of 1

/seq_det_fsm_10010/clk /seq_det_fsm_10010/rst

/seq_det_fsm_10010/din

/seq_det_fsm_10010/seq_ok

/seq_det_fsm_10010/current_state s0 /seq_det_fsm_10010/next_state s0 s1

s1 s2

s2 s3

s3 s4

s4 s5

s5 s1

s1 s2

s2 s3

s3 s4

s4 s5

s5 s0

s0 s1

s1 s2

s2 s1

s1

500

1 us

1500

2 us

Entity:seq_det_fsm_10010 Architecture:fsm Date: Mon Dec 19 12:49:10 HDS 2011 Row: 1 Page: 1

Sequence Detector
Overlapping

S_Sequence_Detector\Seq_Det_10010_O\struct
Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Declarations Ports: Clk : std_logic Rst : std_logic din : std_logic Seq_Ok : std_logic Diagram Signals: Project: <enter project name here>

<company name>
Title: Path: Edited: <enter diagram title here> <<-- more -->> by Pharaoh on 17 Dec 2011

<enter comments here>

Clk Rst

Clk Rst

din

din

S_Sequence_Detector Seq_Det_FSM_10010_O I3

Seq_Ok

Seq_Ok

Printed by Pharaoh on 12/19/2011 at 12:36:22 PM

Page 1 of 1

S_Sequence_Detector\Seq_Det_FSM_10010_O\fsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Signals Status State Register Statements SIGNAL SCOPE DEFAULT RESET STATUS Seq_Ok OUT '0' COMB Process Declarations

<company name>
Title: Path: Edited: <enter diagram title here> <<-- more -->> by Pharaoh on 17 Dec 2011

Project:

<enter project name here>

<enter comments here>

s0

din = '1'

Seq_Ok <= '1';

s5

din = '1'

s1

1 din = '0' 2 1 din = '0' din = '0'

din = '1' din = '0' din = '1' 1

s4 1 din = '0' din = '1' 2 s3 2

s2

Printed by Pharaoh on 12/19/2011 at 12:36:39 PM

Page 1 of 1

/seq_det_fsm_10010_o/clk /seq_det_fsm_10010_o/rst

/seq_det_fsm_10010_o/din

/seq_det_fsm_10010_o/seq_ok

/seq_det_fsm_10010_o/current_state s0 /seq_det_fsm_10010_o/next_state s0 s1

s1 s2

s2 s3

s3 s4

s4 s5

s5 s1

s1 s2

s2 s3

s3 s4

s4 s5

s5 s3

s3 s4

s4 s5

s5 s1

s1

500

1 us

1500

2 us

Entity:seq_det_fsm_10010_o Architecture:fsm Date: Mon Dec 19 12:40:35 HDS 2011 Row: 1 Page: 1

Vending Machine

S_VM\VM\struct

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

<company name>
Title: Path: Edited: <enter diagram title here> S_VM/VM/struct by Pharaoh on 21 Dec 2011

Declarations Ports: Diagram Signals: SIGNAL Clk : std_logic SIGNAL Dollar : std_logic SIGNAL Quarter_Dollar : std_logic SIGNAL Return_Request : std_logic SIGNAL Rst : std_logic <enter : std_logic project name here> SIGNAL Project: Soda SIGNAL Soda_Request : std_logic <enter comments here> SIGNAL The_Return : std_logic

Clk Rst

Dollar Quarter_Dollar

S_VM VM_FSM I0
The_Return

Soda_Request Return_Request

Soda

Printed by Pharaoh on 12/21/2011 at 11:36:14 AM

Page 1 of 1

S_VM\VM_FSM\fsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements SIGNAL SCOPE DEFAULT RESET STATUS Soda OUT '0' COMB The_Return OUT '0' COMB Process Declarations

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

<company name>
Title: Path: Edited: <enter diagram title here> S_VM/VM_FSM/fsm by Pharaoh on 21 Dec 2011

Project:

<enter project name here>

<enter comments here>

s1

Quarter_Dollar = '1'

s2

Quarter_Dollar = '1'

s3

2 1 Quarter_Dollar = '1' Soda_Request = '1' 1

Quarter_Dollar = '1' s0 s5 Soda <= '1'; 2

Dollar = '1'

s8 The_Return <= '1';

s4

Return_Request = '1'

Soda_Request = '1'

s7 Soda <= '0';

s6 Soda <= '1';

Printed by Pharaoh on 12/21/2011 at 11:41:17 AM

Page 1 of 1

VM Simulation Code - 3 Quarters force -freeze sim:/vm_fsm/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/vm_fsm/rst 1 0 force -freeze sim:/vm_fsm/rst 0 50 force -freeze sim:/vm_fsm/dollar 0 0 force -freeze sim:/vm_fsm/quarter_dollar 0 0 force -freeze sim:/vm_fsm/soda_request 0 0 force -freeze sim:/vm_fsm/return_request 0 0 force -freeze sim:/vm_fsm/quarter_dollar 1 200 force -freeze sim:/vm_fsm/quarter_dollar 0 500 force -freeze sim:/vm_fsm/soda_request 1 1200 add wave sim:/vm_fsm/* run run run run run run run run run run run run run run run run run run run run run

Page 1

/vm_fsm/clk /vm_fsm/rst /vm_fsm/dollar

/vm_fsm/quarter_dollar

/vm_fsm/return_request

/vm_fsm/soda_request

/vm_fsm/soda

/vm_fsm/the_return

/vm_fsm/current_state s0 /vm_fsm/next_state s0 s1

s1 s2

s2 s3

s3 s3 s5

s5 s0

s0

500

1 us

1500

2 us

Entity:vm_fsm Architecture:fsm Date: Wed Dec 21 12:09:48 HDS 2011 Row: 1 Page: 1

VM Simulation Code - 4 Quarters force -freeze sim:/vm_fsm/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/vm_fsm/rst 1 0 force -freeze sim:/vm_fsm/rst 0 50 force -freeze sim:/vm_fsm/dollar 0 0 force -freeze sim:/vm_fsm/quarter_dollar 0 0 force -freeze sim:/vm_fsm/soda_request 0 0 force -freeze sim:/vm_fsm/return_request 0 0 force -freeze sim:/vm_fsm/quarter_dollar 1 200 force -freeze sim:/vm_fsm/quarter_dollar 0 600 force -freeze sim:/vm_fsm/soda_request 1 1200 force -freeze sim:/vm_fsm/return_request 1 2000 add wave sim:/vm_fsm/* run run run run run run run run run run run run run run run run run run run run run

Page 1

/vm_fsm/clk /vm_fsm/rst /vm_fsm/dollar

/vm_fsm/quarter_dollar

/vm_fsm/return_request

/vm_fsm/soda_request

/vm_fsm/soda

/vm_fsm/the_return

/vm_fsm/current_state s0 /vm_fsm/next_state s0 s1

s1 s2

s2 s3

s3 s4

s4 s4 s6

s6 s7

s7 s8

s8 s0

s0

500

1 us

1500

2 us

Entity:vm_fsm Architecture:fsm Date: Wed Dec 21 11:52:56 HDS 2011 Row: 1 Page: 1

VM Simulation Code - Dollar force -freeze sim:/vm_fsm/clk 1 0, 0 {50 force -freeze sim:/vm_fsm/rst 1 0 force -freeze sim:/vm_fsm/rst 0 50 force -freeze sim:/vm_fsm/dollar 0 0 force -freeze sim:/vm_fsm/quarter_dollar force -freeze sim:/vm_fsm/soda_request 0 force -freeze sim:/vm_fsm/return_request force -freeze sim:/vm_fsm/dollar 1 200 force -freeze sim:/vm_fsm/dollar 0 300 force -freeze sim:/vm_fsm/soda_request 1 force -freeze sim:/vm_fsm/return_request add wave sim:/vm_fsm/* run run run run run run run run run run run run run run run run run run run run run

ns} -r 100

0 0 0 0 0 800 1 1600

Page 1

/vm_fsm/clk /vm_fsm/rst /vm_fsm/dollar

/vm_fsm/quarter_dollar

/vm_fsm/return_request

/vm_fsm/soda_request

/vm_fsm/soda

/vm_fsm/the_return

/vm_fsm/current_state s0 /vm_fsm/next_state s0 s4

s4 s4 s6

s6 s7

s7 s8

s8 s0

s0

500

1 us

1500

2 us

Entity:vm_fsm Architecture:fsm Date: Wed Dec 21 12:03:18 HDS 2011 Row: 1 Page: 1

Electronic Door Lock

No Interrupt

Exp\TLC\struct

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

<company name>
Title: Path: Edited: <enter diagram title here> Exp/TLC/struct by Pharaoh on 24 Dec 2011

Declarations Ports: Diagram Signals: SIGNAL Clk : std_logic SIGNAL Green : std_logic SIGNAL Red : std_logic SIGNAL Rst : std_logic SIGNAL Start : std_logic Project: SIGNAL Yellow :<enter project name here> std_logic SIGNAL finish_r : Std_Logic <enter comments here> SIGNAL finish_y : Std_Logic

Clk Rst

Green

Start finish_y finish_r

Exp TLC_FSM I2

Yellow

Red

Clk Yellow Rst

clk en rst

S_TLC Counter_2bit I0

finish_y

Clk Red Rst

clk en rst

S_TLC Counter_4bit I1

finish_r

Printed by Pharaoh on 12/29/2011 at 05:33:30 PM

Page 1 of 1

Exp\EDL_FSM\fsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements SIGNAL SCOPE DEFAULT RESET STATUS Click OUT '0' COMB Open_Door OUT '0' COMB Process Declarations

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

<company name>
Title: Path: Edited: <enter diagram title here> Exp/EDL_FSM/fsm by Pharaoh on 29 Dec 2011

Project:

<enter project name here>

<enter comments here>

s0 2 1 Key = "0011"

s1 Click <= '1'; 1 Key = "1010" 2

s5 Click <= '1';

s2 Click <= '1'; 1 Key = "0101" 2

s6 Click <= '1';

s3 Click <= '1';

s7 Click <= '1';

Key = "1011"

s4 Open_Door <= '1'; Click <= '1';

Printed by Pharaoh on 12/29/2011 at 05:35:08 PM

Page 1 of 1

/edl_fsm/clk /edl_fsm/key 0011 1010 0101 1011

/edl_fsm/rst

/edl_fsm/click

/edl_fsm/open_door

/edl_fsm/current_state s0 /edl_fsm/next_state s1

s1 s2

s2 s3

s3 s4

s4 s0

s0 s5

s5 s6

s6 s7

s7 s0

s0 s5

s5 s6

s6 s7

s7 s0

s0 s5

s5 s6

s6 s7

s7 s0

s0 s5

500

1 us

1500

2 us

Entity:edl_fsm Architecture:fsm Date: Thu Dec 29 17:30:47 HDS 2011 Row: 1 Page: 1

Simulation Code force -freeze sim:/edl_fsm/clk 1 0, force -freeze sim:/edl_fsm/rst 1 0 force -freeze sim:/edl_fsm/rst 0 50 force -freeze sim:/edl_fsm/key 0011 force -freeze sim:/edl_fsm/key 1010 force -freeze sim:/edl_fsm/key 0101 force -freeze sim:/edl_fsm/key 1011 add wave sim:/edl_fsm/* run run run run run run run run run run run run run run run run run run

0 {50 ns} -r 100 0 100 200 300

Page 1

Electronic Door Lock

With Interrupt

S_EDL\EDL\struct

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

<company name>
Title: Path: Edited: <enter diagram title here> S_EDL/EDL/struct by Pharaoh on 24 Dec 2011

Declarations Ports: Clk : std_logic Key : std_logic_vector(3 DOWNTO 0) Rst : std_logic intr : std_logic door_open : std_logic rdy_bsy : std_logic Project: <enter project name here> Diagram Signals: <enter comments here>

intr

intr

Key(3:0)

Key : (3:0)

Clk

Clk

S_EDL EDL_FSM I0

door_open

door_open

rdy_bsy

rdy_bsy

Rst

Rst

Printed by Pharaoh on 12/29/2011 at 05:03:50 PM

Page 1 of 1

S_EDL\EDL_FSM\fsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Signals Status State Register Statements SIGNAL SCOPE DEFAULT RESET STATUS door_open OUT '0' COMB rdy_bsy OUT '0' COMB Process Declarations

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

<company name>
Title: Path: Edited: <enter diagram title here> S_EDL/EDL_FSM/fsm by Pharaoh on 24 Dec 2011

Project:

<enter project name here>

<enter comments here>

s0 door_open <= '0'; rdy_bsy <= '0';

2 intr = '1' intr = '1'

intr = '1' AND Key = "1101"

s5 door_open <= '0'; rdy_bsy <= '1';

intr = '1'

s1 door_open <= '0'; rdy_bsy <= '1';

intr = '1' 2 intr = '1'

intr = '1' AND Key = "0011"

s6 door_open <= '0'; rdy_bsy <= '1';

s2 door_open <= '0'; rdy_bsy <= '1';

intr = '1' 2 intr = '1'

intr = '1' AND Key = "0111"

s7 door_open <= '0'; rdy_bsy <= '1';

s3 door_open <= '0'; rdy_bsy <= '1';

intr = '1' AND Key = "1001"

s4 door_open <= '1'; rdy_bsy <= '1';

Printed by Pharaoh on 12/29/2011 at 05:04:16 PM

Page 1 of 1

/edl_fsm/clk /edl_fsm/rst

/edl_fsm/key 0000

1101

0011

0111

1001

/edl_fsm/intr

/edl_fsm/door_open

/edl_fsm/rdy_bsy

/edl_fsm/current_state s0 /edl_fsm/next_state s0 s1

s1 s1 s2

s2 s2 s3

s3 s3 s4

s4 s0

s0

500

1 us

1500

2 us

Entity:edl_fsm Architecture:fsm Date: Thu Dec 29 17:42:03 HDS 2011 Row: 1 Page: 1

Simulation Code force -freeze sim:/edl_fsm/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/edl_fsm/rst 1 0 force -freeze sim:/edl_fsm/rst 0 50 force -freeze sim:/edl_fsm/key 0000 0 force -freeze sim:/edl_fsm/intr 0 0 force -freeze sim:/edl_fsm/intr 1 200 force -freeze sim:/edl_fsm/intr 1 500 force -freeze sim:/edl_fsm/intr 1 800 force -freeze sim:/edl_fsm/intr 1 1100 force -freeze sim:/edl_fsm/intr 0 300 force -freeze sim:/edl_fsm/intr 0 600 force -freeze sim:/edl_fsm/intr 0 900 force -freeze sim:/edl_fsm/intr 0 1200 force -freeze sim:/edl_fsm/key 1101 200 force -freeze sim:/edl_fsm/key 0011 500 force -freeze sim:/edl_fsm/key 0111 800 force -freeze sim:/edl_fsm/key 1001 1100 add wave sim:/edl_fsm/* run run run run run run run run run run run run run run run run run run run run Page 1

Simulation Code run run run run

Page 2

Smart Door

S_SD\SD\struct

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

<company name>
Title: Path: Edited: <enter diagram title here> S_SD/SD/struct by Pharaoh on 21 Dec 2011

Declarations Ports: Diagram Signals: SIGNAL Clk : std_logic SIGNAL Open_Door : std_logic SIGNAL Rst : std_logic SIGNAL Sensor_1 : std_logic SIGNAL Sensor_2 : std_logic <enter project name here> SIGNAL Project: close : std_logic SIGNAL <enter comments here> en : std_logic

Clk Rst Open_Door

Sensor_1 Sensor_2

Clk Rst

clk rst en

close S_SD Counter_20sec I1

close

S_SD SD_FSM I0

en

Printed by Pharaoh on 12/21/2011 at 02:59:21 PM

Page 1 of 1

S_SD\SD_FSM\fsm ['machine0']

Architecture Declarations Global Actions Concurrent Statements Process Declarations Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Signals Status State Register Statements SIGNAL SCOPE DEFAULT RESET STATUS Open_Door OUT '0' COMB en OUT '0' COMB

<company name>
Title: Path: Edited: Smart Door S_SD/SD_FSM/fsm by Pharaoh on 21 Dec 2011

Project:

<enter project name here>

<enter comments here>

s0

Sensor_1 = '1' OR Sensor_2 = '1' 2

s1 Open_Door <= '1'; en <= '1';

close = '1' Sensor_1 = '1' OR Sensor_2 = '1' 1

s2 en <= '0';

Printed by Pharaoh on 12/21/2011 at 03:05:29 PM

Page 1 of 1

Smart Door - Simulation Code add wave sim:/sd/* force -freeze sim:/sd/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/sd/rst 1 0 force -freeze sim:/sd/rst 0 50 force -freeze sim:/sd/sensor_2 0 0 force -freeze sim:/sd/sensor_1 0 0 force -freeze sim:/sd/sensor_1 1 900 force -freeze sim:/sd/sensor_1 0 1000 force -freeze sim:/sd/sensor_2 1 3900 force -freeze sim:/sd/sensor_2 0 4000 force -freeze sim:/sd/sensor_2 1 6900 force -freeze sim:/sd/sensor_2 0 7000 run run run run run run run run run run run run run run run run run run run run run run run run run Page 1

Smart Door - Simulation Code run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run run Page 2

Smart Door - Simulation Code run run run run run run run run run run run run run run run run run run run run

Page 3

C:\FPGAdv52\Libraries\S_SD\src\@counter_20sec\rtl.vhd 12/21/11 14:58:23 -- hds header_start --- VHDL Architecture S_SD.Counter_20sec.rtl --- Created: -by - Pharaoh.UNKNOWN (S) -at - 12:40:51 12/21/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Counter_20sec IS -- Declarations port(rst,clk,en: in std_logic; close: out std_logic); END Counter_20sec ; -- hds interface_end ARCHITECTURE rtl OF Counter_20sec IS signal count: unsigned(4 downto 0); BEGIN process(rst,clk) begin if(rst = '1')then count <= "00010"; close <= '0'; elsif (rising_edge(clk)) then if(en = '1') then if( count < 20 ) then count <= count + 1; close <= '0'; else count <= "00001"; close <= '1'; end if; end if; end if; end process; END rtl;

Page: 1

Suez Canal

Basma\Suez\struct

Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

Declarations Ports: Diagram Signals: SIGNAL Clk SIGNAL Rst SIGNAL Start_4 SIGNAL Start_8 SIGNAL alarm SIGNAL finish_4 SIGNAL finish_8 SIGNAL gate_closed SIGNAL green SIGNAL red SIGNAL sensor_A SIGNAL sensor_B SIGNAL sensor_C SIGNAL yellow Project:

: : : : : : : : : : : : : :

Std_Logic Std_Logic Std_Logic Std_Logic Std_Logic Std_Logic Std_Logic Std_Logic Std_Logic Std_Logic std_logic std_logic std_logic Std_Logic

<company name>
Title: Path: Edited: <enter diagram title here> Basma/Suez/struct by Pharaoh on 29 Dec 2011

<enter project name here>

<enter comments here>

Clk

Rst

sensor_A

alarm gate_closed

sensor_B

sensor_C

green yellow

Basma suez_fsm I0
finish_4 finish_8

red

Start_4

Start_8

Clk Start_4 Rst

clk en rst

Clk

finish_4 Start_8 Rst

clk en rst

Basma counter_2bits I1

Basma counter_3bits I2

finish_8

Printed by Pharaoh on 12/29/2011 at 04:42:42 PM

Page 1 of 1

Basma\suez_fsm\fsm ['machine0']
Global Actions Concurrent Statements Architecture Declarations Package List LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Signals Status SIGNAL Start_4 Start_8 alarm gate_closed green red yellow SCOPE OUT OUT OUT OUT OUT OUT OUT Title: Path: Edited: State Register Statements DEFAULT RESET STATUS '0' COMB '0' COMB '0' COMB '0' COMB '0' COMB '0' COMB <company name> '0' COMB <enter diagram title here> Basma/suez_fsm/fsm by Pharaoh on 29 Dec 2011 Process Declarations

Project:

<enter project name here>

<enter comments here>

sensor_A = '0' AND sensor_B = '0' AND sensor_C = '0'

s5 green <= '0'; yellow <= '0'; red <= '1';

s0 green <= '1'; yellow <= '0'; red <= '0';

sensor_A = '1'

s1

green <= '0'; yellow <= '1'; red <= '0'; Start_4 <= '1';

sensor_C = '1'

finish_4 = '1'

alarm <= '1'; gate_closed <= '1'; green <= '0'; yellow <= '0'; red <= '1';

s4

sensor_B = '1'

s3

finish_8 = '1'

s2

green <= '0'; yellow <= '0'; red <= '1'; Start_8 <= '1';

gate_closed <= '1'; green <= '0'; yellow <= '0'; red <= '1';

Printed by Pharaoh on 12/29/2011 at 04:43:10 PM

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Simulation Forces force -freeze sim:/suez/clk 1 0, 0 {50 ns} -r 100 force -freeze sim:/suez/rst 1 0 force -freeze sim:/suez/rst 0 50 force -freeze sim:/suez/sensor_a 0 0 force -freeze sim:/suez/sensor_b 0 0 force -freeze sim:/suez/sensor_c 0 0 force -freeze sim:/suez/sensor_a 1 200 force -freeze sim:/suez/sensor_a 0 300 force -freeze sim:/suez/sensor_b 1 1600 force -freeze sim:/suez/sensor_b 0 1700 force -freeze sim:/suez/sensor_c 1 4000 force -freeze sim:/suez/sensor_c 0 4100 add wave sim:/suez/* run run run run run run run run run run run run run run run run run run run run run run run run run Page 1

Simulation Forces run run run run run run run run run run run run run run run run run run run run run run run

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/suez/clk /suez/rst

/suez/green

/suez/yellow

/suez/red

/suez/sensor_a /suez/sensor_b /suez/sensor_c /suez/start_4 /suez/finish_4 /suez/start_8 /suez/finish_8

/suez/gate_closed

/suez/alarm

500

1 us

1500

2 us

2500

3 us

3500

4 us

4500

Entity:suez Architecture:struct Date: Thu Dec 29 16:44:34 HDS 2011 Row: 1 Page: 1

C:\FPGAdv52\Libraries\Basma\src\counter_2bits\untitled.vhd 12/29/11 14:06:48 -- hds header_start --- VHDL Architecture Basma.counter_2bits.untitled --- Created: -by - Pharaoh.UNKNOWN (S) -at - 13:55:37 12/29/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY counter_2bits IS -- Declarations PORT (rst, en, clk: IN Std_Logic; q : OUT Std_Logic); END counter_2bits ; -- hds interface_end ARCHITECTURE untitled OF counter_2bits IS Signal count_sig: unsigned (1 downto 0); BEGIN Process(rst,clk) Begin if (rst ='1') then count_sig <= (Others => '0'); elsif (rising_edge(clk)) then if (en = '1') then count_sig <= count_sig +1; end if; end if; end process; q <= count_sig(0) and count_sig(1); END untitled;

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C:\FPGAdv52\Libraries\Basma\src\counter_3bits\untitled.vhd 12/29/11 14:08:12 -- hds header_start --- VHDL Architecture Basma.counter_3bits.untitled --- Created: -by - Pharaoh.UNKNOWN (S) -at - 14:06:22 12/29/2011 --- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170) --- hds header_end LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY counter_3bits IS -- Declarations PORT (rst, en, clk: IN Std_Logic; q : OUT Std_Logic); END counter_3bits ; -- hds interface_end ARCHITECTURE untitled OF counter_3bits IS Signal count_sig: unsigned (2 downto 0); BEGIN Process(rst,clk) Begin if (rst ='1') then count_sig <= (Others => '0'); elsif (rising_edge(clk)) then if (en = '1') then count_sig <= count_sig +1; end if; end if; end process; q <= count_sig(0) and count_sig(1) and count_sig(2); END untitled;

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