A summary of the questions-0S2

-----------------------------------------------------------------( (CH-5))------------------------------------------------------------------------------Q1/P4| Definition of multiprogramming ? Computer multiprogramming is the allocation of a computer system and its resources to more than one concurrent application, job or user. Q2/P7| What is CPU Scheduler? Selects from among the processes in memory that are ready to execute, and allocates the CPU to one of them. Q3/P7| What is nonpreemptive and preemptive? Preemptive:

2. Switches from running to ready state. 3. Switches from waiting to ready.

Nonpreemptive.

1. Switches from running to waiting state 2. Switches from running to ready state 3. Switches from waiting to ready 4. Terminates

1. Switches from running to waiting state. 4. Terminates.

Q4/P8| Definition of Dispatcher? Dispatcher module gives control of the CPU to the process selected by the short-term scheduler. Q5/P8| Definition of Dispatch latency ? time it takes for the dispatcher to stop one process and start another running. Q6/P9|

CPU utilization keep the CPU as busy as possible Throughput # of processes that complete their execution per time unit Turnaround time amount of time to execute a particular process Waiting time amount of time a process has been waiting in the ready queue Response time amount of time it takes from when a request was submitted until the first response is produced, not output (for time-sharing environment)

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Q10/P11|

First-Come, First-Served (FCFS) Scheduling

At time 0

Q11/P14|

Example of SJF

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Ex\Q

Priority Scheduling

Q12/P20| Example of RR with Time Quantum = 4

--------------------------------------------------------))CH8))-----------------------------------------------------------------------------Q13/P3|

Completed
Main memory and registers are only storage CPU can access directly.

Q14/P13|

Completed
Cache sits between main memory and CPU registers

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Q14/P7|

What is the problem when using addresses in programs physical addresses .give example

When instruction jump 12 will be executed it will go to location 12 in memory add belongs to program 1

Q15/P9|

Explain Binding of Instructions and Data to Memory?

Address binding of instructions and data to (physical) memory addresses can happen at three different stages Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes Load time: Must generate relocatable code if memory location is not known at compile time Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers)

Q16/P12|

Define Logical and Physical Address Space

Logical address generated by the CPU; also referred to as virtual address Physical address address seen by the memory unit

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Q17/P13| Explain the mapping from logical to physical adders using base and limit register ?

Q18/P14|

Memory-Management Unit (MMU)

Hardware device that maps logical (virtual) to physical address

Q19/P18|

What is Swapping?
A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution.

Q20/P22| Hardware Support for Relocation and Limit Registers (MMU)

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Q21/P24|
Definition:

First-fit: Allocate the first hole that is big enough Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size Produces the smallest leftover hole Worst-fit: Allocate the largest hole; must also search entire list Produces the largest leftover hole

Q22/P25|
Definition:
External Fragmentation total memory space exists to satisfy a request, but it is not contiguous. Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition (allocation), but not being used