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Chapter 1

1.1 Brief Introduction
Addition is one of the fundamental arithmetic operations. It is used extensively in many VLSI
systems such as application-specific DSP architectures and microprocessors. In addition to its
main task, which is adding two binary numbers, it is the nucleus of many other useful operations
such as subtraction, multiplication, division, address calculation, etc. In most of these systems
the adder is part of the critical path that determines the overall performance of the system. That is
why enhancing the performance of the full-adder cell is a significant goal. Recently, building
low-power VLSI systems has emerged as highly in demand because of the fast growing
technologies in mobile communication and computation. The battery technology doesnt
advance at the same rate as the microelectronics technology. There is a limited amount of power
available for the mobile systems. So designers are faced with more constraints: high speed, high
throughput, small silicon area, and at the same time, low-power consumption. So building low-
power, high-performance adder cells is of great interest. In this work, a structured approach for
analysing the adder design is introduced.
1.2 Thesis Objective
Based up on above discussion the pre dissertation has the following objectives:
To design and simulate different types of adders.
The performance evaluation of adder will be done in terms of speed and power
1.3 Organization of pre dissertation report
The 2
chapter contains literature survey. This chapter includes the study of different full adder
based papers. The 3
chapter includes definition of static, pass transistor, dynamic CMOS
circuits and their advantages and disadvantages are studied. The 4
chapter explains the concept
D3L and transistor sizing. The 5
chapter contains the simulation results and calculations.
1.4 Methodology
This pre dissertation work includes the study of different types of CMOS adders. Main focus is
given to two adders. One of adder is based up on dynamic logic and the other is based up on D3L
logic. These two adders are designed and simulated by using Design Architect tool of Mentor
Graphics based on 180nm CMOS technology.

Chapter 2
Digital adders are crucial components in any digital system because they can significantly
influence the overall achievable performances. For this reason, high speed adders are highly
desirable. Speed performances of an adder can be improved optimizing both the top-level
architecture and the circuit implementation. The performance of a full adder circuit depends to a
great extent on the type of design style used for implementation as well as the logic function
realized using the particular design style. For instance, a static CMOS implementation allows
circuits to achieve a reasonable power delay product (PDP) with high noise margins, regular
layout and relatively higher tolerance to process variations. The static logic is a logic in which
the functioning of the circuit is not synchronized by a global signal, namely the clock of the
circuit. The output is solely function of the input of the circuit, and it is asynchronous with
respect to them. The timing of the circuit is defined exclusively by its internal delay. In contrast,
the dynamic logic is a logic in which the output is synchronized by a global signal, viz. the clock.
The output is, then, function of both of the inputs of the circuit and of the clock signal. The
timing of the circuit is defined both by its internal delay and by the timing of the clock. After a
lot of research the domino logic circuits are replaced by D3L (Data Driven Dynamic Logic) .This
logic has replace the clock with the data. The things will be clearer from the brief literature

2.1 Low-Power CMOS Digital Design:-This paper was presented as IEEE journal in the year
1994.The author of this paper was motivated by emerging battery-operated applications that
demand intensive computation in portable environments, techniques are investigated which
reduce power consumption in CMOS digital circuits while maintaining computational
throughput. Techniques for low-power operation are shown which use the lowest possible supply
voltage coupled with architectural, logic style, circuit, and technology optimizations. This paper
compared static CMOS full adder and pass transistor based full adder. The pass-gate design uses
only a single transmission NMOS gate, instead of a full complementary pass gate to reduce node
capacitance. Pass-gate logic is attractive as fewer transistors are required to implement important
logic functions, such as XOR'S which only require two pass transistors. But the pass transistor
has two basic problems. First, the threshold drop across the single-channel pass transistors results
in reduced current drive and hence slower operation at reduced supply voltages. Second, since
the "high" input voltage level at the regenerative inverters is not V
, the PMOS device in the
inverter is not fully turned off, and hence direct-path static power dissipation could be
significant. To solve these problems, reduction of the threshold voltage has proven effective,
although if taken too far will incur a cost in dissipation due to subthreshold leakage and reduced
noise margins. However apart from these limitations, the power dissipation for a pass-gate adder
with zero-threshold pass transistors at a supply voltage of 4 V was reported to be 30% lower
than a conventional static design.

2.2 ASIC Implementation of 1 Bit Full Adder: - This paper was presented in the First
International Conference on Emerging Trends in Engineering and Technology in the year 1998.
In this paper the author presented study of 1-bit full adder circuit. The author focussed on certain
parameter such as power and delay. The conventional adder is implemented with 28 Transistors
in CMOS technology. Conventional adder circuits do not function well below one V supply. Due
to large number of active devices per chip require highly refined and sophisticated CMOS logic
structures. CMOS design techniques suffers from the drawback of higher penalty on silicon area,
less densely packed, low speed and high power dissipation.

2.3 A high Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates:-
The paper proposed the novel design of a 3T XOR gate combining complementary CMOS with
pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates
and a significant improvement in silicon area and power-delay
product has been obtained. An eight transistor full adder has been designed using the proposed
three-transistor XOR gate and its performance has been investigated using 0.15m and 0.35 m
technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder
shows a significant improvement in silicon area and power delay product. The whole simulation
has been carried out using HSPICE. The early designs of XOR gates were based on either eight
transistors or six transistors that are conventionally used in most designs. Over the last decade,
considerable emphasis has been laid on the design of four-transistor XOR gate. Wang, Fang and
Feng proposed novel XOR architectures of 4T XOR gate. However, the proposed XOR gates
consumed considerable silicon area for their optimum performance and the power delay product
is also large. Wang, Fang and Feng also proposed another XOR gate and further studied by
Shams, Darwish and Bayoumi. With a view of further optimization of performance of XOR
gates in terms of silicon area and power delay product, considerable emphasis has been given in
the present work on the design of three transistor XOR gates. By using 3T XOR gate the
transistor count of full get reduced to 16T from 20T as mentioned in previous papers. The noise
margin of the proposed XOR gate has been studied and found to have quite acceptable. The
proposed XOR gate also has a much less delay and hence much less power delay product than
its peer designs.
2.4 Dynamic CMOS Full Adder:- In this paper author presented in the year 2002. In this
paper study of dynamic structure using 1-bit full adder circuit is done. A common clock is used
for both carry output and SUM output. This type of logic structure is best suited for low power
circuit design. The problem with dynamic CMOS circuit is that it suffers from the problem of
charge sharing and cascading of dynamic CMOS circuits. To avoid this problem a buffer is
added at the SUM output to restore the logic levels the size of buffer should be minimum as of
the other transistors. The speed of the dynamic full adder is greater than conventional CMOS
adder and pass transistor full adder.
2.5 A Novel Mixed Mode Current and Dynamic Voltage Full Adder:- In this paper the
dynamic voltage CMOS 1-bit full adder cell is presented in the year 2008. In this new design,
high speed is obtained. The results are validated through HSPICE Simulation with 0.18 um and
1.8v, Vdd. The advantages of dynamic logic consist of decrease in chip area as compared with
CMOS static logic, less parasite capacitor, high speed in each gate and consequently speed up of
the whole circuit .
2.6 Designing High-Speed Adders in Power-Constrained Environments:-
This paper was presented in the year 2009. This paper proposed D3L.Data-driven dynamic logic
(D3L) is very efficient when low-power constraints are mandatory. Unfortunately, this advantage
is typically obtained at the expense of speed performances. This paper presents a novel technique
to realize D3L parallel prefix tree adders without significantly compromising speed performance.
When applied to a full adder realized with 90-nm complementary metaloxidesemiconductor
(CMOS) technology, the proposed technique leads to an energydelay product that is 29% and
21% lower than its standard domino logic and conventional D3L counterparts, respectively. It
also shows a worst case delay that is 10% lower than that of the D3L approach and only 5%
higher than that of the conventional.
2.7 New Performance/Power/Area Efficient, Reliable Full Adder Design:-
The design brings together the speed advantages of dynamic design with the reliability and
robustness of static CMOS design. The proposed adder is found to perform up to 2 times as fast
as competing designs, while providing second highest noise margins amongst all the adders. The
circuit is found to be one of the most reliable when included in building bigger circuits. The
performance of the proposed adder was compared against Standard CMOS, Domino, pure D3L
and the highly popular 10 transistor based low power, high performance adder. We rate each of
these circuits on the basis of speed, power and area for an initial comparison .All the adder
circuits were custom built in IBMs 0.13 micron CMOS process. The circuits were then
simulated using Spectre simulator from Cadence. All the circuits were tested for all possible
combinations of input signals A,B and Cin. After the initial simulations for power and delay, the
circuits were tested for noise margins. The input signals are swept from 0V to 1.2V using a
parametric analysis to calculate VIH and VIL.

Chapter 3
3.1 CONVENTIONAL STATIC LOGIC: - It is the logic normally referred when speaking of
static logic. A static circuit has the same number of NMOS and PMOS transistors, but the n and
p branches are respectively one the dual of the other. As in figure 1.1, this represents a static
NAND gate. The gate has high output when both the inputs are low.

Figure 3.1 Static NAND Gate
As in static logic the number of NMOS and PMOS are the same therefore this type of circuits
results in larger area as well as more static power dissipation. Now take an example of static
CMOS full adder. The full adder as shown in figure takes three input A, B, C
and produces two
outputs Sum and Carry. The working of static full adder will be clearer from the truth table1.
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The SUM and CARRY of full adder is calculated by using following equations:-


The equation (1) and (2) are the full adder equations for SUM and CARRY. The SUM is high
when odd numbers of inputs are high. And the CARRY is high when two or more than two input
are high. The above equations can be written as


A B C(3)
The equation (3) and (4) can be used to implement a full adder. This gives a regular structure of
full adder. As we know that in the static full adder every pull down network has its compliment
in the pull up network. So this results in increase in transistor count and hence increase in area as
well power consumption. Drawback of CMOS is the relatively weak output driving capability
due to series transistors in the output stage. This, however, can be corrected by additional output
buffers/inverters which are inherent in other logic styles. The Static CMOS full adder is shown
below, in figure 1.2.

Figure 3.2 Static CMOS Full Adder
3.1.1 Disadvantages Of Static Cmos Full Adder
PMOS is always conducting and leads the output node to the high state. When the
NMOS branch also conducts, then the output discharges, if the ratio among the NMOS
and PMOS transistor is well designed. This logic is cited here only for historical reason,
since it is not so fast, it dissipates static power in a steady state (when the output is in the
low state) and it is sensible to noise.
Most of the disadvantages of using static CMOS, however, are associated with the use of
PMOS because hole mobility are significantly slower than electron mobility. PMOS
devices must be much larger than NMOS devices for the two to have the same ability to
transport a fixed amount of charge during a fixed time interval. The larger surface area
needed to form a PMOS device than an NMOS device is not only a detriment to the
overall chip size, but also increases the capacitance associated to the PMOS device. The
larger capacitance and slower carrier mobility associated with PMOS cause results in a
greater time delay for the PMOS to charge up the capacitor associated with the next logic
stage. This increased time delay becomes a bottleneck when trying to design faster
circuits. In standard CMOS logic, one PMOS device will always compliment an NMOS
device. Altering this logic so that fewer PMOS devices are needed will vastly improve
circuit performance.
3.2 PASS-LOGIC: The pass-logic is relatively new logic, and, for many digital designs,
Implementation in pass-transistor logic (PTL) has been shown to be superior in terms of area,
timing, and power characteristics to static CMOS.As an example see figure 1.2

Figure 3.3 Pass XOR Gate

The pass-gate design uses only a single transmission NMOS gate, instead of a full
complementary pass gate to reduce node capacitance. Pass-gate logic is attractive as fewer
transistors are required to implement important logic functions, such as XOR'S which only
require two pass transistors. Pass transistor based designs consume very little power and area, but
suffer from poor performance and reliability. When an NMOS and PMOS is used alone act as
imperfect switch. An NMOS is perfect switch when passing a 0 and thus we say it passes strong
0.However NMOS transistor is imperfect in passing strong 1.The high voltage level is somewhat
less then V

supply voltage).we can say that it passes a degraded or weak 1.A PMOS again
has the opposite behaviour, passing strong 1 but degrades 0.The pass transistor based on the full
NMOS have fast fall time while the full adder based up on PMOS have fast rise time. But if the
width of PMOS is increased the rise time decreases but the fall time increases. The basic
difference of pass-transistor logic compared to the CMOS logic style is that the source side of the
logic transistor networks is connected to some input signals instead of the power lines. The
advantage is that one pass-transistor network (either NMOS or PMOS) is sufficient to perform
the logic operation, which results in a smaller number of transistors and smaller input loads,
especially when NMOS networks are used.

3.2.1 Disadvantage Of Pass Transistor Based Full Adder
There is threshold voltage drop through the NMOS transistors while passing logic
1.This makes swing (or level) restoration at the gate outputs necessary in order to
avoid static currents at the subsequent logic gates. Adjusting the threshold voltages, as a
solution at the process technology level is usually not feasible for other reasons. In order
to decouple gate inputs and outputs and to provide acceptable output driving capabilities,
inverters are usually attached to the gate outputs. Because the MOS networks are
connected to variable gate inputs rather than constant power lines, only one signal path
through each network must be active at a time in order to avoid shorts between inputs.


Figure 3.4 Pass transistor full adder

3.3 DYNAMIC LOGIC FAMILIES The principal dynamic families have a characteristic in
common: every dynamic logic needs of a pre-charge (or pre-discharge) transistor to lead to a
known state some pre-charged nodes. This is done during the working phase known as pre-
charge phase or memory phase; during another working phase, the evaluation phase the output
has a stable value. This brief introduction is limited to systems that have a single global clock, or
one phase, intending here the word phase as synonym of clock, and not as above as a synonym of
working period. There are systems that have two, or even four phase, but they are not introduced
here. The basic functioning, however, remains the same.
When the clock is low, the NMOS device is cutoff while the PMOS is turned ON. This has the
effect of disconnecting the output node from ground while simultaneously connecting the node
to VDD. Since the input to the next stage is charged through the PMOS transistor when the clock
is low, this phase of the clock is known as the precharge phase. When clock is high however,
the PMOS is cutoff and the bottom NMOS is turned ON, thereby disconnecting the output node
from VDD and providing a possible pull-down path to ground through the bottom NMOS
transistor. This part of the clock cycle is known as the evaluation phase, and so the bottom
NMOS is called the evaluation NMOS. When the clock is in the evaluation phase, the output
node will either be maintained at its previous logic level or discharged to GND.

Figure 3.5 Basic Dynamic CMOS circuit
In other words, the output node may be selectively discharged through the NMOS logic structure
depending upon whether or not a path to GND is formed due to inputs of the NMOS logic block.
If a path to ground is not formed during the evaluation phase, the output node will maintain its
previous voltage level since no path exists from the output to VDD or GND for the charge to
flow away.
3.3.1 Footed Dynamic Circuit
If the input A is high during precharge ,contention will take place because both the PMOS and
NMOS transistors will be ON. When the input cannot be gauranteed to be zero during the
precharge ,an extra clocked evaluated transistor can be added to the bottom of nmos stack to
avoid contention. The extra transistor is called foot .
Due to the fact that we have removed contention the logic effort get improved footed transistor
have higher logical effort then unfooted.

Figure 3.6 Footed dynamic circuit

3.3.2 Advantages Of Dynamic Logic Full Adder
No static power dissipation
The dynamic circuits are not having any power dissipation when there is no circuit activity i.e.
there is no change in inputs occurs. The dynamic circuit dissipates power when the inputs are
active i.e. when the input switches from one state to another.
Higher speed
Dynamic logic is faster than the normal logic. It uses only fast N transistors that is it use more
no. of nmos than pmos but in static circuits more no of PMOS are used to represent a logic. A
pmos is slower than nmos as the mobility of holes in PMOS is slower than the mobility of
electrons in nmos. So dynamic are circuits faster than static. The example is shown in figure
3.3 and 3.4.

Figure 3.7 Static NAND Figure 3.8 Dynamic NAND

Low power requirement
A static circuit uses more no. of transistor than dynamic for e.g. static latch require 66
transistors and a dynamic latch requires only 36 transistors. Reducing the no. of transistor not
only allows the overall device to be significantly smaller but also reduces power requirement
of a system.
One requirement for the dynamic logic circuit is that the inputs must be monotonically rising in
the evaluation phase in order to compute correct function.

Figure 3.9 Monotonicity in dynamic circuits
Unfortunately the output of a dynamic gate begins HIGH and monotonically falls LOW during
evaluation. This monotonically falling output is not suitable input to second gate. So dynamic
gates sharing same clock cannot be directly connected. So a solution to overcome this problem is
required. In the next chapter the solution to overcome monotonicity is discussed in details.
The monotonicity problem can be solved by placing a static CMOS inverter between dynamic
gates as shown below in figure 3.7. This converts the monotonically falling output in to
monotonically rising signal suitable for the next gate. The dynamic static pair together is called
DOMINO GATE because precharge resembles setting up a chain of dominos tipping over, each
triggering the next. A single clock can be used to precharge and evaluate all the logic gates
within the chain. The dynamic output is monotonically falling during evaluation, so the static
inverter output is monotonically rising.

Figure 3.10 Two dynamic NAND gates sharing same clock
The dynamic-static combination is known as a domino gate. This is analogous to a chain of
dominoes - the precharge represents setting up of dominoes and the evaluation represents their
sequential triggering. No doubt, the domino circuit has removed the problem of monotonicity but
it further has certain disadvantages. The problems associated with domino are non-inverting
output and the charge sharing problem. As it is clear that by placing a inverter solves the problem
of monotonicity. Therefore we are getting correct output Y. This will be clear from the figure

Figure 3.11 Output waveforms of two dynamic NAND gates sharing same clock
3.3.1 Properties of Domino Logic
A single clock can be used to precharge/evaluate each stage in a chain
Precharge occurs in parallel, but evaluation occurs sequentially
The static inverter can in general be replaced by a static gate
Unlike static CMOS gates, domino gates are inherently non-inverting
The gate is capable of very high speed.

When clock is in the precharge phase PMOS is On whereas pull down NMOS is Off, output is
high (V
) at the dynamic node , therefore in the precharge phase whatever the inputs are , the
output always remain high at the dynamic node and final output is low after passing through
inverter. In the evaluation phase clock goes low, therefore the pull up PMOS is off and pull
down NMOS is On. The output now is evaluated based up on the status of inputs.


Figure 3.12: Dynamic Full Adder
3.3.2 Disadvantages of domino logic circuits
Non-inverting output The domino circuits produce only the non -inverting output
however certain logic synthesis operations require inverting as well as non -inverting
operation in the same circuit. So there is a need of some logic with inverting as well as
non-inverting function.
Charge sharing
Charge sharing is an undesirable signal integrity phenomenon observed most commonly in the
domino logic family of digital circuits. The charge sharing problem occurs when the charge
which is stored at the output node in the phase is shared among the output or junction
capacitances of transistors which are in the evaluation phase. Charge sharing may degrade the
output voltage level or even cause erroneous output value.
Clock overloading
In the domino logic circuits clock is associated with every PMOS, therefore in case of large or
cascading domino logic circuits overloading occurs. So more the no. of PMOS transistor more
will be the clocks associated and hence more is the power dissipation.

3.5 KEEPER The dynamic circuits also suffer from charge leakage on the dynamic node. If the
dynamic node is prechaged high and then left floating, the voltage on the dynamic node will drift
over the time due to subthreshold, gate, and, junction leakage. This problem is analogous to the
leakage in dynamic RAM. Moreover the dynamic circuits have poor noise margins. If the input
rises above V
while the gate is in evaluation phase, the input transistor till turn ON weakly and
incorrectly discharge the output. Both leakage and noise margin problem can be reduced by
adding a keeper. The keeper is a weak that holds the output at the correct level when it would
otherwise float. When the dynamic node X is high and the output Y is low and keeper is ON to
prevent X from floating. When X fall, the keeper initially opposes the transistor so it must be
weaker than the pull down network. Eventually Y rises turning the keeper OFF and thus avoiding
static power dissipation.

Figure 3.13 Dynamic Nand gate with Keeper
The keeper must be stong enough to compentiate for any type of leakage drawnwhen the output
is floating and the pull down stack is OFF. Strong keeper also improves the noise margin
because when the input is slighly above V
the keeper can supply enough current to hold the
dynamic circuit. The keeper width should be carefully decided because too strong keeper may
create contention with the pulll down network and too weak may not be useful to hold the output
node to its correct value. The benefit of using keeper will be more clear from the following
output wave forms of a dynamic full adder.

The second waveform is the sum waveform without keeper .This waveform shows unwanted
trasition in the output which is undesirable because if we are cascading circuits then it will in
wrong output.

Figure 3.14 Output waveform full adders SUM with and without KEEPER
So by placing a keeper transistor will result in desired output . As is clear from first waveform.

Chapter 4
From the above study we come two know that no doubt the domino, dual rail and split path
dynamic circuits are energy efficient and fast logic but these circuits uses of global clock .The
clock distribution network dissipated 20 to 45% of overall consumed power. Moreover the in
dynamic domino logic the precharge phase occurs simultaneously by synchronizing all the gates
with the same clock signal. Thus causing precharge phase to be slower. But for high speed
performances precharge path need not to be slower than the evaluation path. Another
disadvantage of clock driven dynamic circuits is the presence of footed transistor which
increases logic evaluation time. So it is found that there is a great need of replacement of clock
and footed transistor. There is a logic which throws away the footed transistor and replaces the
clock with data, called data driven dynamic logic (D3L).

Figure 4.1: data driven dynamic logic

In this section, we describe D3L design concept. In creation of conventional dynamic logic, a set
of conditions is imposed on dynamic blocks. These conditions are arranged such that the logic
transistors stay in off state during the precharge time. This condition is necessary for correct
operation at the beginning of the evaluation phase and prohibits the output node from accidental
discharge. In D3L, we use these existing conditions to find a replacement for the clock signal.
For example, consider a 2-input AND gate in Domino logic, implemented as shown in Fig.3h.
noted in this figure, both of the inputs A and B are held at a low level in the precharge phase.
Awareness of this usual restriction enables us to eliminate the clock signal as shown in Fig.3g.

4.1.1 Design rules of D3L
y The logic transistors stay in off state during the precharge time .This condition is
necessary for correct operation at the beginning of the evaluation phase and prohibits the
output node from accidental discharge.

Figure 4.2: D3L (design rule related)

y In general, for D3L designs, when we have a function F in fig3i in the sum-of-products
form F

, then the minimum Pi (the Pi with a minimum number of literals) is

selected. Thus the clock is now replaced with the minimum numbers of literals.

4.1.2 Advantages of D3L
y A decrease of the power consumption owing to the elimination of the clock distribution
network and a decrease of the evaluation path delay owing to the elimination of the
clocked NMOS transistor.
y Unlike dynamic domino logic where the pre-charge phase occurs simultaneously by
synchronizing all the gates with the same clock signal, the pre-charge of D3L circuits
takes place through a propagation path along the PUNs of all the cascaded gates. That is
.the most frequent scenario since a lot of digital circuits, that is arithmetic circuit such as
adders and multipliers, are composed of a cascade of combinational stages where all the
possible pre-charge inputs of a stage are the outputs of the previous one. There are some
kinds of circuits where, due to their particular topology, all the gates can have the same
global pre-charge inputs and the pre-charge phase can take place synchronously. In order
to keep high-speed performances, the precharge path needs to be not slower than the
evaluation path by opportunely increasing the PMOS transistors size of the PUNs.
However, in this way, the load capacitance of the pre-charge inputs increases as well as
the gate dynamic energy consumption thus the energydelay product (EDP)
improvements offered by D3L gates are limited.

4.1.3 Disadvantages of D3L
y The main drawback of the D3L implementation (take example of XOR gate) is the
presence of the two series-connected PMOS transistors that have to be sufficiently wide
to make the pre-charge phase fast enough. Wide transistors make the input capacitances
large, which in turn increase the evaluation delay and the dynamic energy consumption.

y The keeper in D3L has a negative impact on dynamic energy consumption and speed
performances. In fact, during a switching of the gate, the keeper generates a DC
contention with the PDN causing short current energy dissipation. Moreover, the
discharging (charging) of the dynamic node is slowed, increasing the gate delay. The
dynamic energy overhead and speed degradation are directly proportional to the width of
the keeper.


Fig 4.4: D3L based Full adder

Transistor size optimization is one method to reduce the power dissipation of CMOS VLSI
circuits. Optimization of VLSI circuits relies heavily on efficient implementation of arithmetic
operations considering signal delay, power consumption, and chip area. Such important design
considerations and trade-offs lead to a general approach towards transistor sizing that will prove
to be extremely useful. In fact, transistor sizing, that is, the operation of enlarging or reducing the
channel width of transistors, is a powerful and effective performance optimization tool in the
hands of the designer. Although VLSI circuits can be optimized in a number of ways, such as
circuit style selection, structural optimizations, and transistor sizing, various reasons exist as to
why transistor sizing is an important issue. First of all, the power dissipation is a strong function
of transistor sizing which affects physical capacitance. Sources of power consumption such as
glitches and short-circuit currents can be minimized by careful circuit design and transistor
sizing. Second, transistor sizing affects not only the resistance of devices and time constant but
also propagation delay of the gate due to the parasitic capacitors. Third, careful transistor sizing
is necessary to maintain sufficient noise margins. Even more important is the observation that
transistor sizing becomes critical in ensuring proper functionality of a circuit. For all the above
reasons, transistor sizing is an essential means of implementing high-performance circuits
Furthermore, with the continued scaling of technology and reduced transistor sizes, the
behaviour and performance of a circuit could not be investigated without transistor sizing. From
simulation results, it has been noticed that a small change in the transistor size for a given
technology leads to a remarkable change in the characteristics of a circuit. Therefore, using an
appropriate transistor sizing method is necessary for a circuit prior to measuring its parameters.
Sizing of the transistors for this module is done in an iterative manner by the following steps.
Set all the transistors to the minimum size.
Simulate the circuit with all possible input-pattern-to input-pattern transitions.
Figure the transition with the highest delay and mark the transistors that are involved.
Size one of the transistors in this critical path.
Repeat Steps 2, 3, and 4 until the power-delay product for the cell continues to increase.
Record the transistor sizes corresponding to the minimum power-delay product.
This methodology guarantees that only the right transistors (the ones in the critical path) are
sized, and in a proper way. No oversizing or under sizing will be incurred, which makes it
optimal for power-delay product performance. Although, this is a lengthy process, it is
guaranteed to give excellent transistor sizing. One practical formulation that recognizes a
designers objective to achieve the best performance at a given time period can be stated as
Minimize Power (w)
Subject to Delay (w) Tspec,
Area Aspec,
Each Gate Size Minimize,
Where both Power and Delay parameters are functions of the transistor size, w R
, and n
represents the number of transistors in a circuit. Tspec and Aspec are, respectively, the
constraints on the circuit delay and area, and Minimize is the minimum transistor size allowed by
the technology.

Chapter 5
In this section we are going to first describe about the tool used that is known as DESIGN
ARCHITECT and then further will see the output waveforms and then discuss the results.
Design Architect tool is a product of MENTOR GRAPHICS. Mentor Graphics is a
technology leader in electronic design automation (EDA), providing software and hardware
design solutions that enable companies to develop better electronic products faster and more
cost-effectively. The company offers innovative products and solutions that help engineers
overcome the design challenges they face in the increasingly complex worlds of board and chip
design. Mentor Graphics has the broadest industry portfolio of best-in-class products and is the
only EDA Company with an embedded software solution [16]. The Design Architect tool
provides the most comprehensive technology available for Schematic capture and hierarchical
design. It includes schematic capture, symbol creation and design viewpoint generation as well
as library data management.
Design Architect uses ELDO, a simulator. Eldo includes the most advanced simulation
technology and provides extensive simulation capabilities. Its advanced analysis features include
transient noise, DC mismatch, sensitivity, aging analysis, library encryption and licensing
capabilities, optimization, distributed computing, multi-threading, RC reduction, pole-zero,
enhanced Monte-Carlo analysis, S-parameters, S-domain and Z-domain generalized transfer
functions. Eldo's extensive device model libraries include all the latest transistor models. It is the
simulator of choice for CPU-intensive applications such as digital cell characterization. Eldo's
capabilities can be further extended with VerilogA analog behavioral modeling, advanced RF
analysis with Eldo RF.
After simulating the design one can easily view the logs. The logs contain various useful
parameters like threshold voltage, channel length modulation coefficient and body effect
coefficient and many more. So, one can easily view different parameters from ASCII files.

Figure 5.1 Schematic of Dynamic full adder
The schematic of adder is shown above, consists of carry module and sum module. This is the
schematic of dynamic full adder. The full adder is having a clock which is changing continuously
from zero to one.


Figure 5.2 Output waveform of dynamic full adder
The schematic shows that the when the clock is in precharge phase(Low) the output is always
low.But when clock is in evaluation phase(high) the output is evaluated according to the input
pattern.When input pattern 110 (A B C respectively) is given as input we are getting SUM equal
to zero and CARRY equal to 1.


Figure 5.3 Schematic of D3L based full adder
This is the schematic D3L full adder the circuit is driven by data instead of clock .This results
in low power dissipation.this will be clear from the result and simulation.


Figure 5.4 Output waveform of D3L based full adder

TABLE 2: Simulation results for the Dynamic and D3L full adder
Type of
full adder
Energy of
delay (ns)
delay (ns)
(W) (W/MHz)


193.58 80.875

Chapter 6
From the results and calculation (chapter 5) we come to know that as expected the Data Driven
Dynamic Logic(D3L) full adder consumes less power as compare to Dynamic full adder.Also the
study shows that keeper has significant role in reduction charge sharing and charge leakage.
This pre dessertation work will be extented to the implementation of multiplier using dynamic
and D3L logic.Also some circuit optimization and leakage reduction techiques will be used to
achieve the low power dissipation and less area.