Training Manual

50PZ950 Pl Plasma Di l S t TV Display Smart

AG S250 AG-S250

RF Active Glasses

Advanced Single Scan Troubleshooting 50" Class F ll HD 1080 Plasma TV Cl Full 1080p Pl (49.9" diagonally) Wireless Ready / Broadband / 3D Ready
To Last Pg

Published March 10th, 201 1 Updated July 18th, 201 1 See last page for Latest Updates

Overview of Topics to be Discussed

Preliminary: Contact Information, Preliminary Matters Specifications Information Matters, Specifications, Plasma Overview, General Troubleshooting Steps, Disassembly Instructions, Voltage and Signal Distribution Troubleshooting: Circuit Board Operation, Troubleshooting and Alignment of : Switch Mode Power Supply No VS On command input to SMPS from the Main Board. Y SUS B d Y-SUS Board Y-Drive Boards (1 Upper and 1 Lower). Z-SUS Board Control Board X Drive Boards (3)
Drives 15 TCPs (5 per/board). Each TCP drives 384 vertical electrodes. Special set-up to run Upper Y-Drive separately. Uses a Z-SUB Board for panel drive connection.

Main Board: Wi l ready, B d B d via LAN or Wi l using USB Dongle, Motion Remote. Wireless d Broad Band i Wireless i D l M ti R t Front IR/Intelligent Sensor, Motion Remote and Center LOGO Boards 3D Glasses are RF not IR Interconnect Diagram: 11X17 Foldout Section used as a quick reference sheet. 2 March 201 1 50PZ950 Plasma

Preliminary Matters

50PZ950 Pl Plasma Di l Display

Section 1
This Section will cover Contact Information and remind the Technician of Important Safety Precautions for the Customers Safety as well as the Technicians and the Equipment. Basic Troubleshooting Techniques which can save time and money sometimes can be overlooked. These techniques will also be presented. This Section will get the Technician familiar with the Disassembly, Identification and Layout of the Plasma Display Panel. At the end of this Section the Technician should be able to Identify the Circuit th d f thi S ti th T h i i h ld b bl t Id tif th Ci it Boards and have the ability and knowledge necessary to safely remove and replace any Circuit Board or Assembly.

March 201 1

50PZ950

Plasma

LG Contact Information
Customer Service (and Part Sales) (800) 243-0000 Technical Support (and Part Sales) (800) 847-7597 USA Website (GSFS) Customer Service Website Knowledgebase Website LG Web Training LG CS Learning Academy http://gsfs-america.lge.com http://www.us.lgservice.com http://lgtechassist.com https://lge.webex.com http://LGLearn.com
New: 2010/11 Wireless Ready Models Software Downloads Presentations with Audio/Video and Screen Notations

http://136.166.4.200

Training Manuals, Schematics with Navigational Bookmarks, Start-Up Sequence, Owners Guides, Interconnect Diagrams, Dimensions, Connector IDs, Product Pictures and Features. I t t Di Di i C t ID P d t Pi t dF t Also available on the Plasma Page: PDP Panel Alignment Handbook, Plasma Control Board ROM Update (Jig required)

Published March 2011 by LG Technical Support and Training LG Electronics Alabama, Inc. 201 James Record Road, Huntsville, AL, 35813.

March 201 1

50PZ950

Plasma

Preliminary Matters (The Fine Print)

IMPORTANT SAFETY NOTICE

The information in this training manual is intended for use by persons possessing an adequate background in electrical equipment, electronic devices, and mechanical systems. In any attempt to repair a major Product, personal injury and property damage can result The manufacturer or Product result. seller maintains no liability for the interpretation of this information, nor can it assume any liability in conjunction with its use. When servicing this product, under no circumstances should the original design be modified or altered without permission from LG Electronics. Unauthorized modifications will not only void the warranty but may lead to property damage or user injury warranty, injury. If wires, screws, clips, straps, nuts, or washers used to complete a ground path are removed for service, they must be returned to their original positions and properly fastened.

CAUTION
To avoid personal injury, disconnect the power before servicing this product. If electrical power is required for diagnosis or test purposes, disconnect the power immediately after performing the necessary checks Also be aware that many household products present a weight hazard checks. hazard. At least two people should be involved in the installation or servicing of such devices. Failure to consider the weight of an product could result in physical injury.

March 201 1

50PZ950

Plasma

ESD Notice

(Electrostatic Static Discharge)

Todays sophisticated electronics are electrostatic discharge (ESD) sensitive. ESD can weaken or damage the electronics in a manner that renders them inoperative or reduces the time until their next failure. Connect an ESD wrist strap to a ground connection point or unpainted metal in the product. Alternatively, you can touch your finger repeatedly to a ground connection point or unpainted metal in the product. Before removing a replacement part from its package, touch the anti static bag to a ground connection point or anti-static unpainted metal in the product. Handle the electronic control assembly by its edges only. When repackaging a failed electronic device in an anti-static bag, observe these same precautions.

Regulatory Information l f
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to g provide reasonable p protection against harmful g Part 15 of the FCC Rules. These limits are designed to p interference when the equipment is operated in a residential installation. This equipment generates, uses, and can radiate radio frequency energy, and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is reception, on, encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna; Increase the separation between the equipment and the receiver; Connect the equipment to an outlet on a different circuit than that to which the receiver is connected; or consult the dealer or an experienced radio/TV technician for help.

March 201 1

50PZ950

Plasma

Safety and Handling, Checking Points

Safety & Handling Regulations
1. 2. 3. 3 4. 5. 5. 5 6. 7. 8. 9. Approximately 10 minute pre-run time is required before any adjustments are performed. Refer to the silk screening on the Switch Mode Power Supply for proper Voltage and Current listings and manufacturers cautions. Refer to the Voltage Sticker on the Panel when making adjustments on the Power Supply Y-SUS and Z-SUS Boards. Supply, Y SUS Z SUS Boards Always adjust to the specified voltage level (+/- volt) unless otherwise specified. Be cautious of electric shock from the PDP module since the PDP module uses high voltage, check that the Power Supply and Drive Circuits are completely discharged because of residual current stored before Circuit Board removal. C-MOS circuits are used extensively for processing the Drive Signals and should be protected from static electricity electricity. The PDP Module must be carried by two people. Always carry vertical NOT horizontal. The Plasma television should be transported vertically NOT horizontally. Exercise care when making voltage and waveform checks to prevent costly short circuits from damaging the unit. Be cautious of lost screws and other metal objects to prevent a possible short in the circuitry.

10. New Plasma Models have thinner Display Panels and Frames than previous models. Be careful when lifting Plasma Displays because flexing the panel may damage the frame mounts or panel.

Checking Points to be Considered

1. Check the appearance of the Replacement Panel and Circuit Boards for both physical damage and part number accuracy. 2. Check the model label. Verify model names and board model matches. 3. Check details of defective condition and history. Example: Y-SUS or Y-Drive Board Failure, Mal-discharge on screen, etc.

March 201 1

50PZ950

Plasma

Basic Troubleshooting Steps

Define, Localize, Isolate and Correct Define Look at the symptom carefully and determine what circuits could be causing the failure. Use your senses Sight, Smell, Touch and Hearing. Look for burned parts and check for possible overheated components. Capacitors will sometimes leak dielectric material and give off a distinct odor. Listen for frequency changes which may occur with a Power Supply load failure, listen for the click of a relay closing, remember to observe the Front Power Indicator LED, if lit, it is a quick indication of Standby Voltage. Localize After carefully checking the symptom and determining the circuits to be checked and after giving a thorough examination using your senses the first check should always be the DC Supply Voltages to those circuits under test. Always confirm the supplies are not only the proper level but be sure they are noise free. If the supplies are missing check the resistance for possible short circuits. Isolate To further isolate the failure, check for the proper waveforms with the Oscilloscope to make a final determination of the failure. Look for correct Amplitude Phasing and Timing of the signals also check for the proper Duty Cycle of the signals. Sometimes glitches or road bumps will be an indication of an imminent failure. Correct The final step is to correct the problem. Be careful of ESD and make sure to check the DC Supplies for proper levels. Make all necessary adjustments and lastly always perform a Safety AC Leakage Test before returning the product back to the Customer.

March 201 1

50PZ950

Plasma

AC Leakage Test Procedure

Leakage Current Cold Check (Antenna Cold Check) p g , j p With the instrument AC plug removed from an AC source, connect an electrical jumper across the two AC plug prongs. Connect one lead of an ohm-meter to the AC plug prongs tied together and touch the other lead one at a time to any exposed metallic part on the set. Such as the antenna terminal, LAN jack, AV connections, HDMI input shield, PC input shield, etc. If the exposed metallic part has a return path to the chassis, the measurement resistance should be between 1M and 5 2M 5.2M. When the exposed metal has no return path to the chassis, the reading must be infinite. If an abnormality exists it must be corrected before the receiver is returned to the customer. Leakage Current Hot Check (See figure) Plug the AC cord directly into the AC outlet. Do not use a line isolation transformer during this check. Connect 1.5K/10watt resistor in parallel with a 0.15uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Any lt A voltage measured must not exceed 0 75 volt RMS d t t d 0.75 lt which corresponds to 0.5mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be p checked and repaired before it is returned to the customer.

March 201 1

50PZ950

Plasma

50PZ950 PRODUCT INFORMATION SECTION

This section of the manual will discuss the specifications of the 50PZ950 Ad Advanced Single Scan Plasma Display Television. d Si l S Pl Di l T l i i 10 March 201 1 50PZ950 Plasma

50PZ950 Specifications

1080P PLASMA HDTV 50" Class (49.9" diagonal) ( g )

For Full Specifications See the Specification Sheet

INFINIA Series Wi-Fi Certified TM Tru-Black Filter (Adaptor Included) THX Certified Wireless 1080p Ready 1080P Full HD Resolution Magic Motion Remote 600 Hz sub field driving Picture Wizard II 820 cd/m2 Brightness (Panel Manual) (Easy Picture Calibration) Dual XD Engine Intelligent Sensor 10M:1 Dynamic Contrast Ratio ISFccc Ready Smart Energy Saving 24P Real Cinema 4x HDMI V.1.4 with Deep Color (4 side). DivX HD AV Mode II (Cinema, Sports, Game) DLNA Certified Clear Voice II Dolby Digital 5 1 Decoder 5.1 LG SimpLink Connectivity Infinite Sound Invisible Speaker System 100,000 Hours to Half Brightness (Typical) PC Input USB 2.0 (JPEG, MP3, MP4, Divx) NetCast Entertainment Access Yahoo! TV Widgets Netflix Instant Streaming Ready Vudu (Streaming) Vudu YouTube YouTube Skype Ready Picasa Web Albums AccuWeather

11

March 201 1

50PZ950

Plasma

50PZ950 Logo Familiarization Page 1 of 3

New definition television. LGs INFINIA TVs are redefining home entertainment. Even beyond their jaw-dropping d i t t i t E b d th i j d i design, th offer they ff access to virtually unlimited entertainment through broadband connectivity and freedom with wireless HD capability.

The new black. Dont let the lamp in the corner keep you from seeing whats going on in the movie. LGs TruBlack Filter helps block glare while boosting images on the screen to improve picture quality and contrast ratio. i t lit d t t ti

You dont have to take our word for it that this is an amazing TV. To T earn THX certification, our TV passed more th 30 rigorous tifi ti TVs d than i tests, ensuring youre bringing an uncompromised HD experience home - as the director wanted it.

Entertainment on tap. NetCast Entertainment Access brings the best Internet services direct to your TV, (Internet connectivity required). Instantly access movies and TV shows, news and th d the ld largest lib t library of HD movies i 1080 f i in 1080p. weather and th worlds l

12

March 201 1

50PZ950

Plasma

50PZ950 Logo Familiarization Page 2 of 3

FULL HD RESOLUTION 1080P HD R Resolution Pi l 1920 (H) 1080 (V) l ti Pixels: Enjoy twice the picture quality of standard HDTV with almost double the pixel resolution. See sharper details like never before. Just imagine a Blu-ray disc or video game seen on your new LG Full HD 1080p TV. HDMI (1.4 Deep Color) Digital multi-connectivity HDMI (1.4 Deep color) provides a wider bandwidth (340MHz, 10.2Gbps) than that of HDMI 1.2, delivering a broader range of colors, y p p and also drastically improves the data-transmission speed. Invisible Speaker Personally tuned by Mr. Mark Levinson for LG TAKE IT TO THE EDGE newly introduces Invisible Speaker system Invisible Speaker system, guaranteeing first class audio quality personally tuned by Mr. Mark Levinson, world renowned as an audio authority. It provides Full Sweet Spot and realistic sound equal to that of theaters with its Invisible Speaker. Dual XD Engine Realizing optimal quality for all images One XD Engine optimizes the images from RF signals as another XD Engine optimizes them from External inputs. Dual XD Engine presents images with optimal quality two times higher than those of previous models.

13

March 201 1

50PZ950

Plasma

50PZ950 Logo Familiarization Page 3 of 3

AV Mode "One click" Cinema, THX Cinema, Sport, Game mode. , , p , TAKE IT TO THE EDGE is a true multimedia TV with an AV Mode which allows you to choose from 4 different modes of Cinema, Sports and Game by a single click of a remote control.

Clear Voice Clearer dialogue sound Automatically enhances and amplifies the sound of the human voice frequency range to provide high-quality dialogue when background noise swells swells. Save Energy, Save Money It reduces the plasma displays power consumption. The default factory setting complies with the Energy Star requirements and is adjusted to the comfortable level to be viewed at home. (Turns on Intelligent Sensor).

Save Energy, Save Money S E S M Home electronic products use energy when they're off to power features like clock displays and remote controls. Those that have earned the ENERGY STAR use as much as 60% less energy to perform these functions, while providing the same performance at t e sa e price the same p ce as less-efficient models. Less e e gy means you pay less o you e e gy ess e c e t ode s ess energy ea s ess on your energy bill. Draws less than 1 Watt in stand by.

14

March 201 1

50PZ950

Plasma

600Hz Sub Field Driving

(600 Hz Sub Field Driving)
600 Hz Sub Field Driving is achieved by using 10 sub-fields per frame process (vs. Comp. 8 sub-field/frame) No smeared images during fast motion scenes

Original Image

10 Sub Fields Per Frame

Sub Field firing occurs using wall charge and polarity differences between Y-SUS and Z-SUS signals.

15

March 201 1

50PZ950

Plasma

50PZ950 Remote Control

p/n AKB72914064 TOP PORTION BOTTOM PORTION

Motion Remote Magic Remote AKB732955

16

March 201 1

50PZ950

Plasma

50PZ950 Rear and Side Input Jacks

Either USB port for Software Upgrades,

Music, Videos and Photos and the Wireless Dongle USB 2 AC In USB 1 SIDE INPUTS Wireless Media Box Remote Jack Cat 5 LAN Composite Video/Audio

HDMI 1~4

REAR INPUTS

17

March 201 1

50PZ950

Plasma

Software Updates (New and Changed Functions)

A wireless Internet Connection will work for Automatic Software Downloads, however if there are problems completing download, a Wired Internet Connection is preferred

Scroll down to highlight the ? mark (SUPPORT). (SUPPORT) Cursor right to highlight Software Update Update, Press ENTER on Bring up the Customers Menu then cursor Remote down 2 times, (Input) will be highlighted. Cursor right to highlight (SETUP). Press ENTER on the Remote. Highlight Check Update Version to see if an update is available available. Scroll up to highlight ON and cursor right to turn off automatic Software Update.
Continue on next page

18

March 201 1

50PZ950

Plasma

Software Updates (New and Changed Functions)

A wireless Internet Connection will work for Automatic Software Downloads, however if there are problems completing download, a Wired Internet Connection is preferred 2) Scroll down to highlight the ? mark ( (SUPPORT). ) Cursor right and scroll down to highlight Product/Service Info Info, Press ENTER on Remote

1) Bring up the Customers Menu then cursor down 2 times, (Input) will be highlighted. highlighted Cursor right to highlight (SETUP). Press ENTER on the Remote.

3) Information for Customer Support appears. Note: Model Number does not include suffix.

Continue on next page

19

March 201 1

50PZ950

Plasma

Generic Plasma USB Automatic Software Download Instructions

1) Download the Software File.

(Root directory of the Flash Drive)

Software File Flash Drive

2) Copy new software (xxx.epk) into the root of p you the Jump Drive. Make sure y have the correct software file for your model. 3) With TV turned ON, insert USB flash drive. 4) You can see the message TV Software Upgrade (See figure on right) 5) Cursor left and highlight "START" Button and push ENTER button using the remote control. 6) You can see the download Progress Bar. 7) Do not unplug until unit has automatically restarted. 8) When download is completed, you will see COMPLETE. 9) Your TV will turn off and then restart automatically.

Currently Installed Version y Software Version found on the USB Flash Drive File found on the USB Flash Drive

Highlight Start Press Select

* CAUTION: Do not remove AC power or the USB Flash Drive. Do not turn off Di D tt ff Power, during the upgrade process.

Software Fil f Wi l S ft Files for Wireless Ready models are now R d d l located on LGTechassist.com web site.

20

March 201 1

50PZ950

Plasma

Manual Software Download:

Prepare the Jump Drive as described in the USB Automatic Download section and insert it into either of the USB ports. Bring up the Customers Menu and scroll to OPTIONS, (Nothing should be highlighted on the right side. Press the 5 key 7 times to bring up the first screen for Manual Download Screen (Expert Mode) 5 Mode).

Press the 5 key 7 times

Location of files found On the Jump Drive

Scroll down and highlight Options Highlight the Software update file the highlight Start and press SELECT to begin the download process. WARNING: Use extreme Caution when using the Manual Forced Download Menu. Any file can be downloaded when selected and may cause the Main board to become inoperative if the incorrect file was selected.

21

March 201 1

50PZ950

Plasma

Accessing the Host Diagnostic Screen (Page 1 of 2)

Use the Host Diagnostic screen to investigate the signal quality of a problem channel. 1) Place Television on the digital channel that ) g may be showing problems. 2) Bring up the Customers Menu. Cursor down two times and right once to highlight Setup. Press Enter on the remote. 4) Scroll down and highlight Options. ) g g p

5) Press the (1) Key 5 to 8 times. The Host Diagnostics screen appears. 3) The Setup Menu appears.

See next page for more details.

22

March 201 1

50PZ950

Plasma

50PZ950 Understanding the Host Diagnostic Screen (Page 2 of 2)

Model Number

Host Diagnostics
Host Information

Channel Selected

Current Channel (Main)

Model Name : 50PZ950-UA (Plasma Display) Memory FLASH : 524288 KB DRAM : 524288 KB NVM : 128 KB Host Release Version Firmware Version(MP) : 3.00.08.11(30183) Micom Version : V3.02.0 Compile Date & Time : 20101228 & 08:45:52
F = 9/5 (C+32)

Channel Info : Digital 19-1 Current Temperature MODULE Temperature: 33.5 Celsius DVI/HDMI Status Software Version Cant display this information now Wireless ready Status

Blocked or Not Blocked

Parental Control : Channel is not blocked

Panel Temperature

Wireless Host Ver:0.00.0 Wireless B/B Ver:0.00.0 Compile User : tu.ryu RF Region Config : Not Configured Media Box Type : Not Configured Channel FAT Status (Main) RF Frequency (Value):Auto (N.A.) Frequency Center Frequency : 663.00 MHz Uplink RF Power gain (Value):Auto (Min 0) Program Clock Reference (Locked or No) Downlink RF Power gain (Value):Auto:Auto (Min 0) PCR lock : Locked Channel Type (8VSB, QAM 64, 256) Link Mode : Unicast Modulation mode : QAM 256 RX MAC Address : ff:ff:ff:ff:ff:ff Channel (Locked or No) Carrier lock status : Locked TX MAC Address : ff:ff:ff:ff:ff:ff Channel Signal to Noise Ratio SNR : 37 dB Signal level : 100%
Channel Signal Level (Above 80% good) 8VSB (Above 20 is good) QAM 64 (Above 24 is good) QAM 256 (Above 30 is good)

Half Page

CH

Move Page

Exit

23

March 2011

50PZ950 Plasma

Accessing the Service Menu

To access the Service Menu. 1) You must have either Service Remote. ) p/n 105-201M or p/n MKJ39170828 2) Press In-Start 3) A Password screen appears. 4) Enter the Password. )

Note: A Password is required to enter the Se ce e u Service Menu. Enter; 0000 te ; Note: If 0000 does not work use 0413.

105-201M

MKJ39170828

24

March 201 1

50PZ950

Plasma

50PZ950 Service Menu First Page

Bring up the Service Menu using the Service Remote And pressing In-Start enter password 0413.

IN SART
SW Version 1. Adjust Check Model Name: 50PZ950-UA 2. ADC Data Serial Number: 011PTED8N316 : 03.00.08.11 3. Power Off Status S/W Version: : 3.02.0 4. System 1 MICOM Version : 1.02.51 5. System 2 BOOT Version : 0.05 (0x00) 6. Model Number D/L IR LED Version : 0.02/0.00 7. Test Option EDID (RGB/HDMI) : BCM 35230 8. External ADC Chip Type : 0.00.0 9. Pattern Selection Wireless Host Ver. : 0.00.0 Wireless B/B/ Ver. Video Processor 10. Panel Control :1.0 11. Spread Spectrum Vi-Fi Version Chip Type :0 12. Sync Level Vi-Fi Channel 13. Wireless Ready Wi-Fi MAC : 00:00:00:00:00:00 14. Stable Count MAC Address : E8:5B:5B:24:75:2C 15. ODC Test Widevine : LGTV10L000010062 ESN Num. : LGE-LX6500XXXX000A0C9037 16. Power Error History 17. SDP Server Selection Module Rom Ver: 50R3_3PV1B1 : 0.80 18. Network No. Formatter Ver. Electronic Serial Error History : VA740 RF Receiver Version : RELEASE Debug Status

Country Group

Adjust Check

US

UTT : 12 APP History Ver.:30183 PQL DB:LGE_PF_LGT10_xxNx50

Unit Total Time

Control Board Software Version

1. Country Group (Press OK to Save) Country Group Code 02 Country Group US Country US 2. Tool Option Tool Option 1 32777 Tool Option 2 65 Tool Option 3 7519 Tool Option 4 7560 Tool Option 5 14925 Tool Option 6 33625 3. Adjust White Balance: OK 4. Adjust ADC: OK 480i Component OK 1080p Component OK RGB OK 5. EDID(AC3): OK RGB OK (0x47) HDMI1 OK (0x7f,0xCF) Priority Audio HDMI2 OK (0x7f,0xBF) Mode HDMI3 OK (0x7f,0xAF) HDMI4 OK (0x7f,0x9F)

25

March 2011

50PZ950 Plasma

50PZ950 Power Off Status (IN START) Screen

Bring up the Service Menu using the Service Remote by pressing In-Start enter password 0413 or 0000.
IN START Model Name: 50PZ950-UA Serial Number: 011PTED8N316 Select Item : 03.00.08.11 3 S/W Version: : 3.02.0 MICOM Version : 1.02.51 BOOT Version : 0.05 (0x00) IR LED Version : 0.02/0.00 EDID (RGB/HDMI) : BCM 35230 Chip Type : 0.00.0 Wireless Host Ver. : 0.00.0 Wireless B/B/ Ver. :1.0 Vi-Fi Version :0 Vi-Fi Channel Wi-Fi MAC : 00:00:00:00:00:00 MAC Address : E8:5B:5B:24:75:2C Widevine : LGTV10L000010062 ESN Num. : LGE-LX6500XXXX000A0C9037 Module Rom Ver: 50R3_3PV1B1 : 0.80 Formatter Ver. RF Receiver Version : VA740 : RELEASE Debug Status UTT : 12 APP History Ver.:30183 PQL DB:LGE_PF_LGT10_xxNx50 1. Adjust Check 2. ADC Data 3. Power Off Status 4. System 1 5. System 2 6. Model Number D/L 7. Test Option 8. External ADC 9. Pattern Selection 10. Panel Control 11. Spread Spectrum 12. Sync Level 13. Wireless Ready 14. Stable Count 15. ODC Test 16. Power Error History 17. SDP Server Selection 18. Network Error History Power Off Status Most Recent 0. POWER_OFF_BY_LOCAL_KEY 1. POWER_OFF_BY_ACDET 2. POWER_OFF_BY_REMOTE_KEY1 3. POWER_OFF_BY_LOCAL_KEY 4. POWER_OFF_BY_ACDET 5. POWER_OFF_BY_ACDET 6. POWER_OFF_BY_ACDET 7. POWER_OFF_BY_SW_DL 8. POWER_OFF_BY_ACDET 9. POWER_OFF_BY_LOCAL_KEY 10. POWER_OFF_BY_LOCAL_KEY 11. POWER_OFF_BY_REMOTE_KEY1 12. POWER_OFF_BY_REMOTE_KEY1 13. POWER_OFF_BY_ACDET 14. POWER_OFF_BY_ACDET 15. POWER_OFF_BY_LOCAL_KEY 16. POWER_OFF_BY_LOCAL_KEY 17. POWER_OFF_BY_LOCAL_KEY 18. POWER_OFF_BY_LOCAL_KEY 19. POWER_OFF_BY_REMOTE_KEY1 20. POWER_OFF_BY_REMOTE_KEY1 21. POWER_OFF_BY_ACDET 22. POWER_OFF_BY_SW_DL 23. POWER_OFF_BY_LOCAL_KEY
INSTOP (Instop Button on Serv. Remote) SW_DL (Software Download) AUTO_OFF (No Signal Time Out) OFF_TIMER (Auto Timer Off)

LOCAL_KEY (Key Board Power) REMOTE_KEY1 (Remote Power) ACDET (Loss of AC Power) SW_DL (Software Download Restart)

26

March 2011

50PZ950 Plasma

50PZ950 Power Off Status Details

CODE POWER_OFF_BY_CPUCMD POWER_OFF_BY_ABN POWER_OFF_BY_KEYTIMEOUT POWER_OFF_BY_ACDET POWER_OFF_BY_RESET POWER_OFF_BY_5VMNT POWER_OFF_BY_NO_POLLING POWER_OFF_BY_REMOTE_KEY POWER_OFF_BY_OFF_TIMER POWER_OFF_BY_SLEEP_TIMER POWER_OFF_BY_FAN_CONTROL POWER_OFF_BY_INSTOP_KEY POWER_OFF_BY_AUTO_OFF POWER_OFF_BY_ON_TIMER POWER_OFF_BY_RS232C POWER_OFF_BY_SWDOWN POWER_OFF_BY_LOCAL_KEY POWER_OFF_BY_CPU_ABNORMAL POWER_OFF_BY_INV_ERROR POWER_OFF_BY_SW_DL POWER_OFF_BY_UNKNOWN

EXPLANATION Power off by CPU Command Power off by abnormal status Power off when TV is not turned off during a certain time Power off by not detecting AC (abnormal case) Power off by Micom Reset Power off by not detecting 5V monitoring Power off when receiving no acknowledge Power off by remote key Power off by Off timer Power off by sleep timer Power off by fan control (Not Used) Power off by InStop Key Power off by auto off function Power off by On timer (2hr if no key presses) Power off by RS232C command Power off by software download Power off by local key Power off by CPU Abnormal status Power off by LCD module inverter error (LCD Only) Power off by Software update Power off by the other causes

27

March 2011

50PZ950 Plasma

50PZ950 UTT Reset (IN START) Screen

IN SART Model Name: 50PZ950-UA Serial Number: 011PTED8N316 : 03.00.08.11 S/W Version: : 3.02.0 MICOM Version Select Item 4 : 1.02.51 BOOT Version : 0.05 (0x00) IR LED Version : 0.02/0.00 EDID (RGB/HDMI) : BCM 35230 Chip Type : 0.00.0 Wireless Host Ver. : 0.00.0 Wireless B/B/ Ver. :1.0 Vi-Fi Version :0 Vi-Fi Channel Wi-Fi MAC : 00:00:00:00:00:00 MAC Address : E8:5B:5B:24:75:2C Widevine : LGTV10L000010062 ESN Num. : LGE-LX6500XXXX000A0C9037 Module Rom Ver: 50R3_3PV1B1 : 0.80 Formatter Ver. RF Receiver Version : VA740 : RELEASE Debug Status
Unit Total Time UTT : 12 APP History Ver.:30183 PQL DB:LGE_PF_LGT10_xxNx50 Note: After UTT is reset, the UTT time on the left will not reset to 0 until the Service Menu is exited. Scroll to (System 1) then Right Cursor

SYSTEM 1 1. Adjust Check 2. ADC Data 3. Power Off Status 4. System 1 5. System 2 6. Model Number D/L 7. Test Option 8. External ADC 9. Pattern Selection 10. Panel Control 11. Spread Spectrum 12. Sync Level 13. Wireless Ready 14. Stable Count 15. ODC Test 16. Power Error History 17. SDP Server Selection 18. Network Error History 0. Baudrate 1. 2 Hours Off (On Timer) 2. 2 Hours Off (Screen Mute) 3. 15Min Force Off 4. Audio EQ 5. Dynamic EQ 6. A2 Threshold 7. HDMI Sound(Port1) 8. Lip Sync Adjust(DTV) 9. Dimming 10. Tuner Option 11. Atten RF Signal 12. UTT Reset 13. Channel Mute 14. Debug Status Changes to 15. NVRAM Type Doing 16. HDEV 17. Blue back 18. China Cable SO 19. Booster On (VHF) 20. Booster Off (VHF) 21. Booster On (UHF) 22. Booster Off (UHF)
Scroll to (UTT Reset) Press (Select) Reset changes to Doing then back to Reset

115200 On Off On On On 11 HDMI Port1 0 On Enhanced Ghost Off Reset On RELEASE EEPROM Off On On 0 0 0 0

After Reset (Doing) has completed, Reset returns. After Exit the UTT Timer is 0

28

March 2011

50PZ950 Plasma

50PZ950 Model Number Download (IN START) Screen

When the Main Board is replaced, the Model Number and Serial Number must be corrected. Follow these instructions
IN SART Model Name: 50PZ950-UA Serial Number: 011PTED8N316 : 03.00.08.11 S/W Version: : 3.02.0 MICOM Version : 1.02.51 BOOT Version : 0.05 Select Item 6 (0x00) IR LED Version : 0.02/0.00 EDID (RGB/HDMI) : BCM 35230 Chip Type : 0.00.0 Wireless Host Ver. : 0.00.0 Wireless B/B/ Ver. :1.0 Vi-Fi Version :0 Vi-Fi Channel Wi-Fi MAC : 00:00:00:00:00:00 MAC Address : E8:5B:5B:24:75:2C Widevine : LGTV10L000010062 ESN Num. : LGE-LX6500XXXX000A0C9037 Module Rom Ver: 50R3_3PV1B1 : 0.80 Formatter Ver. RF Receiver Version : VA740 : RELEASE Debug Status UTT : 12 APP History Ver.:30183 PQL DB:LGE_PF_LGT10_xxNx50
Bring up the Service Menu using the Service Remote. Scroll down to item 6. Model Number D/L to highlight. Press ENTER or Cursor Right. Select Model Name or Serial Num. to change and Cursor Right.

1. Adjust Check 2. ADC Data 3. Power Off Status 4. System 1 5. System 2 6. Model Number D/L 7. Test Option 8. External ADC 9. Pattern Select 10. Panel Control 11. Spread Spectrum 12. Sync Level 13. Wireless Ready 14. Stable Count 15. ODC Test 16. Power Error History

Model Number D/L 0. Model Name 1. Serial Num. 50PZ950-UA 011PTED8N316 Press OK to Save
To Change the Model Number: 1) Use the cursor right or left to select the area to change to the correct value. 2) Use the cursor up or down to change. 3) Cursor right until there is no text cursor visible. 4) Cursor down to highlight Serial Number To Change the Serial Number: 6) Cursor Right and a Text Cursor appears under the first digit. Use the same procedure as above to correct the Serial Number. 5) Press ENTER to Save. 6) Press IN-START to see the changes on the left.

29

March 2011

50PZ950 Plasma

50PZ950 Panel Control (IN START) Screen

At the bottom right you can see the Panel Model Number, Control board Software Version and the Panel Temperature
IN START Model Name: 50PZ950-UA 1. Adjust Check Serial Number: 011PTED8N316 2. ADC Data S/W Version: : 03.00.08.11 3. Power Off Status MICOM Version : 3.02.0 4. System 1 BOOT Version : 1.02.51 5. System 2 IR LED Version : 0.05 (0x00) 6. Model Number D/L EDID (RGB/HDMI) : 0.02/0.00 7. Test Option Chip Type : BCM 35230 8. External ADC Wireless Host Ver. : 0.00.0 9. Pattern Selection Wireless B/B/ Ver. : 0.00.0 Select Item 10 10. Panel Control Vi-Fi Version :1.0 11. Spread Spectrum Vi-Fi Channel :0 12. Sync Level Wi-Fi MAC : 00:00:00:00:00:00 13. Wireless Ready MAC Address : E8:5B:5B:24:75:2C 14. Stable Count Widevine : LGTV10L000010062 15. ODC Test ESN Num. : LGE-LX6500XXXX000A0C9037 16. Power Error History No Selection Module Rom Ver: 50R3_3PV1B1 17.SDP ServerFunction Formatter Ver. Panel Model No. : 0.80 18.Network Error History RF Receiver Version : VA740Ctl. Board ROM Software Version Debug Status : RELEASE
Panel Temperature Unit Total Time UTT : 12 APP History Ver.:30183 PQL DB:LGE_PF_LGT10_xxNx50 Software Build Version

Panel Control 1. AV/PC 2. ISM 3. Gamma 4. Power Save 5. APS Contrast 6. OrbitPixel 7. OrbitStep 8. OrbitTime 9. MRE(FMC) 10. DPS2 11. GRP 12. Module OSD 13. Module XDP 13. Formatter XDP 14. RF Emitter Control 15. Formatter Download 16. Reset Use Time Module Name: Rom Ver. Temperature: Build Ver. AV Auto 0 Mode 0 98 2 2 step 120 sec. On 0 Off 0 On On On

50R3 50R3_3PV1B1 25.00 Celsius V30183

30

March 2011

50PZ950 Plasma

50PZ950 Power Error History (IN START) Screen

Bring up the Service Menu using the Service Remote by pressing In-Start enter password 0413 or 0000.
IN SART Model Name: 50PZ950-UA Serial Number: 011PTED8N316 S/W Version: : 03.00.08.11 MICOM Version : 3.02.0 BOOT Version : 1.02.51 IR LED Version : 0.05 (0x00) EDID (RGB/HDMI) : 0.02/0.00 Chip Type : BCM 35230 Wireless Host Ver. : 0.00.0 Wireless B/B/ Ver. : 0.00.0 Vi-Fi Version :1.0 Vi-Fi Channel :0 Wi-Fi MAC : 00:00:00:00:00:00 MAC Address : E8:5B:5B:24:75:2C Widevine : LGTV10L000010062 Select Item 16 ESN Num. : LGE-LX6500XXXX000A0C9037 Module Rom Ver: 50R3_3PV1B1 Formatter Ver. : 0.80 RF Receiver Version : VA740 Debug Status : RELEASE UTT : 12 APP History Ver.:30183 PQL DB:LGE_PF_LGT10_xxNx50 1. Adjust Check 2. ADC Data 3. Power Off Status 4. System 1 5. System 2 6. Model Number D/L 7. Test Option 8. External ADC 9. Pattern Selection 10. Panel Control 11. Spread Spectrum 12. Sync Level 13. Wireless Ready 14. Stable Count 15. ODC Test 16. Power Error History 17. SDP Server Selection 18. Network Error History POWER ERROR HISTORY 1. Last History: 2. Last History: 3. Last History: 4. Error Count 1) PFC_DET Error 2) 5V OVP 3) 5V UVP 4) 17V OVP 5) 17V UVP 6) M5V OVP 7) M5V UVP 8) Vs OCP 9) Vs OVP 10) Vs UVP 11) Va OVP 12) Va UVP 5. Reset All
PFC_DET: Power Factor Control Detect OVP: Over Voltage Protect OCP: Over Current Protect UVP: Under Voltage Protect Most Recent

VA UVP VS OCP NONE

ff ff ff ff ff ff ff 1 ff ff ff 1

Clears Contents

31

March 2011

50PZ950 Plasma

50PZ950 EDID Download Screens

EZ ADJUST 0. Tool Option1 1. Tool Option2 2. Tool Option3 3. Tool Option4 4. Tool Option5 5. Country Group 6. ADC Calibration 7. White Balance 8. 10 Point WB 9. Test Pattern 10. PCM EDID D/L 11. AC3 EDID D/L 12. Sub B/C 13. V-Com 14. P-Gamma 15. Touch Sensitivity Setting
PCM EDID D/L HDMI1 HDMI2 HDMI3 HDMI4 RGB Start OK/(PCM) OK/(PCM) OK/(PCM) OK/(PCM) OK/(PCM) Reset

When Item 11 was selected

If Item 5 on Adjust Check in the 1st page of the Service Menu shows EDID PCM this shows OK(PCM) If Item 5 on Adjust Check in the 1st page of the Service Menu shows AC3, this shows NG. If NG was shown, highlight Start and press Select on the remote. Writing appears, then OK/(PCM) shows here. Now Item 5 on Adjust Check in the 1st page of the Service Menu shows EDID PCM. If Reset is selected, Erasing will appear and then this shows NG.

When Item 12 was selected

AC3 EDID D/L HDMI1 HDMI2 HDMI3 HDMI4 RGB Start OK/(AC3) OK/(AC3) OK/(AC3) OK/(AC3) OK/(AC3) Reset

If Item 5 on Adjust Check in the 1st page of the Service Menu shows EDID AC3 this shows OK(AC3) If Item 5 on Adjust Check in the 1st page of the Service Menu shows PCM, this shows NG. If NG was shown, highlight Start and press Select on the remote. Writing appears, then OK/(AC3) shows here. Now Item 5 on Adjust Check in the 1st page of the Service Menu shows EDID AC3. If Reset is selected, Erasing will appear and then this shows NG.

32

March 2011

50PZ950 Plasma

50PZ950 Dimensions
There must be at least 4 inches of Clearance on all sides 46-1/4" 1175.2mm 23-1/8" Center Center 587.5mm 5-3/8" 137mm 15-3/16" 385mm Center 14-3/16" 360mm 15-3/4" 400mm 1-5/16" 49.6mm

31" 787.6mm

15-3/4" 400mm Model No. Serial No. Label Remove 4 screws to remove stand for wall mount

28-3/8" 720.6mm

7-1/4" 184mm

2-5/8" 67mm 20-13/16" 528mm Max Watts 270W Power Consumption: Typical: 140W <0.1 Watts (Stand-By) Weight:

3-11/16" 93m 12-1/2" 317.2mm 71.57 lbs with Stand 63.64 lbs without Stand

33

March 2011

50PZ950

Plasma

Wireless Media Box

Wireless Media Box (Sold Separately)
The Wireless Media box communicates to the television via a wireless receiver called a Dongle. The Dongle attaches to the Television via two connections: 1. HDMI Cable from the Dongle to the TV to transfer Audio and Video Signals. 2. Wired Remote cable between the TV and Dongle for Control Functions.

Media Box
Media Box Audio is only to TV. (TV audio can not be heard via Optical Audio Out on Media Box). Media Box is Not 3D Ready.

Non Compressed Audio/Video is sent to the TV.

Wired Remote to control the Media Box

Wireless Receiver/Transmitter Wi l R i /T itt Dongle Attaches via Velcro to the back of the set HDMI

TV A/V Inputs

34

March 201 1

50PZ950

Plasma

Wireless Network Adaptor (AN-WF100)

Wireless Network Adaptor Included

Using the LG Wireless LAN for Broadband Adaptor, allows the TV to connect to a wireless LAN network. The Wireless Network adaptor attaches to the Television via either of the two USB connections: Allows access to DLNA: Digital Living Network Alliance
Any USB Port is OK.

AP (Wireless Router)

Side A/V Inputs

Wireless Adaptor Dongle

Cat 5 Cable with RJ 45 Connectors on each side

Modem

Note: If Software Update does not complete using Wireless Dongle, use Wired (CAT-5) Connection to the Router.

35

March 201 1

50PZ950

Plasma

DISASSEMBLY SECTION
This section of the manual will discuss Disassembly, Layout and Circuit y, y Board Identification of the 50PZ950 Advanced Single Scan Plasma Display Panel. Upon completion of this section the Technician will have a better understanding of the disassembly p g y procedures, the layout of the p , y printed circuit boards and be able to identify each board.

36

March 201 1

50PZ950

Plasma

Removing the Back Cover

Caution: The Back may have very sharp edges

To remove the back cover remove the 28 screws cover, Indicated by the arrows. (The Stand does not need to be removed). PAY CLOSE ATTENTION TO THE TYPE, SIZE AND LENGTH Of the screws when replacing the back cover. Improper type can damage the front.

37

March 201 1

50PZ950

Plasma

Circuit Board Layout

FPC F

Identifying the Circuit Boards

Panel Voltage and Panel ID Label

Y-Drive U Upper Y-SUS Y SUS Y-Drive L Lower

TCP Heat Sink

FPC FPC FPC FPC FPC FPC FPC

FPC

Z-SUS Power Supply (SMPS)

FPC

Z-SUB Control Main Board

FPC

AC In

Left X
IR/LED/Motion/ 3D Transmitter Board

Center X
Conductive Tape

Right X

Side Input (part of main)

Soft Touch S ft T h Keypad

Invisible Speaker

Invisible Speaker

38

March 201 1

50PZ950

Plasma

50PZ950 Connector Identification Diagram

Y-DRIVE UPPER Board
PANEL p/n: EAJ61527904 (PDP50R30000.ASLGB 50Inch 1920X1080) p/n: EAJ61527931 (PDP50R30000.ASLGB 50Inch 1920X1080) P101
p/n: EBR69839101

Z-SUB Board
p/n: EBR71728001

P102

P811 P218 P214 P210 P215

P111 P112 P121 P221 P211 P212 P213

p/n: EBR69839201

SMPS POWER SUPPLY Board

p/n: EAY62171101 Top row Odd Back row Even

P103

Z-SUS Board

P203 P201

p/n: EBR71727901

P204 P205 P201 P206

P101 P102 P103

P104

Y-SUS Board
p/n: EBR69839001

P202

P201

SC101 P813 L N P102 n/c

P217 P216 P213 P102 P203

p/n EAD59493806

P202

P105 P101

P2
LVDS p/n EAD60956111

P500 P1600
P3201 n/c P102 n/c

CONTROL Board P31

P203

P3200
P602 n/c P101 n/c P600 n/c

P203

Y-DRIVE LOWER Board

p/n: P102 EBR71727801

P104 AC In

P900 P1302

MAIN Board
p/n: EBR73295301

P204

P121 P100
P201 P101

LEFT X Board
p/n: EBR71728101
P202 P203 P204

P110 P120 P320

P205

p/n: EBR71728401
P202

P310

CENTER X P321
P204 P205

P320 P310
P201 P202

RIGHT X Board
p/n: EBR71728501
P203 P204 P205

P201 P100

P203

PWR LED J1

p/n: EBR72650201

Speakers (Front Right) IR Front Soft Switch Key Pad

p/n: EAB62028901

p/n: EBR72499601

p/n: EBR72769401

Motion Remote

Speakers (Front Left)

p/n: EAB62028901

39

March 2011

50PZ950

Plasma

Disassembly Procedure for Circuit Board Removal

Note: Remove AC Power before doing any circuit board removal procedures.

Switch Mode Power Supply Board Removal Disconnect the following connectors: P811, P813 and SC101. Remove the 7 screws holding the SMPS in place. Remove the board. When replacing, be sure to readjust the Va/Vs voltages in accordance with the Panel Label. Also, re-confirm VSC, -Vy and Z-Bias as well. Y-SUS Board Removal

Note: The Y-SUS does not come with the connectors between the Y-SUS and Y-Drive

Disconnect the following connectors: P218 P210 and Ribbon Cables P102 and 213. P218, 213 Remove the 9 screws holding the Y-SUS in place. Do not run the set with P213 or P121/P221 removed. Remove the Y-SUS board by lifting up slightly and the carefully unseating connectors P214, P215, P217 and P218 by sliding the Y-SUS to the right while gently prying the connectors apart. When replacing, be sure to readjust the Va/Vs voltages in accordance with the Panel Label. Confirm VSC, -Vy and Z-bias as well. ll Note: The Y-SUS does not come with the connectors Board Standoff Y-Drive Boards Removal
between the Y-SUS and Y-Drive

Disconnect the following Flexible Ribbon Connectors P101~P104 and/or P201~P204: Disconnect the following Connectors P213 and P121/P221 by pressing in on the locking mechanism and lifting upward. Do not run the set with these connectors removed. Remove the 3 screws holding either of the Y-Drive Boards in place. Lift up slightly, then slide Collar to the left while gently prying the connectors apart. Remove the Y-Drive Board. Note: Y-SUS, Z-SUS and Y-Drive Boards are mounted on board stand-offs that have a small collar. The board must be lifted slightly to clear these collars. Behind each board are Rubber pieces that act as a cushion. They may make the board stick when removing.

40

March 201 1

50PZ950

Plasma

Disassembly Procedure for Circuit Board Removal (Continued)

Z-SUS Board Removal
Disconnect the following connectors: P203 and P201 by lifting up the locking mechanism and unseating. Remove the 7 screws holding the board in place. Lift up slightly to clear the screw stand-offs and pull the Z-SUS to the left to unseat P204, P205 and P206 from the Z-SUB board and remove the board. When replacing, be sure to readjust the Va/Vs voltages in accordance with the Panel Label. Confirm VS, -Vy and Z-bias as well.

Z-SUB Board Removal

Disconnect the following connectors: P101, P102 and P103 by pulling the locking mechanism to the right and remove the flexible ribbon cables, lifting them up slightly and pulling the FPC out of the connector. Remove the 3 screws holding the board in place. Lift the board up slightly and slide to the right while unseating P204, P204 P205 and P206 Remove the Z-SUB board P206. Z SUB board.

Main Board Removal

Remove connectors: P3200 LVDS (flip the locking tab upward and pulling out the ribbon cable), P500, P1600, P900 and P1302. Remove the 4 screws holding the Main board in place and Remove the board. (Slide Left)

Control Board Removal

Remove the following ribbon cables by flipping the locking tab upward and pulling out the ribbon cables, P31 LVDS, P2, P105, and P101, P102, P104. Remove the 4 screws holding the Control board in place. Lift up and Remove the board. (Note: Chocolate piece behind upper left of board, move to new board).

Power LED and Motion Remote Board Removal

MOTION REMOTE: Remove 1 screw and remove the board. Disconnect the one connector. POWER LED BOARD: Release tab on the left of the board and Remove the Board and Disconnect J1.

Front IR / Key Pad / Intelligent Sensor Board y g

Front IR / Intelligent Sensor and Key Pad Board: (Not Removable) attached to front glass.

41

March 201 1

50PZ950

Plasma

X Drive Circuit Board Removal

Remove AC and Lay the Television down carefully on a padded surface. Make sure to use at least two people for this process so as not to flex the panel glass. Refer to next 3 pages for disassembly and precautions. A. B. C. D. Remove the Back Cover. Remove the Stand (4 Stand Screws were removed during back removal). pp (5 ) p Remove the Stand Metal Support Bracket ( Screws) 2 Plastic tap thread and 3 Metal thread. Remove the Vertical support Braces. Note: There is a Left and a Right brace. (3 Screws per/bracket) 1 Plastic tap thread and 2 Metal thread. (Note: The top screws were removed when the back was taken off). E. Remove the 13 screws holding the Heat Sink. (Warning: Never run the set with this heat sink removed). removed) To remove the heat sink, lift up to release the tacky Chocolate (heat transfer material) and slide the heat sink to the left to clear the connector wires on the right side. Note: There may be pieces of conductive tape that may need to be removed. Also, note that there are several pieces of Chocolate heat transfer material attached all the way across the underside of the heat sink. X-DRIVE LEFT, CENTER AND RIGHT REMOVAL: Disconnect all TCP ribbon cables from the defective X-Drive board and all other Ribbon cables going to the b d th board. Remove the 5 screws holding the defective X-Drive board in place. Remove the board. Reassemble in reverse order. Recheck VA / VS / VSC / -VY / Z-Bias.

42

March 201 1

50PZ950

Plasma

Getting to the X Circuit Boards

Stand B k t Bl St d Bracket Blowup

D Left

D Right

Warning: Never run the TV with the TCP Heat Sink removed Ground Wire

E Heat Sink

Remove the tape.

43

March 201 1

50PZ950

Plasma

Left , Center and Right X Drive Connector Removal

From the Control Board to the X-Boards. There may be tape on these connectors connectors. P110 P210 P310 Are all the same Remove tape (if present) and Gently pry the locking mechanism upward and remove the ribbon cable f from the connector.

Disconnect connector P121 Va from the Y-SUS to Left X Only Disconnect Va from Left to Center and Center to Right X Boards

P120 to P220 Left to Center X P221 to P320 Center to Right X Carefully lift the TCP ribbon up and off. It may stick, be careful not to crack TCP stick TCP. (See next page for precautions)

Removing Connectors to the TCPs.

Gently lift the locking mechanism upward on all TCP connectors Left X: P201~205 L ft X P201 205 Center X: P201~205 Cushion (Chocolate) Right X: P201~205 And pull the TCP from the connector.

TCP

Flexible ribbon cable connector

44

March 201 1

50PZ950

Plasma

TCP (Tape Carrier Package) Generic Removal Precautions

Lift up the locking mechanism as shown to p g release the ribbon cable. (The Lock can be easily damaged, and needs to be handled carefully.)

Separate the TCP Ribbon Cable from the connector as shown. TCP Film can be easily damaged. Handle with care. The TCP Ribbon Cable has two small tabs on each side which help secure it into the connector. They have t b lift d up slightly to pull h to be lifted li htl t ll the Ribbon Cable out. Note: TCP is usually stuck down to the Chocolate heat transfer material, be Very Careful when lifting up on the TCP ribbon cable cable. Tab Tab

Chocolate

45

March 201 1

50PZ950

Plasma

Left, Center and Right X Drive Removal

Remove the screws indicated from the X-Board being removed.

All X-Boards pass R G B signals to 5 TCPs across the bottom of the panel. R, G, TCP s panel

46

March 201 1

50PZ950

Plasma

3D SECTION AND 3D TROUBLESHOOTING

This section will give you an understanding of 3D as it relates to Televisions. This section also includes 3D troubleshooting. Note: The 3D Glasses must be mated To the Television so that multiple TVs Can operate in the same room with different glasses synchronized to the correct TV TV. HOW TO CONNECT THE 3D GLASSES When initially switched on, the device will automatically be connected to the TV with the on strongest signal. HOW TO RECONNECT THE 3D GLASSES Press the power button for over eight seconds. Release the button when the green LED light turns on. Then, you will see the green light blink three times before the device is switched off. If you switch the power on again, the glasses will be connected to the TV or PROJECTOR with the strongest signal.

47

March 201 1

50PZ950

Plasma

3D Fundamentals (What is 3D?) From the Human Perspective

Each eye looks at an image from slightly different angles. Therefore, the brain takes these two different images and translates them into one image giving us depth perception. This is difficult to reproduce on a 2 dimensional screen. We have to come up with a scheme that will allo us to see the same image from screen ha e p ith ill allow s two different angles giving us 3D effects.

If the two images were added together without the g g brain doing the calculations to combine them, they would appear out of focus. Note: The Left and Right eye are actually seeing the same image but from a different angle, but for this explanation one is shown inverted from the other for clarity purposes simply to show there is a difference between the two images seen by each eye.

48

March 201 1

50PZ950

Plasma

3D Fundamentals (What is 3D?) From the Electronic Perspective

Each Camera looks at an image from slightly different angles. Each camera generates its own video, well call Left Camera View and Right Camera View. The Frame packing adds both of these videos together as described in the 3D Broadcasting page page. Original Image

Left Camera View

Right Camera View

Both Videos are Packed together For transmission.

The two videos are separated by the Frame rate converter in the Television and put on the screen. The first horizontal line is the Left Camera view and the 2nd line is the Right camera view. 3rd line is Left, 4th is Right and so on.

Note: The Left and Right Cameras are actually seeing the same image but from a different angle, but for this explanation one is shown inverted from the other for clarity purposes simply to show there is a difference between the two images seen by each camera.

49

March 201 1

50PZ950

Plasma

LCD 3D Formatter
3D Formatter - All Formats of input are available and converted by 3D technology - Full HD input available u put a a ab e - 3D Enhancement Input Capabilities HDMI 1.3 / HDMI 1.4 Regular 2D 3D Formats (Frame P k d) F t (F Packed) 1) Side by Side 2D 3D Formatter or 2D 3D to 2D Output Capabilities

LCD: Interlaced (Passive) Horizontal 1) Line by Line

2) Top and Bottom or 3) Checkerboard R 4) Frame Sequential (Full Resolution available) L L HDMI 1.4 (Only) 5) Over/Under L

Polarized Lens (Frame ( Retarder) over LCD panel and Polarized Glasses required No Synchronization required between glasses and TV

PLASMA: Frame Sequential R

Active Glasses required Synchronization required between glasses and TV

L / R represents; Left Camera View Right Camera View

50

March 201 1

50PZ950

Plasma

TV 3D broadcasting
3D for All types of broadcasting signals
1. 2. 3. 4. 5. Input of broadcasting signal Press 3D button. Read the Warning. Press ENTER. Select type of input source. In case 3D looks *abnormal, press Quick MENU and select 3D Mode Setting. *Abnormality may be caused by reversed L/R *Ab li b db d order of the input signal. If TV already in Left/Right change to Right/Left or vice versa. HD Broadcasting Input SD Broadcasting Input Online Video Input Network Drive Input

(1)

HDMI p Component RF

Component p Composite RF, S-Video

USB Port

Wireless Wired LAN

(2) (3) (5) (4)

Top & Bottom 2D to 3D Side by Side Checker Board Single frame Sequential

See next page for more 3D Mode Setting details.

Note: Picture behind the menu is showing a side by side format. Note: HDMI 1.4 will automatically select 3D type for you.

51

March 201 1

50PZ950

Plasma

3D Settings Menu
3D settings may help with 3D view pleasure.
(1) In case 3D looks *abnormal press Quick MENU (2) Select 3D Mode Setting . abnormal, Quick MENU 3D Setting

(1) (2)

3D Picture Size: Cuts off the outer edges of the picture and stretch it to fit the full screen in 3D mode. 3D Depth: Adjusts the distance between the object and the background in the picture to enhance the 3D effect in 2D to 3D mode mode. 3D View Point: Brings the picture (including both the object and background images) to the front or back to enhance the 3D effect in 3D mode. 3D Picture Balance: Adjusts the color and brightness difference between the right and left sides of the picture in 3D mode. 3D Picture Correction: Changes the order of images in the right and left sides of the picture in 3D mode.

(3)

Note: Not all selections will be available on all 3D sources.

52

March 201 1

50PZ950

Plasma

LG RF 3D Emitter & Glasses

Convenient 2.4GHz RF Transmitter built-in to TV
Wider viewing angle Longer Viewing distance Longer battery life LED Indicator

AG-S250
Power Button

USB port (Charging port) 8-pin mini USB cable 3D Glasses Lenses Nose Pad

(1.5h charging / 40h battery life)

Improved sync performance

User friendly Glasses

1) 2) 3) 4) 5) L-frame for glasses users UV coating to prevent scratch LED indicator for user convenience Easy to Recharge with USB port (Note: Glasses will work while being charged) Adjustable Nose Piece for comfort Power On Power Off Press the Power button once Press and hold down the Power button The power is automatically turned off if no signal is transmitted for 1 minute. Battery (Lithium polymer) discharge

3D Glasses Lenses

7m

600 600

2~7 Meter Viewing Distance (6.5 ft~ 22.9 ft) Maximum 10 Meter (32.8 ft) The red LED blinks once. once The red LED blinks three times.

RF Transmitter Location

Auto

Off1.

The red LED blinks three times. It will also be automatically switched off when the user does not make any move for over ten minutes. If the battery is discharged, the LED blinks for 1 minute and turns off automatically. * When charging is completed, the LED is lit green.

Battery (Lithium polymer) discharge

The Auto Off function automatically turns the 3D glasses off if there is no signal for 1 minute after the connection with the 3D signal emitter is disconnected due to a change in the distance or angle from the 3D signal emitter when the user moves under normal operating conditions.

53

March 201 1

50PZ950

Plasma

Active RF glasses 3D TV components

Battery B tt USB Charge Port (8-pin mini USB) AG-S250 0.80mA/h 1Hr. 50min Charge Time 40Hr. Charge

RF Receiver

3D Sync signal

RF Sync signal

*TN LCD shutter Twisted State light passes

Shutter Actuator circuit board On St t li ht bl k d O State light blocked

TV with built in RF Transmitter

*TN LCD shutter CD h *TN = Twisted Nematic

54

March 201 1

50PZ950

Plasma

3D Active Glasses Type

Shutter glasses type 3D: Separating left and right images by synchronizing the TV and the glasses Fundamentals of Shutter glasses < Shutter glasses 3D > Between Frames

Left Eye viewing left camera shot

Between Frames

The image is broadcast using two different viewing angles every other frame.

Right Eye viewing right camera shot The 3D Glasses are then synchronized with the two different images to give the 3D effect. They are blanked between scene changes.

55

March 201 1

50PZ950

Plasma

3D Video viewing range and Compatible 3D Formats

VIEWING CONDITIONS Viewing Distance Viewing Angle
Accepted 3D Formats Signal Resolution 720P 1080i HDMI Input 1080p 1920X1080 27 24 1280X720 Horizontal Frequency kHz 45 33.75 67.5 60 Vertical Frequency Hz Playable 3D video format Top & Bottom, Side by Side HDMI (V1.4 with HDMI 3D Frame Packing Top & Bottom, Side by Side Top & Bottom, Side by Side Checker Board Single Frame Sequential Top & Bottom, Side by Side Checker Board HDMI (V1.4 with HDMI 3D Frame Packing Top & Bottom, Side by Side Checker Board Top & Bottom Side by Side Bottom, Checker Board

Maximum 7m (22.9 ft)

Optimum p 2m-7m (6.5 ft - 22.9 ft)

120 (When the viewing distance is 3 m (22.9 ft)

33.75 USB Input 1080p 1920X1080 33.75

30 30

56

March 201 1

50PZ950

Plasma

50PZ950 3D Troubleshooting Flow Chart Page 1 of 3

If you are having trouble seeing 3D, Try changing the 3D selection types if it is difficult to determine what format the 3D movie is in. Example: Top/Bottom, Side by Side, Checker Board, Frame Sequential. Make sure you are using at least version 1.3 HDMI cable. (1.4 HDMI will auto select).

Play a 3D Movie Make sure the 3D Glasses are charged Charged

No 3D

Red Power LED should stay on solid for about 3 sec. then go off. When power button is pressed for Power Off, the LED will blink 3 times. Note 1: The Red LED will blink constantly for 1 minute if battery is discharged. Note 2: Glasses can operate using the USB connector plugged in if batteries are not charged. Dont forget to try swapping the L/R selection by pressing the 3D Options button on the remote control. (If available)

Glass turn off in 1 Min. with no 3D sync. Glasses turn off in 10 Min with no movement.

A simple test is to hold the glasses about 1 ft. in front of you towards a white sheet of paper. The TV must be playing a 3D movie and be in the 3D mode. If the glasses sync up the paper will appear as looking through normal sun glasses, if not synced, the paper will appear amber in color.

No Change Change the 3D Glasses

AG-S230, AG-S250, AG-S270)

No glasses sync Check 3.3V for the Motion Remote board. P1302 Connector 1 pin : 3.3V OK
Note: Motion Remote board connector has no ID

NG

Check 3.3V_Normal Regulator IC505

NG

Replace Main board

Check 3D/Motion Remote RF Transmitter Board Connector pin 1 : 3.3V OK Check for 60Hz sync signal on pin 12 of P1302 OK

NG

Cable Open

3.32V p/p 60 Hz 1.59VDC

Check 3D Sync is output from IC3202. R3280 R3238 Back side of Board: 3D-Sync NG Front side of Board R1324 P1302 Pin 12

NG

Replace Main board

Continued on next page.

57

March 2010

50PZ950

Plasma

50PZ950 3D Troubleshooting Flow Chart Page 2 of 3

Note: Motion Remote board connector has no ID

Continued from previous page

Check for 60Hz sync to the 3D sync / Motion Remote board. Connector pin 12 OK

Should be

3.32V p/p 60 Hz 1.59VDC

RF Freq

GPIO 0 (9) GPIO 1 (10) GPIO 2 (11) 0 1 0 0 0 1 0 0 0

Check P1302 Connector pins 9, 10, 11 (See Chart) Pin 10 should be only high OK Check 3D / Motion Remote Connector pins 9, 10, 11 OK Replace 3D / Motion Remote p/n: EBR72499601

3D Disable 60Hz 59.94Hz

NG

Replace Main board

Note: If all are low, make sure you are in 3D Mode on the Television

NG

Cable Open

See next page for additional details

58

March 2010

50PZ950

Plasma

50PZ950 3D Sync Troubleshooting Flow Chart Page 3 of 3

Continued from previous page
Note: The 3D sync on the LVDS cable is not the same as the 3D_SYNC route shown on the Main board. This is just a TP. 3D_SYNC straight from (IC3202) chip. 3D-Sync R3280 R3238 Back side of Board

3.32V p/p 60 Hz 1.59VDC

Check 3D_SYNC Line Control P31 pin 79

Check 3D_SYNC Line Main P3200 pin 2

P500
L519 IC505 IC501 L505

To R1324
P600 n/c
L511

Control Board
P105
C61

SW3200 3D IC Reset IC3202

L1603 L1602

P102 n/c

IC500 USB2

P22 n/c

C52

P2 To Z-SUS Board FL5 IC61

M5V

L1601

IC1600

P1600

L1600

To Y-SUS Board

IC25

IC101

IC102

IC51

P3201 n/c
IC1700

P101 n/c

IC1201 USB1

25Mhz X3200

L1 FL1/2 L2
C65

L1702

IC102 IC3202 IC401 IC1702

IC1200 IC502
3 2 2 1

C76

D1 Blinks Indicating Board is Functioning

VS-DA TP

HDMI4

BCM
IC101 IC700

D1 IC11 IC1 X1

D717
A2 A1 C

CONTROL BOARD p/n: EBR71727801

AUTO Gen

P31 LVDS

P3200 LVDS

IC402

P101
To Left X Board

P3200
SW600 Micro Reset 10Mhz X600
1 3 2

HDMI3
A2 A1 C

Q1
C72

D716 HDMI2 D2100

A2

P102
To Center X Board

IC53

P104
To Right X Board

IC600

IC503 Microprocessor IC801

A1

D714 Q710

A1 A2 2

1 4

HDMI1

3D_SYNC straight from the MCM (IC1) chip. Check 3D_SYNC Line Pin 12 3.32V p/p 60 Hz 1.59VDC Motion Remote Board Connector has no ID GPI0 1 (pin 10) should be high

P900
Q1002
D

Pin 12

IC803

Q1001
S G E B C

3D-Sync R1324 Front side of Board

TUNER UDA55AL
Digital Video

3D_SYNC pin 12

P1302

Q?

Analog Video

18. IF p 17. IF n 16. IF AGC 15. Reset 14. 3.3V 13. 1.26V 12. GND 11. CVBS 10. NC 9. SIF 8. NC 7. SDA 6. SCL 5. NC 4. NC 3. 5V 2. NC 1. NC

C B B E C E

Q2105

TU2101

Q2104 IC506 AV IN 2 L
1 23 2

59

March 2010

50PZ950

Plasma

CIRCUIT OPERATION, TROUBLESHOOTING AND CIRCUIT ALIGNMENT SECTION

50PZ950 Plasma Display
This Section will cover Circuit Operation, Troubleshooting of the Power Supply, Y-SUS Board, Y-Drive Boards, Z-SUS Board, Control Board, Main Board and the X Drive Boards. Alignment of the Power Supply, Y-SUS Board and the Z-SUS Board.

At the end of this Section the technician should understand the operation of each circuit board and how to adjust the controls The technician should then be able to troubleshoot a circuit board failure replace the controls. failure, defective circuit and perform all necessary adjustments.

60

March 201 1

50PZ950

Plasma

50PKZ950 Signal and Voltage Distribution Block

Y Drive Upper
FPCs P101 FG Voltages measured from Floating Ground P214 Floating Gnd (FG) FG10.9V P215 Floating Gnd (FG) Y-Scan P218 P113 P811 SMPS OUTPUT VOLTAGES IN STBY STBY_5V (3.47V) SMPS OUTPUT VOLTAGES IN RUN STBY_5V, AC Det, Error, +5V, 17V to Main Board Vs, Va and M5V to Y-SUS,

Display Panel Horizontal Electrodes Sustain

Vs
P203 Z-Drive FPCs

P102

P111

P103 P112 P104 FG5V P121

M5V, Vs, Va
Note: Va not used by Y-SUS only fused and routed to the X-Board

SMPS Board
SK101 AC Input Filter P813

AC Det line (if missing) will Mute the Audio. Error is Not Used Set in Stand By: STB +3.47V Run: +STB 5.1V SMPS TURN ON SEQUENCE Step 1: RL ON: 17V, +5V, Error, ,AC_Det. Step 2: M_On: M5V, Va, Vs

Z-SUS Board
P101 P102 P103 P201 P101 P102

FPCs P221 FG5V

When M5V arrives FG10.9V, FG23.77V, 18V Scan Data, When VS arrives: VSC, -VY Clk, FG

P201

Y-SUS Board
P217 Floating Gnd (FG) Y-Scan P216 Floating Gnd (FG) Y-Scan P213 Scan Data, Clk P203 P102

P201

P211 P202 P212 P203 P213 P204 M5V

Logic Signals To Y-SUS and Y-Drive

P105 P2

18V / M5V

Z Drive Control Signals

P103 P202

18V / M5V
Note: 18V not used by Control

CONTROL Board P31

P101 P104 P102

Z-SUB
Display Enable LVDS Video P1600 P500 P3200 Turn On Commands

P203

3.3V

FPCs Speakers

3.3V RGB Logic Signals 3.3V Va

P210 P232

3.3V
STBY_5V

MAIN Board
P900 P300 +3.3V To Motion Remote

Y Drive Lower
Display Panel Horizontal Electrodes Reset, Sustain

Va

RGB Logic Signals 3.3V Va

3.3V Key Board Pull Up Soft Touch Keys And Power Button

3.3V

P100

IR, Intelligent Sensor

P101

X-Board-Left

P122

P110 P120 P220

X-Board-Center
P211 P311 P331

P221 P320 P310

X-Board-Right

P101

P102

P103

P104

P105

P301

P302

P303

P304

P305

P301

P302

P303

P304

P305

Display Panel Vertical Address (Colored Cell Address)

61

March 2011

50PZ950

Plasma

Panel Label Explanation

(1) (2) (3) (4) (5) (6) (7) (9) (10) (11) (12) (13) (14) (15)

(8)

(1) Panel Model Name (2) Bar Code (3) Manufacture No. (4) Adjusting Voltage DC, Va, Vs (5) Adjusting Voltage (Set Up / -Vy / Vsc / Ve / Vzb) (6) Trade name of LG Electronics (7) Manufactured date (Year & Month) (8) Warning

(9) TUV Approval Mark (Not Used) (10) UL Approval Mark (11) UL Approval No. (12) Panel Model Name (13) Max. Watt (Full White) (14) Max. Volts (15) Max Amps Max.

62

March 201 1

50PZ950

Plasma

Adjustment Notice

All adjustments (DC or Waveform) are adjusted in WHITE WASH. Customers Menu, Select Options, select ISM select WHITE WASH.

It is critical that the DC Voltage adjustments be checked when; C 1) SMPS, Y-SUS or Z-SUS board is replaced. 2) Panel is replaced, Check Va/Vs since the SMPS does not come with new panel 3) A Picture issue is encountered 4) As a general rule of thumb when ever the back is removed ADJUSTMENT ORDER IMPORTANT DC VOLTAGE ADJUSTMENTS C O G S S 1) POWER SUPPLY: VS, VA (Always do first) 2) Y-SUS: Adjust Vy, VSC 3) Z-SUS: Adjust Z-Bias (VZB) WAVEFORM ADJUSTMENTS 1) Y-SUS: Set-Up, Set-Down
The Waveform adjustment is only necessary 1) When the Y-SUS board is replaced 2) When a Mal-Discharge problem is encountered 3) When any abnormal picture issue is encountered

Remember, the Voltage Label MUST be followed, it is specific to the panels needs.
Power Supply

Set-Up

-Vy

Vsc

Ve

ZBias

Panel Rear View

All label references are from a specific panel panel. They are not the same for every panel encountered.

63

March 201 1

50PZ950

Plasma

SWITCH MODE POWER SUPPLY SECTION

This S ti Thi Section of the Presentation covers troubleshooting the S it h M d Power Supply. f th P t ti t bl h ti th Switch Mode P S l Upon completion of the section the technician will have a better understanding of the operation of the Power Supply Circuit and will be able to locate test points needed for troubleshooting and alignments. DC Voltages developed on the SMPS Adjustments VA and VS. Always refer to the Voltage Sticker on the back of the panel, located at the upper Center, for the correct voltage levels for the VA and VS supplies as these voltages will vary from Panel to Panel even on the same Model.

SMPS P/N EAY62171101 Check th ilk Ch k the silk screen label on th t center of th P l b l the top t f the Power S Supply b d t id tif th correct part l board to identify the t t number. (It may vary in your specific model number). On the following pages, we will examine the Operation of this Power Supply.

64

March 201 1

50PZ950

Plasma

Switch Mode Power Supply Overview

VS

SMPS p/n: EAY62171101

The Switch Mode Power Supply Board Outputs to the :

Drives the Display Panels Horizontal Electrodes. To Y-SUS, fused then to the X-Boards. (Not used by Y-SUS). Primarily responsible for Display Panel Vertical Electrodes. Used to develop Bias Voltages on the Y-SUS, Z-SUS Boards. p g ,

Y-SUS Board

VA M5V

Y-SUS Delivers VS to Z-SUS Board

VS Drives the Display Panels Horizontal Electrodes.

STBY 5V

Microprocessor Circuits Audio B+ Supply, Tuner B+ Circuits Signal Processing Circuits AC_Det d Error_Det lines are not used. AC D t and E D t li t d

Main Board

17V 5V

Adjustments

There are 2 adjustments located on the Power Supply Board VA and VS. The M5V is pre-adjusted and fixed. All adjustments are made referenced to Chassis Ground. Use Full White Raster 100 IRE VS VA VR901 VR501

65

March 201 1

50PZ950

Plasma

50PZ950 SMPS Layout Drawing

Example Panel Label:
P811 1) VS 2) VS 3) n/c 4) Gnd 5) Gnd 6) VA 7) M5V
VS or VA Diode Check Open with Board Disconnected or Open with Board Connected M5V Diode Check 0.73V Board Connected or 0.72V Disconnected
VA TP VS TP

P811

Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.A. / -190 / 150 / N.A. / 130 Max Watt : 360 W (Full White)
VS Adj VR901

F801 4A/250V

VA
P813 "SMPS" to P500 "Main"
Pin 18 17 16 15 13-14 9-12 8 5-7 3-4 1-2 Stby Gnd b M_On 0V ab AC_Det 0V a RL_ON 0V Stby_5V 3.47V Gnd Gnd ac Error_Det 3.44V a 5.1V 0.46V Gnd Gnd a 17V 0V
e

VS
Diode Gnd Open 3.1V Open 2.53V Gnd 2.84V 2.13V Gnd 3.06V

F302/F801 160.1V STBY 390V Run

Label

Auto_Gnd

VA Adj VR502

Hot Ground F302 2.5A/250V

POWER SUPPLY p/n: EAY62171101

CURRENT LABEL
Input: 100~240V 50/60Hz 4.8A 17V= 1A 5.1V = 3.0A STBY5V (5V) = 1A VS 201~207V = 1.6A VA 55V = 2.0A M5V (5.1V) = 2.5A PDP Module MAX 360W

Run Gnd 3.28V 4.06V 3.28V 5.14V Gnd 4.02V 5.17V Gnd 17V

Note a: The RL_On command turns on the 17V, +5V, Error_Det and AC_DET. Note b: The M-On command turns on M5V, Va and Vs.

D102 RL103 D101 F101 10A/250V

P813
J63 J26 5.1V 17V

Note c: The Error Det line is not used in this model. Note d: AC Det line (if missing) will Mute the Audio. Note e: Pin 18 is grounded on the Main. If opened, the power supply turn on automatically.

AC In

P701 n/c

66

March 2011

50PZ950

Plasma

Power Supply Circuit Layout

P811 To Y-SUS Fuse F801 160.1V Stby 390V Run 4Amp/250V

SMPS p/n: EAY62171101

VS Source

VS VR901

VA Source
VA VR501 Fuse F302 160.1V Stby 390V Run 2.5Amp/250V Bridge g Rectifiers

17V Source

PFC C Circuit

STBY 5V, 5V Source

RL103

Main Fuse F101 10Amp/250V

P701 n/a AC I Input t SC 101

To MAIN P813

67

March 201 1

50PZ950

Plasma

Power Supply Basic Operation

AC Voltage is supplied to the SMPS Board at Connector SC101 from the AC Input assembly, routed to the two Bridge Rectifiers D101 and D102 which then route the primary voltage to the PFC circuit (Power Factor Controller). Standby 5V is developed from 160.1V source supply (which during run measures 390V measured from the primary fuses F801 and F302). This Thi supply i also used t generate all other voltages on th SMPS l is l d to t ll th lt the SMPS. The STBY5V (standby) is B+ for the Controller chip on the back of the SMPS board (IC701) and output at P813 pins 13 and 14 then sent to the Main board for Microprocessor (IC600) operation (STBY 3.47V RUN 5.14V). When the Microprocessor (IC600 on the Main Board) receives a POWER ON Command from either the Power button or the Remote IR Signal, it outputs a high (3.28V) called RL_ON at Pin 15 of P500 to P813 on the SMPS. This command causes the Relay Circuit to close Relay RL103 bringing the PFC circuit up to full power by increasing the 160V standby to 390V run which can be read measuring voltage at Fuse F302 and F801 (390V) from Hot Ground. AC Detection (AC Det) is generated on the SMPS, by rectifying a small sample of the A/C Line and routed to the Controller (IC701) where it outputs at P813 pin 16 (4.06V) and sent to P500 to the Main Board, but it is not used in this set. When RL_ON arrives, the run voltage +5V source becomes active and is sent to the Main Board via P813 (+5.14V at pin 5, 6 and 7) The (Error Det) from the SMPS Board to the Main Board can be measured at pin 8 of P813 (3 44V STBY and 4 02V 7). (3.44V 4.02V RUN), but it is not used. The RL-ON command also turns on the 17V (Audio B+) which is also sent to the Main Board. The 17V (17V) Audio supply outputs to the Main board at P813 pins 1 and 2 and used for Audio processing and amplification and wireless dongle operational voltage, (when connected). The 17V is also regulated down to 7V by IC500 and then down to 5V by IC506 to become Tuner 5V, (5V_TU). The next step is for the Microprocessor IC600 on the Main Board to output a high (3 28V) on M ON Line to the SMPS at P813 (3.28V) M_ON Pin 17 which is sensed by the Controller IC701, turning on the M5V line and outputs at P811 pin 7 to the Y-SUS board. The Controller (IC701) also uses the M_ON line to turn on the VA and the VS supplies. (Note there is no VS On Command in this set). VS is output at P811 to the Y-SUS board P210. (VA pins 6 and VS pins 1 and 2) N i d i d 2). Note: Th Va is fused (FS203) on the Y SUS then routed out P203 pins 4 5 to the X B d The V i f d h Y-SUS h d i 4-5 h X-Board Left. Vs is routed out of the Y-SUS P218 pins 4-5 to P203 on the Z-SUS where it is fused by FS201. AUTO GND Pin 18 of P813: This pin is grounded on the Main board. When it is grounded, the Controller (IC701) works in the normal mode, meaning it turns on the power supply via commands sent from the Main board. When AUTO GND is floated (ope ed), t pulls (opened), it pu s up a d p aces t e Co t o e ( C 0 ) into t e Auto mode. In t s state, t e Co t o e tu s o t e po e supply and places the Controller (IC701) to the uto ode this the Controller turns on the power supp y in stages automatically. A load is necessary to perform a good test of the SMPS if the Main board is suspect.

68

March 201 1

50PZ950

Plasma

50PZ950 Television Turn On Sequence

F302 F801
In Stand-By Primary side is 160.1V In Run (Relay On) Primary side is 390V

AC In

(SMPS)
Stand By 5V Reg
STBY 3.47V RUN 5.14V RL On

3rd
Relays

Vs Reg

Vs

1
AC Det

+5V Regulator
RL On

1st

M5V Reg

M5V Va Vs

17V Reg

2nd

Va Reg

8
Va

9
Vs

9
Vs

9
Vs

AC Det.

Stand By Error Det. 5V

5V

17V

M5V
7

CONTROL
M5V 18V
7 7 7 3.3V Reg

6
RL On Not Used

Y-SUS
M_On 8

Z-SUS
10.9VFG Reg 18V Reg

5
17V 7V Via Audio IC500 IC1600 +5V HDMI EDID And other circuits

7
8 At point 3 TV is in Stand-By state. It is Energy Star Compliant. Less than 1 Watt

18V / M5V

7 10.9V Floating Gnd

If Missing Mutes Audio

Error Det. Not Used

18V / M5V

Y DRIVE Upper
7

5VFG Reg 5VFG

Y DRIVE Lower
M5V
7 3.3V

7 5VFG 3.3V 7

Tuner 5V Via IC506 M_On

Va
8

3.3V Reg IC503

Reset R630/C607

3.3VST

5 Error Relay Det. On Microprocessor 7 4

2 3

MAIN Board
Power On

X Board Va Left 8 2 4 Front IR Board

X Board Va Center 8

X Board Right

STBY 5V

IC600

Remote or Key Pad

Soft Touch Key Pad

Power Key

Remote Power Key

69

March 2011

50PZ950

Plasma

Turn On Sequence Text

The text below is related to the previous page.
STBY 5V (Stepped down to 3.3V_ST by IC503) powers on the Microprocessor IC600 on the Main board. This also starts ( pp _ y )p p the 10Mhz Oscillator (X600) however, the Microprocessor is not functional until after it is Reset. The Reset circuit (C607 and R630) is energized when 3.3V_ST arrives. AC Det is 0V when the set is in Stand-By, but rises to 4.06V when the set turns on by the Relay-On Command. AC Det is not used in this set. At power on the 1st output from the Microprocessor is, the Relay On command called (RL-ON) which turns on the following SMPS supplies: +5V for Video Processing 17V for Audio Amplification and Tuner B+. On the Main board, 17V is stepped down to 7V (IC500) then 5V (5V_TU by IC506). The 17V is also sent to the Audio Amp (IC1600). The SMPS (+5V) creates a signal called (ERROR DET) and is sent to the Main Board. ERROR DET is Not used by the Main board. The 2nd output from the Microprocessor is the (M_ON) command which turns on (3) supplies: (1) M5V (Monitor 5V): For the Control Board, Y-SUS Board, Lower Y-Drive and Z-SUS Board. (The M5V is routed through the Y-SUS to the Control Board then to the Z-SUS and through the Y-SUS to the Lower Y-Drive). (2) Va: (Voltage for Address) For amplification voltage for the TCPs driving the vertical electrodes. (Voltage routed through the Y-SUS then to the X-Drive boards. (3) Vs: Voltage for Sustain sent to the Y-SUS and then to the Z-SUS) used for amplification voltage driving the horizontal electrodes. On the Y-SUS, when M5V arrives, it develops 3 voltages: FG23V, FG10.9V (FG=Floating Ground) and 18V. The 18V is routed through the Control board to the Z-SUS. The FG10.9V is routed to the upper Y-Drive board and regulated down to FG5V and used by both the upper and lower Y-Drive boards for the low voltage processing voltage. When Vs arrives on the Y-SUS, it develops 2 additional voltages; -Vy and VSC which are adjustable. When the M5V from the SMPS through the Y-SUS arrives on the Control board, the control develops 3.3V and 1.8V for internal use and 3.3V which is routed down to the each X-Board for each TCPs low voltage processing voltage.

70

March 201 1

50PZ950

Plasma

Power Supply Va and Vs Adjustments

Important: Use the Panel Label Not this book for all voltage adjustments adjustments. Use Full White Raster White Wash
Va TP or P811 Pin 5 Vs TP or P811 Pin 1 or 2 Example Voltage Label

Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.A. / -190 / 150 / N.A. / 130 Max Watt : 360 W (Full White) VA Voltage VS Voltage

Vs Adjust: Place voltmeter on VS TP. Adjust VR901 until the reading j g matches your Panels label. Va Adjust: Place voltmeter on VA TP. Adjust VR502 until the reading j g matches your Panels label.

71

March 201 1

50PZ950

Plasma

Power Supply Static Test with Light Bulb Load

Using two 100 Watt light bulbs, attach one end to Vs and the other end to ground. Apply AC to SC101. If the light bulbs turn on and VS is the correct voltage, allow the SMPS to run for several minutes to be sure it will operate under load. If this test is successful and all other voltages are generated, you can be fairly assured the power supply is OK. Note: To be 100% sure, you would need to read the current handling capabilities of each power supply listed on the silk screen on the SMPS and place each supply voltage under the appropriate load.
Pins
100W

or

2
P811

VS

VS VS n/c Gnd Gnd Va M5V

VA TP VS TP

F801 4A/250V

Note: Always test the SMPS under a load using the 2 light bulbs. Abnormal operational conditions may result if not loaded.
VS Adj VR901

CURRENT LABEL
Input: 100~240V 50/60Hz 4.8A 17V= 1A 5.1V = 3.0A STBY5V (5V) = 1A VS 201~207V = 1.6A VA 55V = 2.0A M5V (5.1V) = 2.5A PDP Module MAX 360W

100W

Gnd
VA Adj VR502

Pins

4 or 5
Hot Ground

POWER SUPPLY p/n: EAY62171101

P811 Check Pins 1 or 2 for Vs voltage Check Pins 6 for Va voltage Check Pins 7 for M5V voltage

F302 2.5A/250V

P813
RL103

Check Pins 1 or 2 For 17V (17V)

F101 10A/250V

P813
AC In P701 n/c

Check Pin 5,6 and 7 for (+5.22V) Check Pin 8 for Error Det (4.94V) Check Pins 13 or 14 for 5V SBY (4.94V) Check Pin 16 for AC Det (4.94V)

Note: To turn on the Power Supply; 1) With Main Board connected, press power. 2) Without Main Board connected SMPS will turn on automatically.

Any time AC is applied to the SMPS, STBY 5V will be 3.47V and will be 5.14V when the set turns on. AC DET WILL NOT be present until RL_ON arrives on. (On Main board, [if missing] will mute the Audio). Error line WILL NOT be present until RL_ON arrives on. (On Main board is not used).

72

March 2011

50PZ950

Plasma

50PZ950 Power Supply Static Test (Forcing on the SMPS in stages)

With P813 disconnected from the Main board (P500) attach two 100 Watt light bulbs, attach one end to Vs and the other end to ground. Apply AC to SC101. If the light bulbs turn on and VS is the correct voltage, allow the SMPS to run for several minutes to be sure it will operate under load. If this test is successful and all other voltages are generated, you can be fairly assured the power supply is OK. Note: To be 100% sure, you would need to read the current handling capabilities of each power supply listed on the silk screen on the SMPS and place each supply voltage under the appropriate load. Then follow the instructions below to completely test turn on sequence. Note: Placing the two 100 Watt light bulbs from Vs to Ground will assure the power supply will regulate with a load and no other Abnormal conditions may result.
Pins
100W

or VS

2
P811

After Step (B) P813 Check Pins 1 or 2 For 17V (17V) Check Pin 5,6 and 7 for (+5.22V) Check Pin 8 for Error Det (4.94V) Check Pins 13 or 14 for 5V SBY (4.94V) Check Pin 16 for AC Det (4.94V)

VS VS n/c Gnd Gnd Va M5V

VA TP

Use Main Board Side Pin 1 (Front Right) P500

17V

VS TP

2 4 6 8 10

1 3 5 7 9 11 13 15 17

17V Gnd +5V +5V Gnd Gnd STBY 5V RL ON M_On

F801 4A/ 250V

Gnd
VS Adj VR901

100W

Gnd
VA Adj VR502

+5V Error Det Gnd

Pins

or 5

or

8
Hot Ground

POWER SUPPLY p/n: EAY62171101

After Step (C) P811 Check Pins 1 or 2 for Vs voltage Check Pins 6 for Va voltage Check Pins 7 for M5 voltage

Gnd 12 STBY 14 5V AC Det 16 100

B
100

F302 2.5A/250V

A
Auto Gnd

RL103

18

F101 10A/250V

P813
AC In P701 n/c

When the supply is operational in its normal state the Auto Ground line at Pin 18 of P813 is held at ground by the Main Board. This Power Supply can be powered on sequentially to test the Controller Chip IC701 operational capabilities and for troubleshooting purposes. Disconnect P500 from the Main board and use the holes in that end of the connector to insert the jumper and resistors. Warning: Remove AC before adding or removing any plug or resistor. Note: Leave previous installed 100 resistor in place when adding the next resistor. (A) Ground the Auto Gnd Line (Pin 18) will allow the supply to be powered up one section at a time. (B) Add a 100 watt resistor from 5V Standby to RL_ON and the AC Det, Error, 17V and 5V Lines on P813 will become active. (C) Add a 100 watt resistor from any 5V line to M_ON (Monitor_On) to make the M5V, VS and VA lines operational. P811 (VS pins 1 and 2) (VA pin 6) and (M5V pin 7).

73

March 2011

50PZ950

Plasma

P813 SMPS Connector Identification, Voltages and Diode Check

P813 Connector SMPS" to Main" P500
Pin 18 17 16 15 13-14 9-12 9 12 8 5-7 3-4 34 1_2
ac e

P813
Diode Open Open 3.1V Open 2.53V Gnd G d 2.84V 2.13V Gnd 3.06V 1

Label Auto_Gnd
b

STBY Gnd 0V 0V 0V 3.47V Gnd G d 3.44V 0.46V Gnd 0V

Run Gnd 3.28V 4.06V 3.28V 5.14V Gnd G d 4.02V 5.17V Gnd 17V

No Load 4.86V 0V 4.94V 0V 4.94V Gnd G d 4.94V 5.22V Gnd 17V

M_ON AC Det

ad a

17V

5V

RL_ON

STBY_5V Gnd G d Error_Det

a

5.1V

Gnd
a

17V

a Note: The RL_On command turns on the 17V, +5V, Error_Det and AC_DET. b Note: The M On command turns on M5V, Va and Vs. M-On c Note: The Error Det line is not used in this model. Note: This connector has two d Note: AC Det line is not used. rows of pins. e Note: Pin 18 is grounded on the Main. If opened, the power Odd on top row. supply turns on automatically.
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

74

March 201 1

50PZ950

Plasma

P811 and SC101 SMPS Connector Identification, Voltages and Diode Check
SC101 AC INPUT Pin L N STBY 120VAC 0.4VAC Run 120VAC 0VAC Diode Check Open Open

P811 "Power Supply to Y-SUS P210

P811

Pin 1~2 1 2 3 4~5 6 7

Label Vs V n/c Gnd Va M5V

Run *201V n/c Gnd *55V 5.0V

Diode Check Open O n/c Gnd Open 1.38V

1

* Note: This voltage will vary in accordance with Panel Label

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

75

March 201 1

50PZ950

Plasma

Y-SUS BOARD SECTION

(Overview)

Y-SUS Board develops the Y-Scan drive signal to the Y-Drive boards. This Section of the Presentation will cover alignment and troubleshooting the Y-SUS Board. Upon completion of the Section the technician will have a better understanding of the operation of the circuit and will be able to locate test points needed for troubleshooting and alignments. g Adjustments DC Voltage and Waveform Checks Diode Mode Measurements Operating Voltages
SMPS Supplied VA VS M5V VA supplies the Panels Vertical Electrodes (Routed to the Left X-Board) VS Supplies the Panels Horizontal Electrodes. Also routed out to the Z-SUS pp ( ) M5V Supplies Bias to Y-SUS. (From Y-SUS routed to the Control Board then Z-SUS). Also, in this set, M5V is routed to the Lower Y-Drive for the data buffers. -VY Sets the Negative excursion of Reset in the Drive Waveform VSC Sets the amplitude of the complex waveform. SET UP sets amplitude of the Top Ramp of Reset in the Drive Waveform SET DOWN sets the Pitch of the Bottom Ramp for Reset in the Waveform Used internally to develop the Y-Scan signal. (Also routed to the Control Board then routed to the Z-SUS board).

Y-SUS Developed

-VY VR501 VSC VR500 V SET UP VR402 V SET DN VR401 18V

Floating Ground

FG 10.9V Used on the Y-Drive boards (Measured from Floating Gnd) FG 23.77V Used in the Development of the Drive Waveform ( p (Measured from Floating Gnd) g )

-Vy and VSC generated when Vs arrives on the board. FG10.9V, FG23.77V and 18V generated when M5V arrives on the board.

76

March 201 1

50PZ950

Plasma

Y-SUS Block Diagram

Power Supply Board - SMPS
Distributes Vs

Z-SUS Board

Simplified Block Diagram of Y-Sustain Board Y-SUS Board

VA

Distributes Vs, Va and M5V 18V / M5V Logic

Receive M5V, Va, Vs from SMPS

Distributes 18V and M5V

Control Board

Distributes VA

VS

Circuits generate Y-Sustain Waveform

Generates Vsc and -Vy from M5V by DC/DC Converters Also controls Set Up/Down

M5V

Logic: Wave shape development and Scan Control Signals

Left X Board

FETs amplify Y-Sustain Waveform

Generates Floating Ground g 10.9V/23.77V by DC/DC Converters

Distributes FG10.9V FG10.9V FG10 9V

Logic and Scan control signals needed to develop Y-Scan and to scan the panel

Logic: Scan Control Signals

Logic

Y-Drive Upper Board Distributes

Receive Y-Scan Waveform
FG5V

Y-Drive Lower Board

Receive Y-Scan Waveform

Display Panel

77

March 201 1

50PZ950

Plasma

Y-SUS Board Layout

Or use the Left Side of C540 454V p/p w/Y-Drives 424V p/p no/Y-Drives FG10.9V Pins 1-2 P214 To Y-Drive Upper

FS203 (VS) 6.3A/250V -Vy Vy R527 VSC R548

P218

To Z-SUS VS, VS VA and M5V Input from the SMPS P210

VR501 VSC

VR500 -Vy
P215 To Y-Drive Upper Y-Scan Y Scan Pins 9~12

FS202 (M5V) 10A/125V / FS201 (VA) 4A/125V

VR401 Set Dn VR402 Set Up C540

FS501 (18V) 2A/125V

Y-Scan Sig

Y-Scan Pins 1~4 P217 To Y-Drive Lower

Y-Scan Pins 11~12 P216 To Y-Drive Lower

18V (pins 6~8) to Control for Z-SUS M5V (pins 3~5) Ribbon

P213 P102
WARNING: Do not run set if P213 is removed. Damage will occur.

Logic Signals from the Control Board

P203

Va to Left X Board Pins 5~7

78

March 201 1

50PZ950

Plasma

WARNING: The upper and lower Y-DRIVE Board has to be Removed Completely if P213 is pulled.
10.9VFG

VR501 VSC
J33

D504 158VFG VSC

G

P214 Pins 3-12 FGnd Pins 1-2 FG10.9V

+Vy R527

D S

Q502

D503
103VFG

T500

Gnd Gnd n/c VS VS n/c ER ER

50PZ950 Y-SUS Board Component Layout Drawing

P218
FS203 (VS) 6.3A / 250V
Note With No Y-Drives: FG23.85V reads 23.85V FG10.8V reads 11.2V
D512 23.77VFG Diode Check 3.1V Red lead on FG Open Blk lead on FG D511 10.9VFG Diode Check 0.5V Red lead on FG Open Blk lead on FG FS201 Va or FS203 Vs Diode Check reads Open with Board Disconnected or Connected

D505 IC501 D501 D511 10.9VFG T502 IC500

P214

VR500 +Vy
R548

P215 Pins 9-12 VSCAN n/c Pin 8 FGnd Pins 1-7

VSC R548

23.77VFG

D512
18.34V

FS202 (M5V) 10A / 125V

D515

P215

IC302

VR401 Set-Dn
VScan FGnd

FS501 (18V) 2A / 125V

FS201 (VA) 4A / 125V

P210

Q502 190VFG VSC +Vy regulator

D500

FS202 M5V Diode Check reads 0.73V Board Connected or 1.32V Disconnected
FS501 Protects 18V Creation D515 and T502 Diode Check With board Connected or 1.32V Disconnected

P217 Pins 6-12 FGnd n/c Pin 5 VSCAN Pins 1-4

C540

VR402 Set-Up

P217

To run the 18V and Floating Ground Voltages, Ground CTRL_OE and supply 5V to Y-SUS CTRL_OE should be 0V (5V indicates and problem)

P216 Pins 11-12 VSCAN Pins 1-10 FGnd

P216

1) M5V 2) M5V 3) OC2_B 4) Gnd 5) DATA_B 6) Gnd 7) OC1_B 8) OC2_T 9) Gnd 10) DATA_T 11) Gnd 12) OC1_T 13) Gnd 14) CLK 15) STB

J113

Y-SUS EBR69839001

J81
Gnd

Board Disconnected Diode Check readings

CTRL_OE

P102

P102 Pins 6-8 18V Pins 3-5 M5V

23VFG D512 3.1V Red Lead on FG Open Blk Lead on FG 10.9VFG D511 0.5V Red Lead on FG Open Blk Lead on FG (+Vy D505) 0.56V Red Lead on FG Open Blk Lead on FG

VS / Va Open Red Lead on FG Open Blk Lead on FG (FS501) 18V 0.62V Red Lead on FG 1.32V Blk Lead on FG (FS202) M5V 0.54V Red Lead on FG 1.4V Blk Lead on FG

P203

VSCAN 107V AC RMS

P213

P203 1-2) Gnd 3) n/c 4-5) VA

(VSC D504) 0.49V Red Lead on FG Open Blk Lead on FG

79

March 2011

50PZ950

Plasma

VSC and -VY Adjustments

CAUTION: Use the actual panel label and not the book for exact voltage settings. These are DC level Voltage Adjustments j p This is just for example Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.A. / -190 / 150 / N.A. / 130 Max Watt : 360 W (Full White) -Vy Voltage Reads Positive R548 VSC TP -Vy Voltages Reads Positive VSC

Set should run for 10 minutes, this is the Heat Run mode. Set screen to White Wash. 1) Adjust Vy (VR500) to Panels Label voltage (+/- 1/2V) 2) Adjust VSC (VR501) to Panels Label voltage (+/- 1/2V)

VR501 VSC Adj

Location: Center Top Left of board

R527 -Vy TP

Location: Top Right of board

80

March 201 1

VR500 -Vy Adj

50PZ950

Plasma

Y-Scan Signal Overview

Y-Drive Upper Test Point Just above 2nd Buffer from bottom

Overall signal observed 2mS/div

107VRMS

560V p/p

Blanking

Blanking

NOTE: The Waveform Test Points are fragile. If by accident the land is torn and the run lifted, make sure there are no lines left to right in the screen picture. There is another test point on the Upper Y-Drive board that can be used. Basically any output pin to any of the FPC to the panel are OK to use.

Adjustment Area

X10 Sub Field Firing (600Hz) Video

81

March 201 1

50PZ950

Plasma

Locking on to the Y-Scan Waveform Tip YNote, Note this TP (VS_DA) can be used as an (VS DA) External Trigger for scope when locking onto the Y-Scan (Scan) or the Z-Drive signal. This signal can also be used to help lock the scope when observing the LVDS video signals.

82

March 201 1

50PZ950

Plasma

Observing (Capturing) the Y-Scan Signal for Set Up Adjustment YFig 1: Fi 1 As an example of how to lock in to the Y-Scan Waveform. Fig 1 shows the signal locked in at 4ms per/div. Note the 3 blanking sections. j pointed out within the Waveform The area for adjustment is p Fig 2: At 2mSec per/division, the area of the waveform to use for SET-UP or SET-DN is now becoming clear. Now only two blanking signals are present present. Fig 3: At 100us per/div the area for adjustment of SET-UP or SET-DN is i now easier t recognize. It is outlined within th W i to i i tli d ithi the Waveform. f st large signal to the right of blanking. Remember, this is the 1 g Fig 4: At 40uSec per/division, the adjustment for SET-UP can be made using VR402 and the SET-DN can be made using VR401. It will make this adjustment easier if you use the Expanded scope Expanded mode of your scope.
Set must be in WHITE WASH All other DC Voltage adjustments should have already been made.

Adjustment Area

Area to expand Adjustment Area Area to p expand Blanking Area to be adjusted

Blanking

FIG1 4mS

FIG2 2mS
Expanded from above

FIG3 100uS

Blanking Expanded from above

Area for Set Up Set-Up adjustment

345V p/p

FIG4 40uS

Area for Set-Dn adjustment

180 uSec

83

March 201 1

50PZ950

Plasma

Set Up and Set Down Adjustments

Y-Scan Test Point Upper Y-Drive Y Drive Set must be in WHITE WASH All other DC Voltage adjustments should have already been made.

Waveform Test Point Y-Drive Upper or Lower (Waveform TP)

VR401 B

SET-UP ADJUST: 1) Adjust VR402 and set the (A) portion of the signal to match the waveform above (345V p/p 5V) above. SET-DN ADJUST: 2) Adjust VR401 and set the (B) time of the signal to match the waveform above. (180uSec 5uSec)

A VR402

ADJUSTMENT LOCATIONS: Center of the board.

84

March 201 1

50PZ950

Plasma

Set Up/Down Adjustments Too High or Low

Set Up swing is Minimum 328V p/p Max 358V p/p Set Dn swing is Minimum 73uSec Max 196uSec Normal 180uSec This will cause The bottom of The picture to distort. 40V off the Floor Floor NOTE: If abnormal settings cause excessive brightness then shutdown, remove the LVDS from Control board and make necessary adjustments. Then reconnect LVDS cable, select White Wash and adjust correctly.

This will cause The black Portions of the Picture to Lighten. Black floor Up Up.

Too Low 88.8uSec

85

March 201 1

50PZ950

Plasma

Y-Drive Signal Checks

Y-SUS Board develops the Y-Scan drive signal to the Y-Drive boards Y Drive boards. This Section of the Presentation will cover troubleshooting the Y-SUS Board. Warning: Never run the Y-SUS with P213 removed unless the Y-Drive boards are removed completely.

TIP: Use C540 Left leg to check the Y-Scan signal if the Y-Drive boards are removed

P/N EBR69839001

TIP: Do not use C540 Left leg to adjust the Y-Scan signal.

86

March 201 1

50PZ950

Plasma

P102 Y-SUS Board Ribbon to Control P203 Voltage and Diode Test YP102 "Y-SUS" to P105 "Control" Pin Pi 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Label L b l CTRL_OE OE SUS_UP SUS_DN SET_DN
Slope_Rate_Sel Det_Level_Sel Ramp_Slope_Opt1

Run R 0.06V 0.02V 0.13V 2.84V 2.2V 0.05V 0.3V 0.06V 0.06V 0.11V 0 11V Gnd 0.09V 1.02V 0.35V 1.98V

Diode Ch k Di d Check Open 2.29V p Open Open Open Open Open Open Open Open Gnd Open Open Open Open

Pin Pi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Label L b l DATA_TOP OC1_TOP CLK STB OC1_BTM DATA_BTM OC2_BTM +18V +18V +18V M5V M5V M5V Gnd Gnd

Run R 0V 1.16V 0.46V 2.86V Gnd 0V 1.98V 18.34V 18.34V 18.34V 18 34V 4.89V 4.89V 4.89V Gnd Gnd

Diode Ch k Di d Check Open Open Open p Open Open Open Open 1.32V 1.32V 1.32V 1 32V 1.40V 1.40V 1.40V Gnd Gnd

SET_UP YER_UP YER UP Gnd YER_DN PASS_TOP DELTA_VY_DET OC2_TOP

Location: Location Bottom Right of board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

87

March 201 1

50PZ950

Plasma

P203 Y-SUS Board to Left X-Board P121 Voltage and Diode Test
Location: Bottom Right of board
P203

P203 "Y-SUS" to "X-Drive Left" P121 Pin 1~2 3 4~5 Label Gnd n/c Va Run Gnd n/c *55V Diode Check Gnd Open Open

To Left X-Board

* Note: This voltage will vary in accordance with Panel Label

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

88

March 201 1

50PZ950

Plasma

P210 Y-SUS Board to SMPS P811 Voltage and Diode Test

Location: Top Right of board
P210

P210 "Y-SUS" to "Power Supply" P811 Pin 1~2 3 4~5 6 Label Vs n/c Gnd Va M5V Run *201V n/c Gnd *55V 5.0V Diode Check Open n/c Gnd Open 1.38V

To SMPS

* Note: This voltage will vary in accordance with Panel Label

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

89

March 201 1

50PZ950

Plasma

P213 Y-SUS Board Connector to P213 Lower Y-Drive (Logic Signals)

TIP: This connector does not come with a new Y-SUS or Y-Drive. TIP: Use C540 Left leg to check the Y Scan signal if the Y Drive boards are removed Y-Scan Y-Drive

Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.
P213

P213 Y-SUS to Lower Y-Drive P213

Pin 1 2 3 4 5 6 7 8 9 10 11 12 Label M5V M5V OC2_B Gnd DATA_B Gnd OC1_B OC1 B OC2_T Gnd DATA_T Gnd OC1_T Gnd CLK STB Run 4.96V 4.96V 2.77V Gnd 0V Gnd 1.73V 1 73V 2.73V Gnd 0V Gnd 1.74V Gnd 0.68V 4.27V Diode Check 1.38V 1.38V Open Gnd 1.85V Gnd 1.85V 1 85V Open Gnd 1.85V Gnd 1.85V Gnd 1.85V 1.85V Diode Mode Readings taken with all connectors Di ll t Disconnected. t d DVM in Diode Mode.

All readings taken from Chassis Ground

Y-SUS Board

13 14 15

90

March 201 1

50PZ950

Plasma

P213 Y-SUS Board Connector Waveforms

Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.
P213

P213 Y-SUS to L Y SUS t Lower Y D i P213 Y-Drive

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Label M5V M5V OC2_B Gnd DATA_B Gnd G d OC1_B OC2_T Gnd DATA_T Gnd OC1_T Gnd G d CLK STB

Pin 3 (19.9V p/p)

Pin 10 (8.47V p/p)

Pin 5 (8.62V p/p)

Pin 12 (9V p/p)

Pin 7 (10.67V p/p)

Pin 14 (9.08V p/p)

Pin 8 (10.67V p/p)

Pin 15 (11.15V p/p)

All scope settings at 5mSec per/div / 5V per/div All signals taken from Chassis Ground

91

March 201 1

50PZ950

Plasma

P214 Y-SUS Board to Upper Y-Drive P111 Voltage and Diode Test
Location: Top Left of board
P111 P214

P214 "Y-SUS to Upper Y-Drive" P111 Pin Pi 3-12 1-2 Label L b l FGnd FG10.9V Run R FGnd 4.89V Diode Ch k Di d Check FGnd Open Diode Ch k Di d Check FGnd 0.55V Red Lead on Floating Gnd

Black Lead on Floating Gnd

All readings from Floating Ground di f Fl ti G d

Y-Drive Upper

Y-SUS Board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

92

March 201 1

50PZ950

Plasma

P215 Y-SUS Board to Upper Y-Drive P112 Voltage and Diode Test
Location: Bottom Left of board
P112 P215

P215 "Y-SUS" to "Upper Y-Drive" P112 Pin 9-12 8 1-7 Label Vscan n/c FGnd Run 107V n/c FGnd Diode Check Open n/c FGnd Diode Check Open n/c FGnd Red Lead on Floating Gnd

Black Lead on Floating Gnd

All readings from Floating Ground

Y-Drive Upper

Y-SUS Board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

93

March 201 1

50PZ950

Plasma

P216 Y-SUS Board to Lower Y-Drive P212 Voltage and Diode Test
Location: Bottom Left of board
P212 P216

P216 "Y-SUS" to "Lower Y-Drive" P212 Pin 11-12 1-10 Label Vscan FGnd Run 107V FGnd Diode Check Open FGnd Diode Check Open FGnd Red Lead on Floating Gnd

Black Lead on Floating Gnd All readings from Floating Ground g g

Y-Drive Upper

Y-SUS Board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

94

March 201 1

50PZ950

Plasma

P217 Y-SUS Board to Lower Y-Drive P211 Voltage and Diode Test
Location: Bottom Left of board
P211 P217

P217 "Y-SUS" to "Lower Y-Drive" P211 Pin 6-12 6 12 5 1-4 Label FGnd FG d n/c Vscan Run FGnd FG d n/c 107V Diode Check FGnd FG d n/c Open Black Lead on Floating Gnd Diode Check FGnd FG d n/c Open Red Lead on Floating Gnd

All readings from Floating Ground g g

Y-Drive Upper

Y-SUS Board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

95

March 201 1

50PZ950

Plasma

Y-SUS Board P218 to Z-SUS P203 Voltage and Diode Test

Location: Top Right of board
P218

P218 "Y-SUS" to "Z-SUS" P203 Pin 1~2 3 4~5 6 7~8 Label Gnd n/c +Vs n/c ER_PASS Run Gnd n/c *201V n/c *98V~102V Diode Check Gnd n/c Open n/c Open

* Note: This voltage will vary in accordance with Panel Label

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

96

March 201 1

50PZ950

Plasma

Y-SUS Floating Ground FG10.9V, FG23.77V and 18V Checks

Voltage Measurements for the Y-SUS Board
FG23.77V (Floating Ground). ( g ) Checked at Cathode of D512

Tip: M5V turns on these supplies. P201 FS202 M5V

Floating Ground checks must be measured from Floating Ground. Use pins 3 12 on P214 3~12 Note With No Y-Drives: FG23.77V reads 23.85VFG FG10.9V reads 11.2VFG

J32 10.9V

D511 FG10.9V

T502 FS201 VA D512 FG23.77V D515 FG18.34V

FG10.9V (Floating Ground). Checked at Cathode of D511. Leaves the Y-SUS board to Upper Y-Drive on P214 pins 1 and 2 18V (Chassis Ground). Checked at Cathode of D515. Leaves the Y-SUS board to Control board on P102 pins 6~8

Location

FS501 18V

J81 (CTRL_OE)

Tip: Remove board, Ground J81 (CTRL_OE) Jump any 5V supply to pin 7 of P210 or FS202 and it will turn on these supplies for test.

97

March 201 1

50PZ950

Plasma

Y-SUS (VSC and Vy) Generation Checks

Voltage Measurements for the Y-SUS Board Tip: VS turns on these supplies, but Floating Gnd 10.9V, 23.77V and Chassis Gnd 18V must be running.

VSC Source Test Point. Used Y-SUS Waveform development. Checked at Cathode Side of D504. Run: 158V Diode check: Open (Black lead on FGnd) 0.49V (Red lead on FGnd) D504 Cathode VSC Source

Location

T500

D505 Cathode +Vy Source

+Vy Source Test Point. Used Y-SUS Waveform development. Checked at Cathode Side D505. Run: 190V Diode check: Open (Black lead on FGnd) 0.56V (Red lead on FGnd)

Floating Ground checks must be measured from Floating Ground. p Use pins 3~12 on P214

98

March 201 1

50PZ950

Plasma

Y-SUS Board Fuse Information

Locations
Board Disconnected Diode Ch k Di d Check readings di FS203 VS or FS201 Va Open Red Lead on FG Open Blk Lead on FG p (FS202) M5V 0.54V Red Lead on FG 1.4V Blk Lead on FG (FS501) 18V 0.62V Red Lead on FG 1.32V Blk Lead on FG

FS203 (VS) 6.3A / 250V

FS202 (M5V) 10A / 125V FS201 (VA) 4A / 125V

Board Connected Diode Check readings FS201 Va or FS203 Vs Open FS202 M5V 0.73V

FS501 (18V) 2A / 125V

FS501 18V 1.28V

99

March 201 1

50PZ950

Plasma

Y-SUS FET Identification and Location

P218
J33
D S

Q502
G

D503

T500

D505

P214

IC501 D501

IC500

HS601
P215

D512 D515 IC302

Q609
Position Direction D610 HS601 Forward Reverse D604,D605 HS602 Forward Reverse D602 HS603 Forward Reverse 0.35V ~ 0.45V Circuit No. Q606,Q607 Q608,Q609

Q605 Q612 D602

C540

HS602
D608

Q608 D604 Q601

0.35V ~ 0.45V 0.45V ~ 0.55V 0.45V ~ 0.55V O.L. (Overload) Q601,Q602 0.45V ~ 0.55V
P217

O.L. (Overload) Q603,Q605 Q610,Q612 0.4V ~ 0.5V

P216

Y-SUS EBR69839001

0.35V ~ 0.45V 0.35V ~ 0.45V O.L. (Overload)

T502

HS603

D511

Q602 D605

Q610 Q603

Q606 Q607 D610

P102
D609

P203

P213

100

March 2011

50PZ950

Plasma

P210

D500

Y-DRIVE BOARD SECTION (Y-Drive Explained) (YY-DRIVE UPPER (TOP) Y-DRIVE LOWER (BOTTOM)

Y-Drive Boards work as a path supplying the Sustain and Reset waveforms which are made in the Y-Sustain board and sent to the Panel through Scan Driver ICs. The Y-Drive Boards receive a waveform (Y-Drive) developed on the Y-SUS board then selects the Y SUS horizontal electrodes sequentially starting at the top and scanning down the panel. Scanning is synchronized by receiving Logic scan signals from the Control board. The 50PZ950 uses 12 Driver ICs on 2 Y-Drive Boards commonly called Y-Drive Buffers but are actually Gate Arrays connected to 1080 horizontal electrodes across the panel. This model also does something new, Monitor 5V is sent to the Lower Y-Drive where the low voltage Data Buffer are located. Also, The upper Y-Drive receives FG10.9V and , pp regulates it down to FG5V for the upper and routed down to the lower Y-Drive buffers.

101

March 201 1

50PZ950

Plasma

Y-Drive Upper Layout

PANEL SIDE Y-SUS SIDE

p/n: EBR69839101

The upper Y-Drive is responsible for driving the upper half of the panels horizontal electrodes with Y-Scan signals through the Panels Flexible printed circuits. (540 horizontal electrodes). The Upper Y Drive is also responsible for developing Y-Drive the FG5V operational voltage for both Drive boards. It receives FG10.9V from the Y-SUS on P111 pins 11~12 and routs this voltage to IC191 which regulates it down to 5VFG. The Upper Y-Drive then delivers the 5VFG to all the buffers for their low voltage signal processing circuits. The 5VFG is also sent down to the lower Y-Drive via p pins 1~9 for the lower P121 pins 21~30 to P221 p Y-Drive buffers.

P111

Warning: Never run the Y-SUS with just P121 di ith j t disconnected. t d You must remove the Upper Y-Drive board completely.

P112 P121

102

March 201 1

50PZ950

Plasma

Y-Drive Upper Floating Ground 5V Regulator (5VFG)

Floating Ground checks must be measured from Floating Ground. Use pins 3~12 on P214

Q191 D191
Pin 1 1 3 3

IC191 (1) 5VFG (2) FGnd (3) 10.9VFG Diode Check 0.42V 2.19V 0.63V 2.79V Red Lead on FGnd Blk Lead on FGnd Red Lead on FGnd Blk Lead on FGnd

P111

The Upper Y-Drive is also responsible for developing the FG5V operational voltage for both Drive boards. It receives FG10.9V from the Y-SUS on P111 pins 11~12 and routs this voltage to IC191 which regulates it down to 5VFG. 5VFG D191 Anode 5VFGnd Cathode 10.9VFGnd C th d 10 9VFG d A C

P112

103

March 201 1

50PZ950

Plasma

P111 Upper Y-Drive to Y-SUS Board P214 Voltage and Diode Test
Location: Top Right hand connector
P111 P214

Upper Y-Drive P111 to Y-SUS Board P214 Pin Pi 11-12 1-10 Label L b l FG10.9V FGnd Run R 4.89V FGnd Diode Ch k Di d Check Open FGnd Diode Ch k Di d Check 0.5V FGnd Red Lead on Floating Gnd

Black Lead on Floating Gnd

All readings from Floating Ground di f Fl ti G d

Y-Drive Upper

Y-SUS Board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

104

March 201 1

50PZ950

Plasma

P112 Upper Y-Drive to Y-SUS Board P215 Voltage and Diode Test
Location: Bottom Left of board
P112 P215

Upper Y-Drive P112 to Y-SUS Board P215 Pin 6-12 5 1-4 Label FGnd n/c Vscan Run FGnd n/c 107V Diode Check FGnd n/c Open Diode Check FGnd n/c 1.54V Red Lead on Floating Gnd

Black Lead on Floating Gnd

All readings from Floating Ground

Y-Drive Upper

Y-SUS Board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

105

March 201 1

50PZ950

Plasma

Y-Drive Lower Layout

PANEL SIDE

p/n: EBR69839201

P221 P211 P212

Y-SUS SIDE

Warning: Never run the set with just P213 disconnected. You must remove the Lower and Upper Y-Drive boards completely. Never run the set with P221 unplugged unless you remove the Upper Y-Drive board completely.

P213

The Lower Y-Drive is responsible for driving the bottom half of the panels 540 horizontal electrodes with Y-Scan signals through the Panels Flexible printed circuits. It receives FG5V from the Upper Y-Drive on P221 pins 21~30 from P121 pins 1 9 for the lower 21 30 1~9 Y-Drive buffers low voltage signal processing. Another new development is that the lower Y-Drive board receives Chassis Ground and M5V P213 pins 14 and 15 f th D t b ff d for the Data buffers. Th Y S The Y-Scan logic l i signals are also related to chassis ground and the Data buffers distribute the Y-Scan logic data to all the Buffers, (Gate arrays) on pp the upper and lower Y-Drive boards. These signals are routed to the Upper Y-Drive through P221 to P121 on the upper.

106

March 201 1

50PZ950

Plasma

P211 Lower Y-Drive to Y-SUS Board P217 Voltage and Diode Test
Location: Bottom Left of board
P211 P217

P211 Lower Y-Drive" to Y-SUS" P217 Pin 9-12 9 12 8 1-7 Label Vscan V n/c FGnd Run 107V n/c FGnd Diode Check Open O n/c FGnd Black Lead on Floating Gnd Diode Check 1.54V 1 54V n/c FGnd Red Lead on Floating Gnd

All readings from Floating Ground g g

Y-Drive Upper

Y-SUS Board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

107

March 201 1

50PZ950

Plasma

P212 Lower Y-Drive to Y-SUS Board P216 Voltage and Diode Test
Location: Bottom Left of board
P212 P216

Y-Drive P212 to Y-SUS Board P216 Pin 3-12 1-2 Label FGnd Vscan Run FGnd 107V Diode Check FGnd Open Diode Check FGnd 1.54V Red Lead on Floating Gnd

Black Lead on Floating Gnd All readings from Floating Ground g g

Y-Drive Upper

Y-SUS Board

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

108

March 201 1

50PZ950

Plasma

P213 Lower Y-Drive to Y-SUS Board P213 Connector (Logic Signals)

TIP: This connector does not come with a new Y-SUS or Y-Drive. TIP: Use C540 Left leg to check the Y Scan signal if the Y Drive boards are removed Y-Scan Y-Drive

Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.
P213 "Y-SUS" to "Lower "Y-Drive" P213 Pin Label Run Diode Check 15 M5V 4.89V 1.9V 14 M5V 4.89V 1.9V 13 OC2_B 2.63V 2.08V 12 Gnd Gnd Gnd 11 DATA_B 0V 2.08V 10 Gnd Gnd Gnd 9 OC1_B 2.2V Open 8 OC2_T 2.2V 2.08V 7 Gnd Gnd Gnd 6 DATA_T 2.8V 2.08V 5 Gnd Gnd Gnd 4 OC1_T 0.86V 2.34V 3 Gnd Gnd Gnd 2 CLK FG 2.08V 1 STB 4.9V 2.08V Red Lead Black Lead on Chassis Gnd on pin Diode Check 0.55V 0.55V 0.63V Gnd 0.63V Gnd 0.63V 0.63V Gnd 0.63V Gnd 0.63V Gnd 0.63V 0.63V Black Lead on pin

P213

P213

Lower Y-Drive

Y-SUS Board

All voltage readings taken from Chassis Ground

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

109

March 201 1

50PZ950

Plasma

Lower Y-Drive Board P213 Connector Waveforms

Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.
P213

P213 Y-SUS to L Y SUS t Lower Y D i P213 Y-Drive

Pin Pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Label Label M5V M5V OC2_B Gnd DATA_B DATA B Gnd OC1_B OC2_T Gnd DATA_T Gnd OC1_T OC1 T Gnd CLK STB

Pin 13 (19.9V p/p)

Pin 6 (8.47V p/p)

Pin 11 (8.62V p/p)

Pin 4 (9V p/p)

Pin 9 (10.67V p/p)

Pin 2 (9.08V p/p)

Pin 8 (10.67V p/p)

Pin 1 (11.15V p/p)

All scope settings at 5mSec per/div / 5V per/div All signals taken from Chassis Ground

1 10

March 201 1

50PZ950

Plasma

Removing (Panel) Flexible Ribbon Cables from Y-Drive Upper or Lower Some pictures are from a different model, but the process is the same.
To T remove the Ribbon C bl f th Ribb Cable from th connector fi t carefully lift the Locking T b f the t first f ll th L ki Tab from the back and tilt it forward ( lift from under the tab as shown in Fig 1). The locking tab must be standing straight up as shown in Fig 2. Lift up the entire Ribbon Cable gently to release the Tabs on each end. (See Fig 3) y Gently slide the Ribbon Cable free from the connector.
Be sure ribbon tab is released By lifting the ribbon up slightly, before removing ribbon.

Gently Pry Up Here

Locking tab in upright position

Fig 1

Fig 2

Fig 3

To reinstall the Ribbon Cable, carefully slide it back into the slot see ( Fig 3 ), be sure the Tab is seated securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1).

11 1

March 201 1

50PZ950

Plasma

Incorrectly Seated Y-Drive Flexible Ribbon Cables

The Ribbon Cable is clearly improperly seated into the connector. You can tell by observing the line of the connector compared to the FPC, they should be parallel. p The Locking Tab will offer a greater resistance to closing in the case. Note the cable is crooked in this case because the Tab on the Ribbon cable was improperly seated at the t t d t th top. Thi can cause bars, lines, This b li intermittent line and other abnormalities in the picture. Remove the ribbon cable and re-seat it correctly.

1 12

March 201 1

50PZ950

Plasma

Y-Drive Buffer Troubleshooting

HOW TO CHECK FOR A SHORTED BUFFER IC
BACK SIDE FRONT SIDE BUFFER IC FLOATING GROUND (FGnd) Using the Diode Test on the DVM, check the pins for shorts or abnormal loads.

RED LEAD On BLACK LEAD On ANY Floating Ground Output Lug Reads 0.78V y Indicated by white outline Reversing the leads reads Open

FRONT SIDE OF Y-DRIVE BOARD

8 Ribbon cables communicating with the Panels (Horizontal Panel s Electrodes) totaling 1080 lines determining the Panels Vertical resolution pixel count.

Any of these output lugs can be tested. Look for shorts indicating a defective Buffer IC

1 13

March 201 1

50PZ950

Plasma

Z-SUS SECTION
This Section of the Presentation will cover troubleshooting the Z-SUS Board Assembly. Upon completion of this section the Technician will have a better understanding of the circuit and be able to locate test points needed for troubleshooting and all alignments.

Locations

DC Voltage and Waveform Test Points Z BIAS Alignment Diode Mode Test Points

Operating Voltages
Power Supply Supplied VS pp y pp M5V Y-SUS Y SUS Supplied Developed on Z-SUS 18V
Routed through the Y-SUS then to the Control Board then to the Z-SUS Generated on the Y-SUS then to the Control Board then to the Z-SUS. Control board does not use the 18V.

Z Bias
March 201 1 50PZ950 Plasma

1 14

Z-SUS Block Diagram

VS

Y-SUS Board
18V M5V M5V

Power Supply Board

VS

Control Board
M5V

18V Receives Logic Signals for wave shape development

Z-SUS board receives VS from the Y-SUS and M5V and 18V from the Y-SUS routed through the Control board
VS Via 3 FPC VZB

M5V, 18V

Circuits generate erase, sustain waveforms

ER_UP ER_DN _ SUS_UP SUS_DN

Generates VZB (Z Bias) G ( ) 130V driving the output FETs.

+VZB

Flexible Printed Circuits

(NO IPMs)

Z-SUS Out Waveform

PDP Display Panel P l

Z-SUB

FET Makes Drive waveform

Simplified Block Diagram of Z-SUS (Sustain) Board Z SUS

1 15

March 201 1

50PZ950

Plasma

Z-SUS Board Component Identification

P203 VS from SMPS FS201 VS 6.3A/250V VZB Adj VR101 Z-SUS Output FETs Z-SUS Waveform Test P i t T t Point J54 No IPMs P204

VZB TP Across R156

Z-SUS Waveform Development FETs

P/N EBR71727901
FS202 M5V 4A/125V

P205 05 M5V from SMPS to the Y-SUS, +18V generated on the Y-SUS are routed through the Control board. Logic Signals generated on the Control board.

To Z-SUB P201 P206

1 16

March 201 1

50PZ950

Plasma

50PZ950 Z-SUS Board Drawing

P203
P203 7-8) Gnd 6) n/c 4-5) VS 3) n/c 1-2) ER
1-2) ER 3) n/c 4-5) VS 6) n/c 7-8) Gnd

57VRMS 100uSec 261V p/p

Example:
Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.A. / -190 / 150 / N.A. / 130 Max Watt : 360 W (Full White)

VR101 VZB Adj

FS201 (VS) 6.3A / 250V

Q104
VZB TP R156

Q109 Q106 D118

Q113 Q114 D110

VZB (Z Bias)

To run the Z-SUS stand-alone: Jump VS from SMPS to pins 4 or 5 of P203. Jump +5V from SMPS to fuse FS202. Jump 17V from SMPS to J21. Leave Connector P201 connected to Control Board. J54 290V p/p (More square shape).
P201
1-2) 18V 3) n/c 4-5) M5V 6-7) Gnd 8) SUS_DN 9) CTRL_EN 10) SUS_UP 11) VZB2 12) ER_DN 13) VZB1 14) ER_UP 15) ZBIAS 18.34V (n/c) 4.89V Gnd 0.73V 0.06V 0.15V 2.49V 0.1V 2.53V 0.11V 1.89V
ER_UP ER_DN SUS_DN

50V 2MSec 288V p/p

Q102
Gnd Gnd

Z-SUS EBR71727901
P204 D114 Q107 Q110
Z-Drive J54 Waveform

J21 18V

D111 D108 Q103

J16 M5V

FS202 (M5V) 4A / 125V

FS202

P205

P201 P206

117

March 2011

50PZ950

Plasma

Z-SUS Waveform
The Z-SUS (in combination with the Y-SUS) generates a g g g SUSTAIN Signal and an ERASE PULSE for generating SUSTAIN and DISCHARGE in the Panel. This waveform is supplied to the panel through Z-SUB and then to FPC (Flexible Printed Circuit) connections P201, P202 and P203.
Reset Location: Center Right of Z-SUS board

Y Drive Waveform Blanking

Oscilloscope Connection Point. J54 to check Z Output waveform. Right Hand Side Center.

Z Drive Waveform Blanking

VZB VR101 manipulates the offset of the Z-Drive waveform segment. VZB (Z-Bias) voltage 130V 1/2V

TIP: The Z-Bias (VZB) Adjustment is a DC level adjustment. This is only to show the effects of Z-Bias on the waveform.

This Waveform is just for reference to observe the effects of Z Bias adjustment

1 18

March 201 1

50PZ950

Plasma

Z-Bias (VZB) VR101 Adjustment

Location Top Left of Z-SUS Board

Example of a voltage label: Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.A. 190 N A / -190 / 150 / N A / 130 N.A. Max Watt : 360 W (Full White)
VZB (Z-Bias)

Read the Voltage Label on the back top center of the panel when adjusting VR101.

VZB (Z-Bias) Adjust VR101

Negative Lead VZB (Z Bias) R156 Positive Lead

Set h ld S t should run for 10 minutes, f i t this is the Heat Run mode. Set screen to White Wash mode or 100 IRE White input. Adjust VR101 VZ (Z-Bias) while reading across R156 to match your Panels Voltage Label ( 1/2V)

1 19

March 201 1

50PZ950

Plasma

P203 Z-SUS Connector to Y-SUS P218 Voltages and Diode Checks

Voltage and Diode Mode Measurements

P203 "Z-SUS to "Y-SUS" P218 Pin 1~2 3 4~5 5 6 7~18 Label ER_PASS n/c +Vs s n/c Gnd Run *98V~102V n/c *201V 0 n/c Gnd Diode Check Open n/c Ope Open n/c Gnd

P203 Location: Top Left of Board

Pin 1

* Note: This voltage will vary in accordance with Panel Label

There are no Stand-By voltages on this connector

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

120

March 201 1

50PZ950

Plasma

P201 Z-SUS Connector to Control P2 Voltages and Diode Checks

Voltage and Diode Mode Measurements P201 "Z-SUS Board" to P2 "Control" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Label +18V +18V n/c +5V (M5V) +5V (M5V) Gnd Gnd SUS_DN CTRL_EN SUS_UP VZB2 ER_DN VZB1 ER_UP ZBIAS Run 18.34V 18.34V n/c 4.89V 4.89V Gnd Gnd 0.73V 0.06V 0.15V 2.49V 0.1V 2.53V 0.87V 1.9V Diode Check Open Open 1.52V 1.52V 1.52V Gnd Gnd Open Open Open Open Open Open p Open Open
Pin 1 FS202 M5V 4A/125V J21 18V

There are no Stand-By voltages on this connector

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

P201 Location: Bottom Left hand side

121

March 201 1

50PZ950

Plasma

50PZ950 Z-SUS Board FET Locations

P203
1-2) ER 3) n/c 4-5) VS 6) n/c 7-8) Gnd

Z-SUS EBR71727901

FS201 (VS) 6.3A / 250V

HS101
Q109 Q106 D118

Q104 Q113
Position Direction D114,D118 HS101 Forward Reverse D109,D110,D108,D111 HS102 Forward Reverse 0.35V ~ 0.45V 0.35V ~ 0.45V Circuit No. Q107,Q110 0.35V ~ 0.45V O.L. (Overload) Q104,Q113,Q114 0.5V ~ 0.6V O.L. (Overload) Q102,Q103 0.4V ~ 0.55V Q106,Q109 0.35V ~ 0.45V

Q114 D110

HS102
Q102 D111 D108 FS202 Q103 D114 Q107 Q110 P205 P204

P201 P206

122

March 2011

50PZ950

Plasma

How to Check the Z-SUS Stand-Alone

The Power Supply should be producing VS or you can substitute voltage matching VS from an external source to either pin 1 or 2 P102 on the Z-SUS board. The Power Supply should be producing M5V or you can substitute Stand-By 5V or any 5V from an external source to the 5V Fuse on the Z-SUS (FS202). Note: The 5V will be routed back to the Control Board for power through the P201 to P2 connector. (For 5V on the SMPS use J26). pp y producing 17V or y can substitute voltage matching 17V from an external g you g g The Power Supply should be p source to either pins 1 or 2 on connector P2 on the Control board. (For 17V on the SMPS use J63).
1) Disconnect P811 5) Turn on the set and check for 221V p/p waveform on Z-SUS Board

5V J26 17V J63

2) Disconnect P105 3) Jump STBY5V to FS202 on Z-SUS (M5V Fuse)

4) Jump 17V to jumper J21 on Z-SUS Board

Tip: If the DC to DC converter generating 18V is running on the Y-SUS you can jump any 5V to the Y-SUS M5V Y-SUS, input pin, leave P105 connected and there will be no need to jump the 17V or the M5V to the Z-SUS.

123

March 201 1

50PZ950

Plasma

CONTROL BOARD SECTION

This Section of the Presentation will cover troubleshooting the Control Board Assembly. Upon completion of this section the Technician will have a better understanding of the circuit and be able to locate test points needed for troubleshooting.

DC Voltage and Waveform Test Points Diode Mode Test Points

Signals
Main Board Supplied Panel Control and LVDS (Video) Signals Control Board Generated Y-SUS and Z-SUS Drive Signals (Sustain) Y SUS Z SUS Y-Drive Board Scan Signals (Gate Address) X Board Drive Signals (RGB Address) Operating Voltages Y-SUS Supplied +5V (M5V) Developed on the SMPS +18V (Routed to the Z-SUS)
(Not used by the Control Board)

Developed on the C Control Board +1.0V (IC61) for internal use +1.8V (IC52) for internal use. Silk screened as IC25. +3.3V (IC51) for LVDS Power +3.3V (IC53) for the X-Boards (TCPs) 124 March 201 1 50PZ950 Plasma

Control Board Component Identification

p/n: EBR71727801

125

March 201 1

50PZ950

Plasma

50PZ950 Control Board Layout Drawing

18V To Z-SUS (In P105 pins 23-25) (Out P2 pins 14-15) Diode Check All Connectors Connected 1.28V

P2
P2 To Z-SUS Board FL5 IC61
M5V

IC25 1) 0.8V 2) Gnd 3) 4.87V 4) 6.46V 8) 2.95V 7) 1.85V 6) 1.85V 5) 4.82V

P105
C61

C52

4.89V

P22 N/C

18V Pins 23-25 M5V Pins 26-28 FL1/FL2 FL5 Diode Check All Connectors Connected 0.73V

To Y-SUS Board

4.89V

IC25

IC101

IC102

3) 4.93V 2) 3.29V 1) Gnd

1.04V

IC51

M5V

1.85V

L1
D1 Blinks Indicating Board is Functioning
1.04V 1.04V

C76

3.26V

14-15) 18V 13) n/c 11-12) M5V 9-10) Gnd 08) SUS_DN 07) CTRL_EN 06) SUS_UP 05) VZB2 04) ER_DN 03) VZB1 02) ER_UP 01) ZBIAS

18.34V (n/c) 4.89V Gnd 0.73V 0.06V 0.15V 2.49V 0.1V 2.53V 0.11V 1.89V

FL1/2
1-4 (3.3V) IC53

L2
C65

1.84V

VS-DA TP

1.84V 3.3V

D1 IC11
1.63V 25 Mhz

IC1

CONTROL BOARD p/n: EBR71727801

AUTO Gen

To Main Board

IC61 05) 3.29V 06) 3.29V 07) 3.28V 08) 3.32V 04) 5.75V 03) 1.88V 02) Gnd 01) 0.8V

Gnd 3.26V 1.69V P101 Gnd X1 To Left 0.02V 0.65V X Board

Q1

1-4 (3.3V) IC53

C72

4.89V

P102
To Center X Board
3) 4.89V 2) 3.3V 1) Gnd

IC53

1-4 (3.3V) IC53

P104
To Right X Board

P31 LVDS

3.3V To X-Boards Diode Check All Connectors Connected 0.6769V

126

March 2011

50PZ950

Plasma

Control Board Temperature Sensor Location (Chocolate)

BACK SIDE OF THE BOARD

The panel is monitored for temperature. The panels temperature is transferred through the (Chocolate) to the Temp. Sensor on the back of the board. With Chocolate (Heat Transfer Material) Covering the Temp IC. The Chocolate (Heat Transfer Material) ( ) may stick to the Panel. Be sure to put it in the right place if the board is removed.

CONTROL BOARD LOCATION

Pin 1 IC103 04) 3.3V 03) Gnd 05) Gnd 02) Gnd 06) 3.3V 01) 3.3V

CONTROL BOARD TEMPERATURE SENSOR LOCATION

127

March 201 1

50PZ950

Plasma

Control Board TP Tips

EXTERNAL TRIGGER: (VS_DA) can be used as an External Trigger for your scope when locking onto the Y-Scan or the Z-Drive signal.
VS_DA

AUTO GEN

Auto Gen (Internal Automatic Generator) Short these two pins together to generate patterns on the screen f a Panel Test. for P lT t If patterns do not appear, try removing the LVDS Cable.

128

March 201 1

50PZ950

Plasma

Checking the Crystal X1Clock on the Control Board

Check the output of the Oscillator (Crystal) X1. The frequency of the sine wave is 25 MHZ. Missing thi l k i Mi i this clock signal will h lt operation of th panel l ill halt ti f the l drive signals.
Osc. Check: 25Mhz Top Leg

X1

Osc. Check: 25Mhz Bottom Leg

CONTROL BOARD CRYSTAL LOCATION

129

March 201 1

50PZ950

Plasma

Control Board Signal (Simplified Block Diagram)

The Control Board supplies Video Signals to the TCP (Taped Carrier Package) ICs. If there is a bar defect on the screen, it could be a Control Board problem.

Control Board to X Board Address Signal Flow

This Picture shows Signal Flow Distribution to help determine the failure depending on where the problem appears on the screen.

Basic Diagram of Control Board

CONTROL BOARD

MCM IC1
To Y-SUS

DRAM DRAM

To ZSUS To Main

The Control board also sends 3.3V to the TCPs. And the X-Board Data Buffers
IC101, IC301, IC301

Data Buffer IC
Resistor Array

X-DRIVE BOARD

MCM IC1
To Left XBoard To Center X-Board

16 bit words RGB Data Shown 3 Buffer Outputs per TCP 128 Lines per Buffer 384 Lines output Total

PANEL There are 15 total TCPs. 5 per/X-Board 5760 Vertical Electrodes 1920 Total Pixels (H) ( )

IC53
3.3V to TCPs

To Ri ht T Right X-Board

130

March 201 1

50PZ950

Plasma

Control Board Connector P105 to Y-SUS P102 Information

Pins are very close together. Use Caution when taking Voltage measurements.
Pin

P105 Label Silk Screen

All the rest are delivering Y-SUS Waveform development and Y-Drive logic signals to the Y-SUS Board. Y-Drive logic signals are simply routed right through the Y-SUS to the Y-Drive boards.

Pins 23 through 25 Receive 18V from the Y-SUS. Pins 26 through 28 Receive M5V from the Y-SUS. Note: The +18V is not used by the Control board, is C t l b d it i routed t the t d to th Z-SUS leaving on P2 Pins 14~15. Note: This silk screen and the actual pin function are not correct. See P105 Connector Voltages and Diode Check from more details.

131

March 201 1

50PZ950

Plasma

Control P105 to Y-SUS P102 Plug Information

P105 "Control" to P102 "Y-SUS" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Label CTRL_OE OE SUS_UP SUS_DN SUS DN SET_DN
Slope_Rate_Sel Det_Level_Sel Ramp_Slope_Opt R Sl O t

Pin 1 on Control is Pin 50 on Y-SUS. Note: There are no voltages in Stand-By mode Run 0V 1.16V 0.46V 2.86V 2 86V Gnd 0V 1.98V 18.34V 18 34V 18.34V 18.34V 4.89V 4.89V 4.89V Gnd Gnd Diode Check 2.81V 2.84V Gnd Gnd Gnd Gnd 2.98V Open O Open Open Open Open Open Gnd Gnd

Run 0.06V 0.02V 0.13V 2.84V 2 84V 2.2V 0.05V 0.3V 0.06V 0 06V 0.06V 0.11V Gnd 0.09V 1.02V 0.35V 1.98V

Diode Check 2.84V 2.84V 2.82V 2.83V 2 83V 2.82V 2.82V 2.82V 2.81V 2 81V 2.82V 2.81V Gnd 2.81V 2.84V 2.81V 2.84V

Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Label DATA_TOP OC1_TOP CLK STB OC1_BTM DATA_BTM OC2_BTM +18V +18V +18V M5V M5V M5V Gnd Gnd

SET_UP ER_UP Gnd ER_DN BLOCKING DELTA_VY_O OC2_TOP

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

132

March 201 1

50PZ950

Plasma

Control Board LVDS P31 Signals

LVDS Cable P31 on Control board shown. Flip up the locking mechanism to unlock.

Video Signals from the Main Board to the Control Board are referred to as Low Voltage Differential Signals or LVDS. The video is delivered in dual 24 bit LVDS format. Their presence can be confirmed with the Oscilloscope by monitoring the LVDS signals with SMPTE Color Bar input. Loss of these Signals would confirm the failure is on the Main Board or the LVDS C bl it lf Cable itself.
Example of LVDS Video Signal (613mV p/p)

10Msec

LVDS
2Msec

Example of Normal Signals measured at 100mV per/div Pins 12~17, 22~25, 28~33, 38~41, 44~49, 60~65, 70~73 are video. Pins 19~20, 35~36, 51~52, 67~68 are Clock signals for synchronizing.

Pins are close together.

Pin 79 is active high when the set is placed into 3D mode.

133

March 201 1

50PZ950

Plasma

Control Board LVDS P31 Connector Voltages and Diode Check

P31 LVDS "Control" to P3200 "Main"
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Label Gnd G d PC_SER_CLK Run Gnd G d 3.29V Diode Check Gnd G d 2.55V 2.55V 2.55V 2.55V 2.55V n/c n/c n/c n/c Gnd Gnd 1.05V 1.05V 1.05V 1.05V 1.05V Gnd 1.05V 1.05V Gnd 1.05V 1 05V 1.05V 1.05V 1.05V Gnd Pin 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Label Gnd G d *RA2*RA2+ *RB2*RB2+ *RC2*RC2+ Gnd Run Gnd G d 1.21V 1.12V 1.22V 1.12V 1.24V 1.09V Gnd Diode Check Gnd G d 1.05V 1.05V 1.05V 1.05V 1.05V 1.05V Gnd 1.05V 1.05V Gnd 1.05V 1.05V 1.05V 1.05V Gnd Gnd 1.05V 1.05V 1.05V 1.05V 1.05V 1 05V 1.05V Gnd 1.05V 1.05V Gnd Pin 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Label *RD3*RD3 *RD3+ *RE3*RE3+ Gnd Gnd *RA4*RA4+ *RB4*RB4+ *RC4*RC4+ Gnd RCLK4RCLK4+ Gnd *RD4*RD4+ *RE4*RE4+ Gnd n/c n/c UART_RDX_12P UART_TDX_12P VS_3D Gnd Run 1.22V 1 22V 1.12V 1.21V 1.12V Gnd Gnd 1.19V 1.13V 1.20V 1.14V 1.21V 1.10V Gnd 1.17V 1.19V Gnd 1.28V 1.13V 1.23V 1.11V Gnd n/c n/c 3.29V 3.29V 0V (3.29V 3D) Gnd Diode Check 1.05V 1 05V 1.05V 1.05V 1.05V Gnd Gnd 1.05V 1.05V 1.05V 1.05V 1.05V 1.05V Gnd 1.05V 1.05V Gnd 1.05V 1.05V 1.05V 1.05V Gnd n/c n/c 3.11V 3.11V 2.23V Gnd

P31

PC_SER_DATA 3.28V SCL DISP_EN SDA n/c n/c n/c n/c Gnd *RA1*RA1+ *RB1*RB1+ *RC1*RC1+ Gnd RCLK1RCLK1+ Gnd *RD1 RD1*RD1+ *RE1*RE1+ Gnd 3.23V 3.29V 3.23V n/c n/c n/c n/c Gnd 1.22V 1.11V 1.21V 1.13V 1.17V 1.17V Gnd 1.15V 1.18V Gnd 1.21V 1 21V 1.12V 1.22V 1.12V Gnd

RCLK2- 1.16V RCLK2+ 1.18V Gnd *RD2*RD2+ *RE2*RE2+ Gnd Gnd *RA3*RA3+ *RB3*RB3+ *RC3 RC3*RC3+ Gnd Gnd 1.21V 1.12V 1.21V 1.12V Gnd Gnd 1.13V 1.13V 1.22V 1.12V 1.15V 1 15V 1.17V Gnd

RCLK3- 1.15V RCLK3+ 1.18V Gnd Gnd

* Indicates video signal Note: There are no voltages in Stand-By mode. Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

134

March 201 1

50PZ950

Plasma

Control Board P2 Connector Pin ID and Voltages

Voltage and Diode Mode Measurements for the Control Board. Note: There are no voltages in Stand-By mode. P2 Label

P2 "Control" to "Z-SUS Board" P201 Pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Label (+18V) (+18V) n/c M5V M5V Gnd Gnd SUS_DN CTRL_EN CTRL EN SUS_UP VZB2 ER_DN VZB1 ER_UP ZBIAS Run 18.34V 18.34V 18 34V n/c 4.89V 4.89V Gnd Gnd 0.73V 0.06V 0 06V 0.15V 2.49V 0.1V 2.53V 0.87V 1.9V Diode Check Open Open O 1.52V 1.52V 1.52V Gnd Gnd Open Open Open Open Open Open Open Open
P2

18V

M5V

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

135

March 201 1

50PZ950

Plasma

Control Board (EMI Filter) Explained

The two EMI Filters just to the bottom right of P105 and one just to the top left of P2 are surface mount mini devices which shunt high frequencies to ground. These high frequencies are generated on the SMPS, Y-SUS and Control Board. Each EMI filter has 4 pins as shown in the example. The left and right are the B+ route, the two side solder points are Chassis Gnd route Gnd.
FL1, FL2 and FL5 (5V EMI filters)

Gnd

5V

5V

Gnd G d

136

March 201 1

50PZ950

Plasma

P101 Connector "Control Board to Left X Board P110

P101 "Control to P110 "X-Left" Pin Label Run Diode Check 1 3.3V 3.28V Open 2 3.3V 3.28V Open 3 3.3V 3.28V Open 4 3.3V 3.28V Open 5 n/c n/c n/c 6 n/c n/c n/c 7 Gnd Gnd Gnd 8 TCP1_RSDS_A3N 1.18V 3.09V TCP1_RSDS_A3P 1.25V 9 3.08V 10 TCP1_RSDS_A2N 1.18V Open 11 TCP1_RSDS_A2P 1.25V Open 12 TCP1_RSDS_A1N 1.18V Gnd 13 TCP1_RSDS_A1P 1.25V 3.09V Gnd 14 Gnd Gnd RSDS_CLK_N0 15 1.34V 1.36V RSDS_CLK_P0 16 1.08V 1.32V Gnd 17 Gnd Gnd TCP2_RSDS_A3N 1.18V TCP2 RSDS A3N 1 18V 18 Gnd 19 TCP2_RSDS_A3P 1.25V 1.36V 20 TCP2_RSDS_A2N 1.18V 1.36V 21 TCP2_RSDS_A2P 1.25V 1.36V TCP2_RSDS_A1N 1.18V 22 1.36V 23 TCP2_RSDS_A1P 1.25V 1.36V Gnd 24 Gnd Gnd RSDS_CLK_N1 25 1.34V Gnd RSDS_CLK_P1 26 1.08V 1.36V Gnd 27 Gnd Gnd 28 TCP3_RSDS_A3N 1.18V 1.36V TCP3_RSDS_A3P 1.25V 29 TCP3 RSDS A3P 1 25V 1.32V 1 32V 30 TCP3_RSDS_A2N 1.18V Gnd Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Label
TCP3_RSDS_A2P TCP3_RSDS_A1N TCP3_RSDS_A1P Gnd TCP4_RSDS_A3N TCP4_RSDS_A3P TCP4_RSDS_A2N TCP4 RSDS A2N TCP4_RSDS_A2P TCP4_RSDS_A1N TCP4_RSDS_A1P Gnd RSDS_CLK_N3 RSDS_CLK_P3 Gnd TCP5_RSDS_A3N TCP5_RSDS_A3P TCP5_RSDS_A2N TCP5_RSDS_A2P TCP5 RSDS A2P TCP5_RSDS_A1N TCP5_RSDS_A1P

Gnd STB0 STB1 X_ER_DN0 X_SUS_DN0 CE1_0 CE2_0 P0C0 BLK0 Gnd

Run 1.25V 1.18V 1.25V Gnd 1.18V 1.25V 1.18V 1 18V 1.25V 1.18V 1.25V Gnd 1.34V 1.08V Gnd 1.18V 1.25V 1.18V 1.25V 1 25V 1.18V 1.25V Gnd 3.2V 3.2V 0.42V 0.42V 0.42V 0.42V 1.89V 1.89V 1 89V Gnd

Diode Check Open Open Open Gnd Gnd 1.36V 1.36V 1 36V 3.09V 3.08V Open Gnd Gnd 3.09V Gnd 1.36V 1.32V Gnd Gnd 1.36V 1.36V Gnd 1.36V 1.36V 1.32V Gnd 1.36V 1.36V 1.36V 1.32V 1 32V Gnd

1 4 1~4 3.3V

White hash marks count as 5

Note: There are no voltages in y Stand-By mode.

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

137

March 201 1

50PZ950

Plasma

P102 Connector "Control Board to Center X Board P310

White hash marks count as 5

1~4 3.3V
Note: There are no voltages in Stand-By mode.
P102 "Control to P310 "X-Cent"
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Label 3.3V 3.3V 3.3V 3.3V n/c n/c Gnd TCP6_RSDS_A3N TCP6_RSDS_A3P TCP6_RSDS_A2N TCP6_RSDS_A2P TCP6_RSDS_A1N TCP6_RSDS_A1P Gnd RSDS_CLK_N0 RSDS_CLK_P0 Gnd TCP7_RSDS_A3N TCP7_RSDS_A3P TCP7_RSDS_A2N Run 3.28V 3.28V 3.28V 3.28V n/c n/c Gnd 1.18V 1.25V 1.18V 1.25V 1.18V 1.25V Gnd 1.34V 1.08V Gnd 1.18V 1.25V 1.18V Diode Check Open Open Open Open n/c n/c Gnd 3.09V 3.08V Open Open Gnd 3.09V Gnd 1.36V 1.32V Gnd Gnd 1.36V 1.36V Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Label TCP7_RSDS_A2P TCP7_RSDS_A1N TCP7_RSDS_A1P Gnd RSDS_CLK_N1 RSDS_CLK_P1 Gnd TCP8_RSDS_A3N TCP8_RSDS_A3P TCP8_RSDS_A2N TCP8_RSDS_A2P TCP8_RSDS_A1N TCP8_RSDS_A1P Gnd TCP9_RSDS_A3N TCP9_RSDS_A3P TCP9_RSDS_A2N TCP9_RSDS_A2P TCP9_RSDS_A1N TCP9_RSDS_A1P Run 1.25V 1.18V 1.25V Gnd 1.34V 1.08V Gnd 1.18V 1.25V 1.18V 1.25V 1.18V 1.25V Gnd 1.18V 1.25V 1.18V 1.25V 1.18V 1.25V Diode Check 1.36V 1.36V 1.36V Gnd Gnd 1.36V Gnd 1.36V 1.32V Gnd Open Open Open Gnd Gnd 1.36V 1.36V 3.09V 3.08V Open Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Label Gnd RSDS_CLK_N3 RSDS_CLK_P3 Gnd TCP10_RSDS_A3N TCP10_RSDS_A3P TCP10_RSDS_A2N TCP10_RSDS_A2P TCP10_RSDS_A1N TCP10_RSDS_A1P Gnd STB4 STB5 X_ER_DN2 X_SUS_DN2 CE1_2 CE2_2 P0C1 BLK1 Gnd Run Gnd 1.34V 1.08V Gnd 1.18V 1.25V 1.18V 1.25V 1.18V 1.25V Gnd 3.2V 3.2V 0.42V 0.42V 0.42V 0.42V 1.89V 1.89V Gnd Diode Check Gnd Gnd 3.09V Gnd 1.36V 1.32V Gnd Gnd 1.36V 1.36V Gnd 1.36V 1.36V 1.32V Gnd 1.36V 1.36V 1.36V 1.32V Gnd

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

138

March 201 1

50PZ950

Plasma

P104 Connector "Control Board to Right X Board P310

White hash marks count as 5

1~4 3.3V
P104 "Control to P310 "X-Right"
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Label 3.3V 3.3V 3.3V 3.3V n/c n/c G d Gnd TCP11_RSDS_A3N TCP11_RSDS_A3P TCP11_RSDS_A2N TCP11_RSDS_A2P TCP11_RSDS_A1N TCP11_RSDS_A1P TCP11 RSDS A1P Gnd RSDS_CLK_NB RSDS_CLK_PB Gnd TCP12_RSDS_A3N TCP12_RSDS_A3P TCP12 RSDS A3P TCP12_RSDS_A2N Run 3.28V 3.28V 3.28V 3.28V n/c n/c G d Gnd 1.18V 1.25V 1.18V 1.25V 1.18V 1.25V 1 25V Gnd 1.34V 1.08V Gnd 1.18V 1.25V 1 25V 1.18V Diode Check Open p Open Open Open n/c n/c G d Gnd 3.09V 3.08V Open Open Gnd 3.09V 3 09V Gnd 1.36V 1.32V Gnd Gnd 1.36V 1 36V 1.36V Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Label TCP12_RSDS_A2P _ _ TCP12_RSDS_A1N TCP12_RSDS_A1P Gnd RSDS_CLK_N9 RSDS_CLK_P9 G d Gnd TCP13_RSDS_A3N TCP13_RSDS_A3P TCP13_RSDS_A2N TCP13_RSDS_A2P TCP13_RSDS_A1N TCP13_RSDS_A1P TCP13 RSDS A1P Gnd TCP14_RSDS_A3N TCP14_RSDS_A3P TCP14_RSDS_A2N TCP14_RSDS_A2P TCP14_RSDS_A1N TCP14 RSDS A1N TCP14_RSDS_A1P Run 1.25V 1.18V 1.25V Gnd 1.34V 1.08V G d Gnd 1.18V 1.25V 1.18V 1.25V 1.18V 1.25V 1 25V Gnd 1.18V 1.25V 1.18V 1.25V 1.18V 1 18V 1.25V Diode Check 1.36V 1.36V 1.36V Gnd Gnd 1.36V G d Gnd 1.36V 1.32V Gnd Open Open Open Gnd Gnd 1.36V 1.36V 3.09V 3.08V 3 08V Open Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Label Gnd

Note: There are no voltages in Stand-By mode.

Run Gnd 1.34V 1.08V Gnd 1.18V 1.25V 1.18V 8 1.25V 1.18V 1.25V Gnd 3.2V 3.2V 3 2V 0.42V 0.42V 0.42V 0.42V 1.89V 1.89V 1 89V Gnd Diode Check Gnd Gnd 3.09V Gnd 1.36V 1.32V G d Gnd Gnd 1.36V 1.36V Gnd 1.36V 1.36V 1 36V 1.32V Gnd 1.36V 1.36V 1.36V 1.32V 1 32V Gnd

RSDS_CLK_N11 RSDS_CLK_P11 Gnd TCP15_RSDS_A3N TCP15_RSDS_A3P TCP15 RSDS A2N C 5_ S S_ TCP15_RSDS_A2P TCP15_RSDS_A1N TCP15_RSDS_A1P Gnd STB4 STB5 X_ER_DN2 X_SUS_DN2 CE1_2 CE2_2 P0C1 BLK1 Gnd

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

139

March 201 1

50PZ950

Plasma

X BOARD (LEFT, RIGHT and CENTER) SECTION

The following section gives detailed information about the X boards. g g These boards deliver the Color information signal developed on the Control board to the TCPs, (Taped Carrier Packages). The TCPs are attached to the vertical FPCs, (Flexible Printed Circuits) which are attached directly to the panel. The X boards are the attachment points for these FPCs. These boards have no adjustment. The X-Boards receive their main B+ from: Originally developed on the Switch Mode Power Supply Va (Voltage for Address) is routed through the Y-SUS board and then to the Left X board via P203 pins 4~5. Va also leaves P120 and is sent to the Center X via P320 pins 1~2. p Then it leaves on P321 and goes to the Right X P320 pins 1~2. Control board develops 3.3V (IC53) and routes to each XBoard via ribbon connectors P110, P310 and P310. P110 P310
140 March 201 1 50PZ950 Plasma

X Board Additional Information

There are three X boards, the Left, Center and the Right , , g (As viewed from the rear of the set). The three X boards have very little circuitry, primarily a Data Buffer and some passive voltage dividers. They are basically signal and voltage p g y y g g routing boards. They route Va voltage to all of the Taped Carrier Packages (TCPs). Va is introduced to the Left X board first, then the Left X sends Va to the Center X and then the Center X sends Va to the Right X. They route the Logic (Color) signals from the Control board to all of the Taped Carrier Packages (TCPs). The X boards have connectors to 15 TCPs, 5 on each X-Board. There are a total of 15 TCPs and each TCP has 3 internal buffers, each buffer output 128 pins to the vertical electrodes. So there are a total of 45 buffers electrodes feeding the panels 5760 vertical electrodes. Divide 5760 by 3 to determine the horizontal resolution of the panel (1920).

141

March 201 1

50PZ950

Plasma

X Board TCP Heat Sink Warning

NEVER run the television with this heat sink removed. Damage to the TCPs will occur and cause a defective panel panel.

The Vertical Address buffers (TCP ) h b ff (TCPs) have one heat sink indicated by the arrow. It protects all 15 TCPs.

142

March 201 1

50PZ950

Plasma

TCP 3.3V B+ Check

For Connectors P101, P102 and P104 on the Control board, board see Control board section. 3.3V leaves on Pins 1~4 of all three connectors.

Warning: DO NOT attempt to run the set with the Heat Sink over the TCPs removed. Checking IC53 for 3.3V, use center pin or Top of component. IC53 4.98V 3.3V Gnd G d

With all connectors connected, place the Red Lead On 3.3V Diode Check (0.62V) Black L d O 3 3V Di d Ch k (0 33V) Bl k Lead On 3.3V Diode Check (0.33V) This also test Data ICs on X-Boards

3.3V for TCPs IC53 on Control Board

3.3V in on Pins 57 ~ 60 on any connector from the Control board

3.3V

Left X Board P110

3.3V

Center X Board P310

3.3V

Right X Board P310

3.3V 3 3V

3.3V 3 3V

All Connectors to All TCPs look very similar for the 3.3V test point. The trace at pins 14 and 38 of each connector. There will a small feed trough off pin 14 and 38 you can use for Test Points. Example here from P302. You can also note a Capacitor (C322 here) left side to identify Pin 38. You can only check for continuity back to IC53, you can not run the set with heat sink removed removed, unless you disconnect VA from the Y-SUS to the Left X-Board.

143

March 201 1

50PZ950

Plasma

X Board Layout Primary Circuit Diode Check

The three X-Boards have similar circuit layouts for the connections going to the TCPs, as shown below.

Va

Data Gnd Gnd 3.3V

3.3V Gnd Va

1 EC

50

Va2 EC

Testing a single X board. Disconnected for any other board. All TCPs Connected All TCPs Disconnected Red Lead On 3.3V Diode Check (Open) Red Lead On 3.3V Diode Check (Open) ( ) ( ) Black Lead On 3.3V Diode Check (0.38V) Black Lead On 3.3V Diode Check (0.58V) This also test Data ICs on X-Boards. This test the Data IC on X-Board. To Test EC. Do not run the set with the heat sink removed. Disconnect VA from all X-Boards by disconnecting Y-SUS. EC reads 27.76V. EC Diode Test: Red Lead on EC (Open). Black lead on EC (Open). TCPs connected or disconnected. VA test: Explained on page 131.

144

March 201 1

50PZ950

Plasma

TCP (Tape Carrier Package)

This shows the layout of the bottom ribbon cables connecting to the Panels Vertical electrodes, (Address Bus). Note that each ribbon cable has a solid state device called a TCP attached.
X Drive Board Frame e Rear pane Vertical Add el dress Front panel Horizo t ontal Address Va

Y-SUS Board

New Type of TCP

Logic X_B/D Control Board 3.3V 256 total lines TCP Taped Carrier Package ac age 128 lines 128 lines Chocolate 128 lines

Back side of TCP Ribbon

256 Vertical Electrodes

TCP Attached directly to Flexible cable

Long Black Heat Sink

145

March 201 1

50PZ950

Plasma

50PZ950 TCP 50 Pin Connector

Va: Comes from Y-SUS P203 4~5 Va: Comes In on:
Arrives Left X : P121 pins 1~2 Leaves to Center X P120 pins 1~2 Arrives Center X : P320 pins 1~2 Leaves to Right X P321 pins 1~2 Arrives Right X : P320 pins 1~2

3.3V Originates from Control board IC53 center leg. Arrives on X boards P110, P310, P310 Pins 57, 58, 59, 60

VA

55V

EC

27.76V

EC Generation

22K

5.6 5.6 5.6

5.6

22K

5.6

5.6 5.6

5.6 5.6

5.6 5.6

5.6 5.6

5.6

EC
Gnd

From On-Board Data Buffer

From Control Board

3.3V
X-ER-DN POCO BLK

Gnd

Gnd
RSDS-CLK-N RSDS-CLK-P RSDS-A1N RSDS-A2N RSDS-A1N RSDS-A3N RSDS-A2N RSDS-A1N RSDS-A1P RSDS-A2P RSDS-A1P RSDS-A3P RSDS-A2P

3.3V
RSDS-A1P

EC
Gnd

VA2
STB

VA2

CE1

CE2

NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

Va

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Flexible Printed Ribbon Cable to TCP IC X Board TCP Connector Distribution Any X Board to Any TCP P101~P105
Black on EC Open Black on VA2 0.5V Black on 3.3V 0.44V Red on 3.3V 1.15V

Red on EC or VA2 Open

146

January 2010

50PZ950

Va

RGB Timing Signals

Clk

RGB Signals

Plasma

NC

TCP Visual Observation. Damaged TCP

Warning: DO NOT attempt to run the set with the Heat Sink over the TCPs removed removed. After a very short time, these ICs will begin to self destruct due to overheating.
This damaged TCP can, (at the location of the TCP). a) Cause the Power Supply to shutdown. (VA shorted, 3.3V shorted). b) Generate abnormal vertical bars, (colored noise). c) Cause the entire area driven by the TCP to be All White or ALL BLACK. d) Cause a Single Pixel Width Line defect. The line can be Red, Green or Blue. e) A dirty contact at the connector can cause b, c and d also.

TCP Taped Carrier Package

Look for burns, pin holes, damage, etc.

147

March 201 1

50PZ950

Plasma

P120, P320, P321 and P320 Connector Va from Left to Center to Right X
Voltage and Diode Mode Measurement (No Stand-By Voltages) All Connectors are 4 Pin Pin 1-2 3-4 Label VA Gnd Run *55V Gnd Diode Mode Open p Gnd

* Note: This voltage will vary in accordance with Panel Label. There are no Stand-By voltages on this connector.

P120 Left X

P320 Center X

P321 Center X

P320 Right X

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

148

March 201 1

50PZ950

Plasma

P120, P220, P221 and P320 X Board Connector (VA Diode Check)

P120 Left X

P320 Center X

P321 Center X

P320 Right X

Va Right 2 pins g p Both Connectors B th C t Gnd Left 2 pins +

On Chassis Gnd

Va Right 2 pins g p Both Connectors B th C t Gnd Left 2 pins

On Chassis Gnd On Va (0.42) all connectors connected. On Va (0.42) Y-SUS connector removed, TCPs connected. On Va (Open) all connectors removed, removed TCPs disconnected.

On Va (Open) all connectors connected. On Va (Open) Y-SUS connector removed, TCPs connected. On Va (Open) all connectors removed, removed TCPs disconnected.

149

March 201 1

50PZ950

Plasma

P121 Left X Drive Connector from Y-SUS P203 Information

Voltage and Diode Mode Measurement (No Stand-By Voltages) Heat Sink Removed 1

P121 Connector " X-Drive Left Board" from "Y-SUS P203 Pin 1-2 3 4-5 Label VA n/c Gnd Run *55V n/c Gnd Diode Mode Open n/c Gnd

* Note: This voltage will vary in accordance with Panel Label. There are no Stand-By voltages on this connector.

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

150

March 201 1

50PZ950

Plasma

P110 Connector Left X Board to Control P101

P110 "X-Left" to P101 "Control"
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Label Gnd BLK0 P0C0 CE2_0 CE1_0 X_SUS_DN0 X_ER_DN0 STB1 STB0 Gnd TCP5_RSDS_A1P TCP5_RSDS_A1N TCP5_RSDS_A2P TCP5_RSDS_A2N TCP5_RSDS_A3P TCP5_RSDS_A3N Gnd RSDS_CLK_P3 RSDS_CLK_N3 Gnd TCP4_RSDS_A1P TCP4_RSDS_A1N Run Gnd 1.89V 1.89V 0.42V 0.42V 0.42V 0.42V 3.2V 3.2V Gnd 1.25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd 1.08V 1.34V Gnd 1.25V 1.18V Diode Check Gnd Open Open Open Open Open Open Open Open Gnd Open Open Open Open Open Open Gnd Open Open Gnd Open Open Pin Label Run 1.25V 1 25V 1.18V 1.25V 1.18V Gnd 1.25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1.18V 1.25V 1 25V 1.18V Gnd Diode Check Open Open Open Open Gnd Open Open Open Open Open Open Gnd Open Open Gnd Open Open Open Open Open Open Gnd Pin 45 46 47 Label RSDS_CLK_P0 RSDS CLK P0 RSDS_CLK_N0 Gnd Run 1.08V 1 08V 1.34V Gnd 1.25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd n/c n/c 3.28V 3.28V 3.28V 3.28V Diode Check Open Open Gnd Open Open Open Open Open Open Gnd Open Open Open Open Open Open 23 TCP4 RSDS A2P TCP4_RSDS_A2P 24 TCP4_RSDS_A2N 25 TCP4_RSDS_A3P 26 TCP4_RSDS_A3N 27 Gnd

48 TCP1_RSDS_A1P 49 TCP1_RSDS_A1N 50 TCP1_RSDS_A2P 51 TCP1_RSDS_A2N 52 TCP1_RSDS_A3P 53 TCP1_RSDS_A3N 54 55 56 57 58 59 60 Gnd n/c n/c 3.3V 3.3V 3.3V 3.3V

28 TCP3_RSDS_A1P 29 TCP3_RSDS_A1N 30 TCP3_RSDS_A2P 31 TCP3_RSDS_A2N 32 TCP3_RSDS_A3P 33 TCP3_RSDS_A3N 34 35 36 37 Gnd RSDS_CLK_P1 RSDS_CLK_N1 Gnd

38 TCP2_RSDS_A1P 39 TCP2_RSDS_A1N 40 TCP2_RSDS_A2P 41 TCP2_RSDS_A2N 42 TCP2 RSDS A3P TCP2_RSDS_A3P 43 TCP2_RSDS_A3N 44 Gnd

57~60

57~60 pins 3.3V TP

White hash marks count as 5

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

151

March 201 1

50PZ950

Plasma

P310 Connector "Center X Board to Control Board P102

P310 "X-Cent" to P102 "Control" Pin 1 2 3 4 5 6 7 8 9 10 Label Gnd BLK1 P0C1 CE2_2 CE1_2 X_SUS_DN2 X SUS DN2 X_ER_DN2 STB5 STB4 Gnd Run Gnd 1.89V 1.89V 0.42V 0.42V 0.42V 0 42V 0.42V 3.2V 3.2V Gnd Diode Check Gnd Open Open Open Open Open O Open Open Open Gnd Open Open Open Open Open p Open Gnd Open Open Gnd Open Open Pin Label Run 1.25V 1.18V 1.25V 1.18V Gnd 1.25V 1 25V 1.18V 1.25V 1.18V 1.25V 1.18V 1 18V Gnd 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd Diode Check Open Open Open Open Gnd Open O Open Open Open Open Open Gnd Open Open Gnd Open p Open Open Open Open Open Gnd Pin 45 46 47 Label RSDS_CLK_P0 RSDS_CLK_N0 Gnd Run 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1 25V 1.18V 1.25V 1.18V Gnd n/c n/c 3.28V 3.28V 3.28V 3.28V 3.28V Diode Check Open Open Gnd Open Open Open O Open Open Open Gnd Open Open Open Open Open Open p Open 23 TCP9_RSDS_A2P 24 TCP9_RSDS_A2N 25 TCP9_RSDS_A3P 26 TCP9_RSDS_A3N 27 Gnd

48 TCP6_RSDS_A1P 49 TCP6_RSDS_A1N 50 TCP6 RSDS A2P TCP6_RSDS_A2P 51 TCP6_RSDS_A2N 52 TCP6_RSDS_A3P 53 TCP6_RSDS_A3N 54 55 56 57 58 59 60 60 Gnd n/c n/c 3.3V 3.3V 3.3V 3.3V 3.3V

28 TCP8 RSDS A1P TCP8_RSDS_A1P 29 TCP8_RSDS_A1N 30 TCP8_RSDS_A2P 31 TCP8_RSDS_A2N 32 TCP8_RSDS_A3P 33 TCP8 RSDS A3N TCP8_RSDS_A3N 34 35 36 37 Gnd RSDS_CLK_P1 RSDS_CLK_N1 Gnd

11 TCP10 RSDS A1P 1 25V TCP10_RSDS_A1P 1.25V 12 TCP10_RSDS_A1N 1.18V 13 TCP10_RSDS_A2P 1.25V 14 TCP10_RSDS_A2N 1.18V 15 TCP10_RSDS_A3P 1.25V 16 TCP10_RSDS_A3N 1.18V 17 18 19 20 21 22 Gnd RSDS_CLK_P3 RSDS_CLK_N3 Gnd TCP9_RSDS_A1P TCP9_RSDS_A1N Gnd 1.08V 1.34V Gnd 1.25V 1.18V

38 TCP7_RSDS_A1P 39 TCP7_RSDS_A1N 40 TCP7_RSDS_A2P 41 TCP7_RSDS_A2N 42 TCP7_RSDS_A3P 43 TCP7_RSDS_A3N 44 Gnd

57~60

57~60 pins 3.3V TP

White hash marks count as 5 t

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

152

March 201 1

50PZ950

Plasma

P310 Connector Right X Board to Control P104

P310 "X-Right" to P104 "Control"
Pin 1 2 3 4 5 6 7 8 9 10 Label Gnd BLK1 P0C1 CE2_2 CE1_2 X_SUS_DN2 X SUS DN2 X_ER_DN2 STB5 STB4 Gnd Run Gnd 1.89V 1.89V 0.42V 0.42V 0.42V 0 42V 0.42V 3.2V 3.2V Gnd Diode Check Gnd Open Open Open Open Open Open Open Open Gnd Open Open Open Open Open Open Gnd Open Open Gnd Open Open Pin Label Run 1.25V 1.18V 1.25V 1.18V Gnd 1.25V 1 25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd Diode Check Open p Open Open Open Gnd Open Open Open Open Open Open Gnd Open Open Gnd Open Open Open Open Open Open Gnd Pin 45 46 47 Label RSDS_CLK_PB RSDS_CLK_NB Gnd Run 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1 25V 1.18V 1.25V 1.18V Gnd n/c n/c 3.28V 3.28V 3.28V 3.28V Diode Check Open p Open Gnd Open Open Open Open Open Open Gnd Open Open Open Open Open Open 23 TCP14_RSDS_A2P 24 TCP14_RSDS_A2N 25 TCP14_RSDS_A3P 26 TCP14_RSDS_A3N 27 Gnd

48 TCP11_RSDS_A1P 49 TCP11_RSDS_A1N 50 TCP11 RSDS A2P TCP11_RSDS_A2P 51 TCP11_RSDS_A2N 52 TCP11_RSDS_A3P 53 TCP11_RSDS_A3N 54 55 56 57 58 59 60 Gnd n/c n/c 3.3V 3.3V 3.3V 3.3V

28 TCP13 RSDS A1P TCP13_RSDS_A1P 29 TCP13_RSDS_A1N 30 TCP13_RSDS_A2P 31 TCP13_RSDS_A2N 32 TCP13_RSDS_A3P 33 TCP13_RSDS_A3N 34 35 36 37 Gnd RSDS_CLK_P9 RSDS_CLK_N9 Gnd

11 TCP15_RSDS_A1P 1.25V 12 TCP15_RSDS_A1N 1.18V 13 TCP15_RSDS_A2P 1.25V 14 TCP15_RSDS_A2N 1.18V 15 TCP15_RSDS_A3P 1.25V 16 TCP15_RSDS_A3N 1.18V 17 18 19 20 Gnd RSDS_CLK_P11 RSDS_CLK_N11 Gnd Gnd 1.08V 1.34V Gnd

38 TCP12_RSDS_A1P 39 TCP12_RSDS_A1N 40 TCP12_RSDS_A2P 41 TCP12_RSDS_A2N 42 TCP12 RSDS A3P TCP12_RSDS_A3P 43 TCP12_RSDS_A3N 44 Gnd

57~60

21 TCP14_RSDS_A1P 1.25V 22 TCP14_RSDS_A1N 1.18V

57~60 pins 3.3V TP

White hash marks count as 5 t

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

153

March 201 1

50PZ950

Plasma

MAIN BOARD SECTION

The following section gives detailed information about the Main board. This board contains the Microprocessor, Microprocessor Audio section, video section and all AV inputs It also receives all input signals section inputs. and processes them to be delivered to the Control board via the LVDS cable. The (VSB, 8VSB and QAM) tuner is located on the main board. This board is also where the televisions software upgrades are accomplished through the USB ports or via the Internet. The Main board also has a LAN (CAT5) input to allow open Internet access or access through either USB port with a wireless network adaptor. In addition, the Main board has an output to the Wireless Media box (Dongle) for control and any of the HDMI inputs can accept the Wireless Media box Dongle HDMI output. This board has no mechanical adjustments. The Main Board Receives its operational voltage from the SMPS: DURING STAND-BY FROM THE SMPS: STBY 5V DURING RUN FROM THE SMPS (STBY 5V remains): +5V for Video processing 17V for Audio and Tuner B+ (Stepped down to 5V)

Distributes Key 1 and Key 2 to the Front IR Board for Front Key Pad detection. Receives Intelligent Sensor data from the Front IR/Key Board (via SCL/SDA). Drives front Power LEDs through the Ft. IR/Key board to the Power LED board. Distributes +3 3V ST and 3.3V_Normal to the Front IR Board and to the Ft Power LED +3.3V_ST 3 3V Normal board.

154

March 201 1

50PZ950

Plasma

Main Board Layout and Identification

3D Reset P1600 Speakers P500 to SMPS P600 N/C P102 N/C USB 2 P101 N/C USB 1

HDMI 4 P3200 LVDS Micro Reset IC600 Microprocessor P900 to Ft IR IC101 Video Processor

HDMI 3

HDMI 2

HDMI 1 TU2101 Tuner

P1302 Motion Remote

155

March 201 1

50PZ950

Plasma

50PZ950 Main (Front and Back) Layout Drawing

P1600 "Main" to "Speakers" P600 n/c 3.3V_Normal / 3V3 L511 P500 Pin SBY Run Diode Check 5V in IC505 3V3 in 1 0V *0V~1V Open IC500 IC501 L519 3D Reset SW3200 3D IC Reset IC3202 P102 7V 2 0V *0V~1V Open Gen 0.9V_Core L1603 L505 IC3204 17V in n/c IC1600 AUDIO OUT 5V in 3 0V *0V~1V Open USB2 To Speakers L1602 Right pin 6 4 0V *0V~1V Open (All Pins Right + pin 9 IC1201 L1601 0V~1V) P101 * Speaker voltage changes with volume level. AUDIO Left - pin 10 USB OCP L1600 Left + pin 13 P1600 n/c AMP P500 "Main" to P813 "SMPS" AUDIO B+ 17V P3201 n/c USB OCP USB1 Pin 8 (Left) 25Mhz Pin Label STBY Run Diode Check IC1700 11 (Right) IC1200 NAND 1_2 17V 0V 17V Open X3200 Flash IC502 IVO IC3201 Serial Flash 3-4 Gnd Gnd Gnd Gnd NVRAM IC102 5V_3D 3 L1702 5-7 5.1V 0.46V 5.17V 1.18V 2 2 in 1 3D 1V Out IC103 8 Error_Det 3.44V 4.02V 1.73V IC3202 Formatter HDMI4 2.5V_BCM35230 9-12 Gnd Gnd Gnd Gnd IC401 DDR BCM 5V in D717 13-14 STBY_5V 3.47V 5.14V 1.07V IC101 1.8V Out IC1702 IC1704 15 RL_ON 0V 3.28V 1.78V 1V8 IC700 IC402 DDR LVDS 16 AC Det 0V 4.06V 1.04V HDMI3 3V3 in Processor HDMI 17 M_ON 0V 3.28V 1.79V P3200 Selector IC504 18 Auto_Gnd Gnd Gnd Gnd SW600
1 3 2

A2

A1

1 3

P900 "MAIN" to "Front IR" Pin Label STBY 15 n/c n/c 14 n/c n/c 13 Touch_Ver_Check 0.19V 12 LED_PWR_On 0V 11 3.3V_Multi 0V 10 3.3VST 3.3V 9 Gnd Gnd 8 EYE_SDA 3.3V 7 EYE_SCL 3.3V 6 Gnd Gnd 5 LED_RED 3.25V 4 Key2 3.3V 3 Key1 3.16V 2 Gnd Gnd 1 IR 2.84V

Micro Reset

3 1

Run n/c n/c 0V 0V 5.07V 3.3V Gnd 3.3V 3.3V Gnd 0V 3.3V 3.16V Gnd 2.85V

Diode Check Open Open 1.69V 1.6V 0.50V 0.85V Gnd 1.72V 1.72V Gnd 1.72V 1.77V 1.77V Gnd 2.63V

EEPROM

10Mhz 1.5V_DDR
3 1 2

MAIN BOARD p/n: EBT61381702

D2100
A2

D716

A2

A1

HDMI2
A2 A1 C

IC601
5V_Normal in

X600

5V_Normal in
A1

3.3V_ST Q102 Q101 IC802

PC EDID
A1 A2 C

IC600
B E C

IC503 5V_ST in Microprocessor

PC Sync

2 1 2 1

3 4 3 4

P900 Q3205 Wireless 17V SW Q1001 Q1002

S E B D

IC801

IC803
RS232 Data

Grayed out components are on the back

TUNER UDA55AL
Digital Video 18. IF p

D715 D714 Q710 HDMI1

A1 C A2 2

D713

A2

A1

D810

17V_in

2 C BE

IC3203
Motion Remote

Q1004 Q1003

E B

RS232

P1302

Q801 IR

Q?

17. IF n 16. IF AGC 15. Reset 14. 3.3V 13. 1.26V Analog Video 12. GND 11. CVBS 10. NC 9. SIF

1.26V_TU 3.3V_TU in Q2105 IC2103

C B E B E C

1 2 3

R AV IN 2 L V

TU2101 Q602
C E B B C E

8. NC 7. SDA 6. SCL 5. NC 4. NC 3. 5V 2. NC 1. NC

Q2104 IC506
1 23 2

Q603

5V_TU
7V in

156

March 2011

50PZ950

Plasma

50PZ950 Main Front Layout Drawing

P500
SW3200 3D IC Reset IC3202
L1603

3.3V_Normal / 3V3 5V in IC505 IC501 L519 0.9V_Core

5V in

P600 n/c
L511 IC500 7V
17V in

To Speakers (All Pins 0V~1V)

P1600

Right pin 6 Right + pin 9 L1601 AUDIO Left - pin 10 L1600 Left + pin 13 AMP AUDIO B+ 17V P3201 n/c Pin 8 (Left) IC1700 25Mhz 11 (Right)

IC1600 AUDIO OUT L1602

P102 n/c

L505

USB2 IC1201
USB OCP

P101 n/c
NAND Flash

USB OCP

USB1

IC500
L1702

IVO
5V_3D in 1V Out

X3200

IC102 IC3202 IC1702

LVDS Processor 3D Formatter

IC1200 IC502
3 2 2 1

IC401 DDR

BCM
IC101

HDMI4 2.5V_BCM35230
5V in

D717
A2 A1 C

IC402 DDR

IC700
HDMI Selector

HDMI3

P3200
SW600 Micro Reset 10Mhz X600 3.3V_ST IC503 5V_ST in Microprocessor
1 2 3

MAIN BOARD p/n: EBT61381702

D2100
A2

A2

A1

D716 HDMI2

A1

IC600

D714 Q710

A1 A2 2

1 4

HDMI1

IC801

IC803
PC Sync RS232 Data

P900
Q1002
Wireless 17V SW 17V_in
D

Q1001
S G E B C

TUNER UDA55AL
Digital Video 18. IF p

RS232 IR

P1302

Q?

17. IF n 16. IF AGC 15. Reset 14. 3.3V 13. 1.26V Analog Video 12. GND 11. CVBS 10. NC 9. SIF

C B B E C E

Q2105

TU2101

8. NC 7. SDA 6. SCL 5. NC 4. NC 3. 5V 2. NC 1. NC

Q2104 IC506 AV IN 2 L
123 2

5V_TU
7V in

157

March 2011

50PZ950

Plasma

50PZ950 Main Board Front Side Component Voltages

IC500 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC501 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC502 Pin [1] [2] [3] IC503 Pin [1] [2] [3]

(+7V) Regulator 13.14V 17V 3.12V 1.79V 0.8V 0.67V 0V 7.11V (+0.9V_Core) Regulator 0V 5V 0V 0.8V 1.04V 3.29V 0.29V 0.99V (+2.5V_BCM35230) Regulator 5.02V 2 4V 2.54V 1.28V (+3.3V_ST) Regulator 5.02V 3.29V 5.19V

IC505 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] IC506

(+3.3V_Normal / 3V3) Regulator 5V 5V 0V 0V 0V 0V Don't read 0.5V (freezes) 1.7V 3.3V 3.3V 3.3V 8.2V 0V 3.3V 5V

IC803 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] IC1200 Pin [1] [2] [3] [4] [ ] [5] [6] [7] [8] D714

RS232 Data Buffer 3.29V 5.56V 0V 0V (-5.46V) (-5.49V) 5.59V 0V 3.29V Gnd 3.28V 3.28V 0V (-5.5V) Gnd 3.29V USB1 5V Overcurrent 0V 5V 5V 3.28V 3 12V 3.12V 5V 5V Gnd

IC1201 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC1700 Pin [1] [2] [3] [4] [5] [6] [7] [8]

USB2 5V Overcurrent 0V 5V 5V 3.28V 3.12V 5V 5V Gnd IV0 Regulator 0V 5V 0V 0.8V 0.83V 5V 1.04V 1.04V

Q710 Pin [1] [2] [3] [4] Q1001

HDMI CEC 3.25V 3.29V 3.25V 3.25V

Wireless 17V Pin Control [B] 0V [E] Gnd [C] 17V Wireless 17V Pin Switch [B] 17V [E] 0V [C] 17V Tuner Pin SIF [B] 0.2V [E] 0.9V [C] 0V T Tuner Pin CVBS [B] 3.6V [E] 4.28V [C] Gnd

Q1002

(+5V_TU) Reg Pin for Tuner [1] 7.1V [2] 5V [3] 3.78V PC Sync S Buffer 1.6V 1.6V 3.67V 1.87V 1.87V 4.43V Gnd 4.42V 1.88V 1.88V 3.67V 1.59V 1.59V 4.98V

Q2104

IC801 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]

Q210 Q2105

HDMI CEC Pin Pull Up [A1] 3.28V [A2] 0V [C] 3.23V 5V Pull-Up for DDC_SCL/SDA3 0V 5V 4.84V

D717

5V Pull-Up for PinDDC_SCL/SDA4 [A1] 0V [A2] 5V [C] 4.86V LED +3.3V_TU Pin Detection [A1] 1.84V [A2] 0.14V [C] 0V

D716 Pin [A1] [A2] [C]

D2100

158

March 2011

50PZ950

Plasma

50PZ950 Main Back Layout Drawing

IC3204
1 2 3

3V3 in 3D Reset Gen

IC3201 IC103
NVRAM Serial Flash

MAIN BOARD p/n: EBT61381702 DDR

IC504
3 2 2 1

IC1704
1 2 3 2

3V3 in

1V8

D715
A2 C A1

1.5V_DDR
RGB_DDC_SCL 5V_Normal in

IC601
EEPROM

D713
C A1 A2

Q102 Q101
TUNER UDA55AL
18. IF p Digital Video 17. IF n 16. IF AGC 15. Reset 14. 3.3V 13. 1.26V 12. GND 11. CVBS Analog Video 10. NC 9. SIF 8. NC 7. SDA 6. SCL 5. NC 4. NC 3. 5V 2. NC 1. NC

3 4 3 4

2 1 2 1

RGB_DDC_SDA

IC802
PC EDID
A2 A1 C

Q3205
E B C

EDID WP

D810 Q801
C E B
C B E

Q1004
E B C

IC2103
1 2 3 2

TU2101

RS232 IR Out

IR Q1003 Pass

IC3203
Motion Remote

1.26V_TU
3.3V_TU in

Q602
IR Buffer
C B B E C E

Q603

IR Buffer

159

March 2011

50PZ950

Plasma

50PZ950 Main Board Back Side Component Voltages

IC103 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC504 NRAM n/c Gnd 3.2V Gnd 3.02V 3.02V Gnd 3.2V IC1704 IC802 Pin [1] [2] [3] [4] [5] [6] [7] [8] PC EDID EPPROM Gnd Gnd Gnd Gnd 4.68V 4.68V 4.68V 4.68V IC3204 3D_ASIC RESET_SWITCH Pin [1] 3.18V [2] Gnd [3] 3.18V Motion Remote 3.23V 3.23V 0.22V 0.22V 0.22V Gnd Gnd Gnd 3.20V 3.20V 3.29V 3.18V 3.18V 3.20V RGB_DDC SDA Gnd 4.68V 3.20V 3.20V RGB_DDC SCL Gnd 4.68V 3.20V 3.20V Q602 Wired IR Pin To Micro [B] 0.02V [C] 3.31V [E] Gnd Wired IR Pin To Micro [B] 0.60V [C] 0.02V [E] Gnd PC Data Pin Buffer [B] 0.59V [C] 0.02V [E] Gnd Wireless Pin IR Pass [B] 0.50V [C] 0.02V [E] Gnd Wireless Pin IR Pass [B] 0.02V [C] 3.3V [E] Gnd EDID Write Protect Buffer 0V 4.68V Gnd

IC3203 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] Q101 Pin [1] [2] [3] [4] Q102 Pin [1] [2] [3] [4]

Q603

(+1.5V_DDR) Pin Regulator [1] 0.30V [2] 1.56V [3] 4.96V EEPROM for Micom Gnd Gnd 3.3V Gnd 3.3V 3.3V Gnd 3.3V

IV8 Pin Regulator [1] Gnd [2] 1.8V [3] 3.17V (+1.26V_TU) Pin Regulator [1] 0.04V [2] 1.28V [3] 3.17V Serial Flash 3.18V 3.18V 3.18V Gnd 0V 0V 3.18V 3.18V

Q801

IC601 Pin [1] [2] [3] [4] [5] [6] [7] [8]

IC2103

Q1003

IC3201 Pin [1] [2] [3] [4] [5] [6] [7] [8]

Q1004

Q3205 Pin [B] [C] [E]

160

March 2011

50PZ950

Plasma

Main Board Tuner Check (Shield Off) Pins Exposed UDA55AL Pins Identified
The pins can be accessed from the front with the cover removed. Data Pin 7 Clock Pin 6 Only present during Channel Change Page numbers are from Schematic Digital Video to the BCM chip IC101. (Page 3) 3.3V_DE from 3.3V_TU made from 3.3V_Normal IC505. (Page 6) 1.26V_TU from IC2103 (Source for IC2103 i 3 3V TU (Page 18) is 3.3V_TU. (P Clock and Data from the BCM chip IC101. (Page 2) 5V_TU from IC506. Generated when 12V arrives. (Page 6)

DIF2 Pin 18 Dif (P) DIF1 Pin 17 Dif (N) Pin 14 B+ (3.3V_DE) Pin 13 B+ (1.26V_TU) Analog Video Pins 11 TU_SIF Pin 9 Audio Data Pin 7 (SDL0_3.3V) Clock Pin 6 (SCL0_3.3V) Pin 3 Tuner B+ (5V_TU) Pin 1 Analog Video to Q2105 CVBS buffer

SIF to Q2104 TU_SIF buffer TU2103 (UDS55AL) Bottom right hand side of Main Board Tuner shown on Page 6 of Schematic

161

March 201 1

50PZ950

Plasma

Main Board Tuner Check (Shield Off) Pins Exposed TDVW-H103F

You must take off the Tuner Cover for Test Points. To keep the Data and Clock lines running so they can be measured easily, place the unit into Auto Tuning. Data Pin 7 Clock Pin 6 Only present during Channel Change

Main B M i Board d

162

March 201 1

50PZ950

Plasma

Main Board Tuner Video and SIF Output Check

You must take off the Tuner Cover for Test Points. USING COLOR BAR SIGNAL INPUT MAIN Board
Tuner Location Pin 11 Analog Video Signal

Note: NTSC Only Video Out Signal only when receiving an analog Channel.

1.6Vp/p

Pin 9 SIF SIF Signal

200mV / 5MSec 511mVp/p

Pin 19 768mVp/p Pin 18 800mVp/p

Note: Pin 17 and Pin 18 Dig IF Signal 8VSB or QAM Only when receiving a Digital Channel.

200mV / 1uSec

100mV / 5MSec

163

March 201 1

50PZ950

Plasma

Main Board Crystal X600, X601 and X3200 Check

Reading this Crystal may cause video lock up X3200 25Mhz
Left Side 3.45V p/p Right Side 3.47V p/p

1.45V X3200

1.53V

X900 Runs only during On On (Overtone Crystal) X600 10Mhz X600 Runs all the time (Micro Crystal)
X600 1.47V 1.43V X601 1.9V 1.77V Left Side 2.46V p/p Right Side 3.47V p/p

X3200 X600 X601

MAIN Board
Crystal Location C t lL ti

X601 32 768KHZ Does not run normally 32.768KHZ (Micro Halt Crystal)

164

March 201 1

50PZ950

Plasma

Main Board P3200 (Removing the LVDS Cable)

(1) Using your fingernail, lift up the locking mechanism. Since the locking tab is very thin and fragile, its best to lift slightly one end, then work across the locking tab g a little at a time, back and forth until the tab is released. (2) Pull the Cable from the Connector

165

March 201 1

50PZ950

Plasma

Main Board Plug P500 to Power Supply Voltages and Diode Check
Diode Mode Check with the Board Disconnected. DVM in the Diode mode.

P500 "Main" to P813 "SMPS" Main SMPS Pin 1_2 34 3-4 5-7 8 9-12 13-14 15 16 17 18
a Note: e a ac

Pin STBY 0V Gnd 0.46V 3.44V Gnd 3.47V 0V 0V 0V Gnd Run 17V Gnd 5.17V 4.02V Gnd 5.14V 3.28V 4.06V 3.28V Gnd Diode Check Open Gnd 1.18V 1.73V Gnd 1.07V 1.78V 1.04V 1.79V Gnd
P500

front

Label
a

17V

Gnd
a

5.1V

Error_Det Gnd

STBY_5V RL_ON AC Det M_ON

ad b

Front pins are odd Back pins are even

Auto_Gnd

The RL On command turns on the 17V +5V Error Det and AC DET RL_On 17V, +5V, Error_Det AC_DET. b Note: The M-On command turns on M5V, Va and Vs. c Note: The Error Det line is not used in this model. d Note: AC Det line is not used. e Note: Pin 18 is grounded on the Main. If opened, the power supply turns on automatically.

166

March 201 1

50PZ950

Plasma

Main Board Plug P900 to Ft IR / Soft Touch Key Board

Voltage and Diode Mode Measurements for the Main Board
P900 "MAIN" t "F to "Front IR / Soft T t S ft Touch Key Board" hK B d" Pin 15 Soft Touch Key board sensitivity For Intelligent Sensor Stand-By 3.3V 7&8 Intelligent Sensor 14 13 12 11 10 9 8 7 6 5 3&4 Function F nction Buttons Infrared Remote 4 3 2 1 Label n/c n/c Touch_Ver_Check LED_PWR_On *3.3V_Multi 3.3VST Gnd EYE_SDA EYE_SCL EYE SCL Gnd LED_RED Key2 Key1 Gnd IR STBY n/c n/c 0.19V 0V 0V 3.3V Gnd 3.3V 3.3V 3 3V Gnd 3.25V 3.3V 3.16V Gnd 2.84V Run n/c n/c 0V 0V 5.07V 3.3V Gnd 3.3V 3.3V 3 3V Gnd 0V 3.3V 3.16V Gnd 2.85V Diode Check Open Open p 1.69V 1.6V 0.50V 0.85V Gnd 1.72V 1.72V 1 72V Gnd 1.72V 1.77V 1.77V Gnd 2.63V Routed to Power LED board

* 3.3V_Multi is actually +3.3V_Normal

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

167

March 201 1

50PZ950

Plasma

Main Board P1302 and P1600 Connector Voltage and Diode Check
P1302 "MAIN Board" To "Motion Remote Sensor" Pin 12 11 10 9 8 7 6 5 4 3 2 1 Label *3D Sync 3D_GPIO_2 *3D_GPIO_1 3D_GPIO_0 Gnd DD_Mremote DC_Mremote DC M t
M_RFModule_Reset

P1600 "Main" to "Speakers" Pin 1 2 3 4 Label FR+ FRFL+ FLSBY 0V 0V 0V 0V Run *0V~1V *0V~1V *0V~1V *0V~1V Diode Check Open Open Open Open

STBY 0V 0V 0V 0V Gnd 0V 0V 0V 0V 0V Gnd 0V

Run 0V/1.59V 0V 0V/3.18V 0V Gnd 3.3V 3.3V 3 3V 3.3V 3.3V 3.29V Gnd 3.33V

Diode Check Open 1.26V 1.26V 1.26V Gnd 1.34V 1.32V 1 32V 2.37V 1.17V 1.18V Gnd 0.49V Pin 12 w/3D /3D

*S Speaker voltage changes with volume l k lt h ith l level. l P1600 P1302

M_REMOTE_TX M_REMOTE_RX _ _ Gnd 3.3V_Normal

*Pin 10 and 12 voltages without 3D / with 3D Pin

RF Freq 3D Disable 60Hz 59.94Hz GPIO 0 0 1 0 GPIO 1 0 0 1 GPIO 2 0 0 0

4.15V p/p 60 Hz

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

168

March 201 1

50PZ950

Plasma

Main Board IC1600 Audio Circuit Explanation

AUDIO OUT Right pin 6 Right + pin 9 Left - pin 10 Left + pin 13 AUDIO B+ 17V Pin 8 (Left) 11 (Right) 3.3V_AMP 3 3V AMP Arriving Pin 21 35 21, From 3.3V_Normal through L1605 3.3V_Normal generated by IC505

All speaker pins 0~1V Varies with audio level Right (-) P1600 Right (+) g ( ) Speaker S k Connector Left (-) Left (+) See previous page For P1600 Diode Check

1 IC1600 Audio Amp

Main Board Location

Audio Master Clk pin 27 Audio_SCK pin 28 Audio_LRCK pin 29 Audio_LRCH pin 30 AMP_Reset_N pin 31

SDA_3.3V SDA 3 3V pin 33 SCL_3.3V pin 34

169

March 201 1

50PZ950

Plasma

Main Board P3200 LVDS Video Signal Checks

Pin Pin Ctl Board Main Board 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 50 31 49 32 48 33 47 34 46 35 45 36 44 37 43 38 42 39 41 40 Pin Pin Ctl Board Main Board 40 41 39 42 38 43 37 44 36 45 35 46 34 47 33 48 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 24 57 23 58 22 59 21 60 20 61 19 62 18 63 17 64 16 65 15 66 14 67 13 68 12 69 11 70 10 71 9 72 8 73 7 74 6 75 5 76 4 77 3 78 2 79 1 80

Example Waveforms Taken from P3200 pins 12 and 13, but there are actually 48 pins carrying video, but they are all similar. Input Si ll i il I t Signal SMPT C l B l Color Bar

Pin 69 RA1-

613mV 10MSec p/p per/div Pin 68 RA1+

Main Board P3200 Location

TIP: Use the Control Board side for measurements. Test Points are available. Use the Pin cross reference chart on the left because the pins are inverted on the Control Board.

170

March 201 1

50PZ950

Plasma

Main Board Plug P3200 LVDS Voltages

Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Label Gnd VS_3D UART_TDX_12P UART_RDX_12P n/c n/c Gnd RE4+ RE4RD4+ RD4Gnd RCLK4+ RCLK4Gnd RC4+ RC4RB4+ RB4RA4+ RA4Gnd Gnd RE3+ RE3RD3+ Run Gnd 0V (1.64V 3D) 3.29V 3.29V n/c n/c Gnd 1.11V 1.23V 1.13V 1.28V Gnd 1.19V 1.17V Gnd 1.10V 1 10V 1.21V 1.14V 1.20V 1.13V 1.19V 9 Gnd Gnd 1.12V 1.21V 1.12V Diode Open Open 1.17V 1.17V Open Open Gnd 1.17V 1.17V 1.17V 1.17V Gnd 1.17V 1.17V Gnd 1.17V 1 17V 1.17V 1.17V 1.17V 1.17V 1.17V Gnd Gnd 1.17V 1.17V 1.17V Pin 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Label RD3Gnd Run 1.22V Gnd Diode 1.17V Gnd 1.17V 1.17V Gnd 1.17V 1.17V 1.17V 1.17V 1.17V 1.17V Gnd Gnd 1.17V 1.17V 1.17V 1 17V 1.17V Gnd 1.17V 1.17V G d Gnd 1.17V 1.17V 1.17V 1.17V 1.17V 1.17V Pin 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Label Gnd Gnd RE1+ RE1RD1+ RD1Gnd RCLK1+ RCLK1Gnd RC1+ RC1RB1+ RB1RA1+ RA1RA1 Gnd n/c n/c n/c n/c /c SDA DISP_EN SCL

Voltage and Diode Test for the Main Board

P3200 "Main LVDS" to P31 "Control" Note: For Voltage Measurements, use the Control Board.
Run Gnd Gnd 1.12V 1.22V 1.12V 1.21V Gnd 1.18V 1.15V Gnd 1.17V 1.17V 1.13V 1.21V 1.11V 1.22V 1 22V Gnd n/c n/c n/c n/c /c 3.23V 3.29V 3.23V Diode Gnd Gnd 1.17V 1.17V 1.17V 1.17V Gnd 1.17V 1.17V Gnd 1.17V 1.17V 1.17V 1.17V 1.17V 1.17V 1 17V Gnd n/c n/c n/c n/c /c 1.17V 1.18V 1.18V 1.56V Open Gnd

RCLK3+ 1.18V RCLK3- 1.15V Gnd RC3+ RC3RB3+ RB3RA3+ RA3Gnd Gnd RE2+ RE2RD2+ RD2Gnd Gnd 1.17V 1.15V 1.12V 1.22V 1.13V 1.13V Gnd Gnd 1.12V 1.21V 1.12V 1 12V 1.21V Gnd

Bold Indicates video signal Note: No Stand-By voltages. o Sta d y o tages Note: Use the Control Board for Voltage Measurements. See Pin cross reference table on preceding page page.

RCLK2+ 1.18V RCLK2- 1.16V G d Gnd RC2+ RC2RB2+ RB2RA2+ RA2G d Gnd 1.09V 1.24V 1.12V 1.22V 1.12V 1.21V

PC_SER_DATA 3.28V PC_SER_CLK Gnd 3.29V Gnd

Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

171

March 201 1

50PZ950

Plasma

Main JK1001 Wireless Media Box Dongle Jack (Voltage and Diode Check)
JK1001 Jack "MAIN Board" To "Wireless Dongle"
Pin 1-6 7 8 9 10 11 12 13 14 15 16 17 18 19-20 19 20 Label *17V Detect Interrupt Gnd n/c Gnd I2C_SCL I2C SCL I2C_SDA Gnd Wireless_RX Wireless_TX Gnd IR_PASS Gnd STBY 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0.67V 0V Run 17V 0.3V 3.3V Gnd 3.3V Gnd 3.3V 3 3V 3.3V Gnd 3.3V 3.3V Gnd 3.3V Gnd Diode Check Open 2.8V Open Gnd Open Gnd 1.04V 1 04V 1.04V Gnd 1.8V 1.8V Gnd Open Gnd 1

JK1001 Jack

Diode Mode values taken with all Connectors Removed R d

Voltages with Wireless Media Box Dongle plugged in. (Use Dongle side to read voltages. Remove cover). *17V Switched from Q1002 Drain Back side of the board. Q1002 turned on by Q1001 front side of the board when Wireless EN arrives Wireless_EN arrives. Q1001 turned on by Microprocessor pin 38.

172

March 201 1

50PZ950

Plasma

FRONT IR / SOFT TOUCH KEY BOARD SECTION

The following section gives detailed information about the Front IR and Soft Touch Key board (IR/STKB). Note: The IR/STKB is attached to the Televisions Front Glass. It requires a great deal of disassembly to reach. After removing the bottom metal shield plate, the panel screws must be removed to lift up the panel in order to see the board. (Removing the panel allows better access). The IR/STKB board contains the Infrared Remote Receiver, Intelligent Sensor and Soft Touch Key Board decoder This board has no adjustments. decoder. adjustments The IR/STKB receives its operational B+ from the Main Board: 3.3V_ST from the Main Board. This voltage is generated on the Main Board (IC503) and output on P900 pin 10. It arrives on the IR/STKB at P100 pin 10. 3.3V_MULTI generated on the SMPS (+5V) and sent to the Main Board P500 pins 5~7. Then sent through a coil L514 to become 5V_Normal and output on P900 pin 11. It arrives on the IR/STKB at P100 pin 11.

The IR signal is routed back to the Main Board via pin 1. The Intelligent sensor is driven by 2 separate pins from the Main board SCL/SDA P100 pins 7 and 8. This sensor monitors the average room light and configures this information in data form back to the Microprocessor to manipulate brightness and color settings to correspond to room lighting conditions. Pin 13 is Touch Version Check pin to adjust the sensitivity of the Soft Touch Keys. The IR/STKB is connected to the Front Power LED board to drive the Power LEDs The control LEDs. for the Power LEDs is routed in P100 pins 5 and 12. Then output on P101 pin 3 and 6.

173

March 201 1

50PZ950

Plasma

IR / Soft Touch Key board and Intelligent Sensor Location

Assembled

You can see P100 without disassembly

P100 To Main

Lower Left Side As viewed from rear.

Disassembled

P101 To LED Power board

P100 To Main

Soft Touch Key Pad (Behind) Thin strip adhered to the protective front glass. glass

Note: The IR/STKB is attached to the Televisions Front Glass. It requires a great deal of disassembly to reach. After removing the bottom metal shield plate, the panel screws must p p be removed to lift up the panel in order to see the board. This picture is taken after panel disassembly.

174

March 201 1

50PZ950

Plasma

IR / Soft Touch Key board and Intelligent Sensor Voltages

p p/n: EBR72650201
TIP: This board is attached to the panels front glass. To Power LED V O G

P101

To Main

P100

1 IC102 IR Receiver IC102 IR Receiver Label V: B+ O: Output G: Ground Readings 0V 3.24V 2.85V IC100 Soft Touch Key Decoder

175

March 201 1

50PZ950

Plasma

P100 / P101 (IR / STKB and Intelligent Sensor )Voltages and Pin Identification
P100 "Front IR and Soft Touch Keys" to "Main" board Pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Label n/c n/c Touch Version Check LED_White LED White *3.3V_Multi 3.3V_ST Gnd EYE_SDA EYE SDA EYE_SCL Gnd LED_RED Key_2 K 2 Key_1 Gnd IR STBY n/c n/c 0.19V 0V 0V 3.3V Gnd 3.3V 3 3V 3.3V Gnd 3.25V 3.3V 3 3V 3.16V Gnd 2.84V Run n/c n/c 0V 0V 5.07V 3.3V Gnd 3.3V 3 3V 3.3V Gnd 0V 3.3V 3 3V 3.16V Gnd 2.85V Diode Check Open Open 0.62V Open Open 2.3V Open Open Open Gnd Open Open O Open Gnd Open P101 IR/STKB" to Power LED" board Pin 1 2 3 4 5 6 Label *3.3V_Multi Gnd LED_White Gnd 3.3V_ST LED_RED LED RED STBY 0V Gnd 0V Gnd 3.3V 3.25V 3 25V Run 5.07V Gnd 0V Gnd 3.3V 0V Diode Check Open Open Open Gnd 2.3V Open

* 3.3V_Multi is actually +3.3V_Normal 1

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

176

March 201 1

50PZ950

Plasma

Soft Touch Key Pad Voltage Checks h k

IC100 on the Front IR, Soft Touch K S ft T h Keys, Intelligent Sensor Board is generating these Resistance changes when a Soft Touch Key is touched. touched This in turn pulls down the Key 1 and Key 2 lines to be interpreted by the Microprocessor.

P900 Voltage Measurements with Soft Touch Key pressed.

Key 1 Line KEY 1 Power CH (Up) CH (Dn) Input Pin 3 measured from Gnd 2.3V 0.21V 1.59V 0.86V KEY 2 Enter Volume (-) Menu Volume (+) Key 2 Line Pin 4 measured from Gnd 2.4V 0.21V 1.65V 0.88V

P900 Main (No Key Pressed) Pin 3 4 Label KEY 1 KEY 2 STBY 3.16V 3.3V Run 3.16V 3.3V

177

March 201 1

50PZ950

Plasma

POWER LED SECTION

p/n: EBR72769401

The following section gives detailed information about the Front Power LED board. The Power LED is located on this board along with the Power LEDs. These boards have no adjustments. The Power LED board receives its operational B+ from the Main Board routed B through the Front IR / Soft Touch Key board: 3.3V_ST from the Main Board. This voltage is generated on the Main Board (IC400) ( ) 3.3V_MULTI generated on the Main Board (IC402).

The Front Power LEDs are driven by 2 separate pins from the Main board LED_White pin 3 and LED_Red pin 6. te p a d ed p 6

J1

178

March 201 1

50PZ950

Plasma

Power LED Board Front and Back Side Pictures

p/n: EBR72769401

J1

U1 LED Driver

Power LEDs

179

March 201 1

50PZ950

Plasma

J1 Front Power LED Board (Voltages and Pin Identification)

Voltage and Diode Mode Measurements for the Power LED Board J1 "Ft Power LED" to P101 "Front IR and Soft Touch Keys" board Pin 1 2 3 4 5 6 Label 3.3V_Multi 3 3V Multi Gnd LED_White Gnd 3.3V_ST LED_RED STBY 0V Gnd 0V Gnd 3.3V 3.25V Run 5.07V 5 07V Gnd 0V Gnd 3.3V 0V Diode Check Open Open Open Gnd 2.3V Open 3.3V_Multi is actually +3.3V_Normal

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

180

March 201 1

50PZ950

Plasma

MOTION REMOTE and 3D SYNC BOARD SECTION

The first time the Motion Remote has its batteries installed and pointed at the Television, the Motion Remote is synchronized with the TV. After that, when pointing the remote at the TV and pressing the Enter key, a pointer appears on screen, then by moving the Motion Remote around, the pointer moves with the movement of the remote. When the pointer is placed over a selectable button, you can press the center Enter button and active the Enter object. This makes navigation much easier. You can also adjust the volume, change channels and mute the audio with the Motion Remote and it has a convenient Home button for the TV Menu. Home A wrist band can be attached to the remote to avoid dropping and damaging the remote. The Motion Remote utilizes a specialized receiver on the Television to receive the RF signal and this information is then routed to P1302 and on to the IC101 the BCM IC for pointer positioning and interpretation of the other functions.
How to Re-register the Magic Motion Remote Control after Registration Failure. Reset the remote control by pressing and holding both the ENTER and MUTE buttons for 5 seconds. An LED will blink 3 times indicating the remote is ready for registering. Motion Remote Magic Remote AKB732955

181

March 201 1

50PZ950

Plasma

Motion Remote Receiver Board

The following section gives detailed information about the Motion Remote Receiver Board The Motion Remote Receiver receives signals from the Board. Motion Remote to manipulate the On-Screen pointer. The Motion Remote receives its operational B+ from the Main Board: 3.3V_Normal P1302 pin 1 from the Main Board to J1 Pin 1. This voltage is generated on the Main Board (IC505) 3 3V MULTI generated on the Main Board (IC402) 3.3V_MULTI (IC402).
No Connector Number Not Identified on board p/n: EBR72499601

182

March 201 1

50PZ950

Plasma

Motion Remote Receiver Board Close Up

No Connector No. Rear View

p/n: EBR72499601

Front View

RF Transmitter Receiver

183

March 201 1

50PZ950

Plasma

Motion Remote Connector Voltage and Diode Check

"Motion Remote Sensor to P1302 "MAIN Board" Pin 1 2 3 4 5 6 7 8 9 10 11 12
Freq 3D Disable 60Hz 59.94Hz

Label 3.3V_Normal Gnd M_REMOTE_RX M_REMOTE_TX M_RFModule_Reset DC_Mremote DD_Mremote DD Mremote Gnd 3D_GPIO_0 3D_GPIO_1 3D_GPIO_2 3D Sync
GPIO 0 0 1 0 GPIO 1 0 0 1

STBY 0V Gnd 0V 0V 0V 0V 0V Gnd 0V 0V 0V 0V

GPIO 2 0 0 0

Run 3.33V Gnd 3.29V 3.3V 3.3V 3.3V 3.3V 3 3V Gnd 0V 0V/3.18V 0V 0V/1.59V

Diode Check 0.49V Gnd 1.18V 1.17V 2.37V 1.32V 1.34V 1 34V Gnd 1.26V 1.26V 1.26V Open
Pin 12 w/3D

P1302

3.32V p/p 60 Hz

*Pin 10/12 voltages without 3D / with 3D

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

184

March 201 1

50PZ950

Plasma

INVISIBLE SPEAKER SYSTEM SECTION Invisible Speaker System Overview (Full Range Speakers)

p/n: EAB62028901

The 50PZ950 contains the Invisible Speaker system. system The Full Range Speakers point downward, so there are no front viewable speaker grills or air ports. Installed Bottom View Anti Rattle Pad Anti Rattle Pad

Remove two screws from the bottom

Reading across speaker wires, 8.2 ohm.

Front View

Rear View

Speaker p Connection

185

March 201 1

50PZ950

Plasma

INTERCONNECT DIAGRAM (11 X 17 Foldout) SECTION

This section shows the Interconnect Diagram called the 11X17 foldout thats available in the Paper and Adobe version of the Training Manual. p g Use the Adobe version to zoom in for easier reading. When Printing the Interconnect diagram from the Adobe version version, use11X17 size paper for best results. Look carefully around the diagram for special notes and troubleshooting tips.

186

March 201 1

50PZ950

Plasma

50PZ950 (50R3 Panel) CIRCUIT INTERCONNECT DIAGRAM

P813 "SMPS" to P500 "Main"

VR402 Set-up
P101 FPC

345V p/p 5V

107VRMS

Pin

Label e Auto_Gnd b M_ON ad AC Det a RL_ON STBY_5V Gnd ac

STBY Gnd 0V 0V 0V

Run Gnd 3.28V 4.06V 3.28V

No Load Diode 4.86V 0V 4.94V 0V 4.94V Gnd 4.94V 5.22V Gnd 17V Open Open 3.1V Open 2.53V Gnd 2.84V 2.13V Gnd 3.06V Note a: The RL_On command turns on the 17V, +5V, Error_Det and AC_DET. Note b: The M-On command turns on M5V, Va and Vs. Note c: The Error Det line is not used in this model. Note d: AC Det line (if missing) will Mute the Audio. Note e: Pin 18 is grounded on the Main. If opened, the power supply turn on automatically.

P203

P811 "Power Supply" to P210 "Y-SUS" Pin Label Run Vs n/c Gnd Va M5V *201V n/c Gnd *55V 5.0V Diode Open n/c Gnd Open 1.38V 1~2

18 17 16 15 13-14 9-12 8 5-7 3-4 1_2

1-2) ER 3) n/c 4-5) VS 6) n/c 7-8) Gnd

Connect Scope between Waveform TP J54 on Z board and Gnd. Use RMS information just to check for board activity.

Z-SUS Signal
100uSec Q109 57VRms Q106 261V p/p

A
0V
100V 2MSec 560V p/p

3 4~5 6

3.47V 5.14V Gnd Gnd

VR101 VZB Adj

FS201 (VS) 6.3A / 250V

VR401 Set-Dn
Y-Drive Upper P102 FPC

Error_Det 3.44V 4.02V a 0.46V 5.17V 5.1V Gnd a 17V Gnd 0V Gnd 17V

Q104
VZB TP R156

WARNING: Remove Y-Drives completely if P213 is removed.

IC191 1 5VFG 2 FGnd 3 10.9VFG

180uSec 5uSec

100V

100uS

560V p/p

Q113 Q114 D110 Z-SUS EBR71727901 P204 D114 Q107 Q110

J54 Z-Drive Waveform TP
D118

*Voltage varies with panel label

Connect Scope between Waveform TP on Y-Drive and Gnd

FS201 Va or FS203 Vs Diode Check reads Open with Board Disconnected or Connected FS202 M5V Diode Check reads 0.73V Board Connected or 1.38V Disconnected FS501 18V Diode Check reads 1.28V Board Connected or 1.31V Disconnected

Y-DRIVE UPPER BOARD p/n: EBR69839101

VS VS n/c Gnd Gnd Va M5V

VA TP

VS TP

F801 4A/250V

FPC

IC191 Waveform

1 3

VR501 VSC
10.9VFG

VS Adj VR901

P203 "Z-SUS" to "Y-SUS" P218 Pin Label Run 1~2 ER_PASS 98V~102V 3 n/c n/c 4~5 +Vs *201V 6 n/c n/c 7~18 Gnd Gnd *Voltage varies with panel label
Pin Label (+15V) (+15V) n/c M5V M5V Gnd Gnd SUS_DN CTRL_EN SUS_UP VZB2 ER_DN VZB1 ER_UP ZBIAS Run 18.34V 18.34V n/c 4.89V 4.89V Gnd Gnd 0.73V 0.06V 0.15V 2.49V 0.1V 2.53V 0.87V 1.9V

57VRMS

50V

2MSec

288V p/p

Diode Open n/c Open n/c Gnd

Gnd Gnd

P811

Q102 D111 D108 Q103

P201

P218
D503 T500

P111 FG10.9V FGnd

J33

+Vy R527

D502 D505

FS203 (VS) 6.3A / 250V

D500 IC50 0

F302/F801 160.1V STBY 390V Run

P2 "Control" to "Z-SUS Board" P201 Diode Open Open 1.52V 1.52V 1.52V Gnd Gnd Open Open Open Open Open Open Open Open 15 14 13 12 11 10 9 8 7 6 5 4 3
ER_UP ER_DN SUS_DN

J21 18V

P101

T502

P103 P104

VA Adj VR502

P214

IC501

P210

VR500 +Vy
VSC R548
23.77VFG

D501 D511

10.9VFG

D512

FS202 (M5V) 10A / 125V

D515

P112 Y-Scan FGnd

18.34V
IC302

P215

P121

VR401 Set-Dn
VScan FGnd

FS501 (18V) 2A / 125V

FS201 (VA) 4A / 125V

P221 P211 P201 FPC FGnd Y-Scan

C540

VR402 Set-Up

SMPS Test Unplug P813 to Main board. Use two (100W) light bulbs in series between Vs and Gnd to place a load on the SMPS. Apply AC, all voltage should run. See Auto Gen on the Control board to perform a Panel Test. If all supplies do not run when A/C is applied, disconnect P811 to isolate the excessive load.

Hot Ground F302 2.5A/ 250V

POWER SUPPLY p/n: EAY62171101

J16 M5V

P205

P102
P202

P201

FS202 (M5V) 4A / 125V

P201 Pins inverted from P2 on Control

P104

FPC

RL103

F101 10A/250V

2 1

P813
AC In P701 n/c

To run Z-SUS stand-alone, jump 5V to Fuse FS202. Jump Audio B+ from SMPS to J21 on the Z-SUS. Disconnect Y-SUS from Control board and from the Z-SUS. Jump VS from SMPS to Z-SUS P203. J54 290V p/p (More square shape).
Grayed out components are on the back

P206

P103

P500

L519 IC505

L511 IC3204
1 2

P217
Left Leg C540 TP With no Y-Drive 116V AC RMS 424V p/p With Y-Drives 454V p/p 107V AC RMS

With the unit on, if D1 is not on, check 5V supply. If present replace the Control Board. If missing, see (To Test Power Supply) 18V To Z-SUS (Out P2 pins 14-15) (In P105 pins 14-15)
J81 Gnd J113

P1600
M5V Gnd Gnd

SW3200
L1603 L1602 L1601

IC501

P102 n/c

IC500 USB2 IC1201 USB1

P203

CTRL_OE

CTRL_OE should be 0V (5V indicates a Problem)

Diode Check All Connectors Connected 1.28V

P22 n/c
IC101 IC102
3) 4.93V 2) 3.29V 1) Gnd 1.04V
C52

4.89V

P212 FGnd Y-Scan P202 FPC Waveform P213 Scan Data M5V Y-Drive Lower P203

P216

Y-SUS EBR69839001
P203
P213

P102

Ribbon Cable Y-SUS and Y Drive Signals

Pins 6-8 (18V) Pins 3-5 (5V) Pins 23-25 (18V) Pins 26-28 (5V)

P105
To Y-SUS Board

C61

IC51 FL5 IC61

M5V

P2

4.89V

M5V FL1, FL2, FL5

To Speakers All speaker wires 0V~1V Soft to Loud

IC1600

L505

P3201 n/c

L1600

IC502

Z-SUB BOARD p/n: EBR71728001

25Mhz IC1700
L1702

IC25

X3200 IC103 IC102

P101 n/c
IC3201

IC1200 HDMI4

M5V

1.85V

L1
D1 Blinks Indicating Board is Functioning
1.04V 1.04V

C76

3.26V

IC3202 IC401

FL1/2
1-4 (3.3V) IC53

L2
C65

1.84V

VS-DA TP

1.84V 3.3V

D1 IC11
1.63V 25 Mhz 1.69V

P101
P203 "Y-SUS" to "X-Drive Left" P121
P214 "Y-SUS" to "Upper Y-Drive" P111 P215 "Y-SUS" to "Upper Y-Drive" P112 Pin 1-2 3-12 Label FG10.9V FGnd Run 4.89V FGnd Pin 1-7 8 9-12 Label FGnd n/c Vscan Run FGnd n/c 107V

Chassis Gnd

P213 "Y-SUS" to "Lower "Y-Drive" P213 Pin 1 2 3 4 5 6 7 8 Label M5V M5V OC2_B Gnd DATA_B Gnd OC1_B OC2_T Gnd DATA_T Gnd OC1_T Gnd CLK STB Run 4.96V 4.96V 2.77V Gnd 0V Gnd 1.73V 2.73V Gnd 0V Gnd 1.74V Gnd 0.68V 4.27V
Diode Check

To Left X Board

IC1

CONTROL BOARD p/n: EBR71727801

AUTO Gen

Ribbon Cable LVDS

See 2nd page for Waveforms PANEL TEST: Remove LVDS Cable. Short across Auto Gen TPs to generate a test pattern. P703 (Main) to P100 (Ft IR)
Pin Label 1 IR 2 Gnd Key 1 3 4 Key 2 5 LED-R 6 Gnd SCL 7 8 SDA 9 Gnd 10 3.3V_ST 11 3.3V_Multi 12 LED W STBY Run 2.82V Gnd 3.14V 3.28V 3.15V Gnd 0.77V 0.77V Gnd 3.29V 0.41V 0V 2.82V To Ft IR Gnd A 3.13V 3.28V 0V Gnd 3.28V 3.28V To Motion Gnd Remote 3.28V B 5.18V 3D Sync 0V
C A1 A2

BCM
IC101 IC1701 IC504
3

IC1702

D717 IC1704
A2 A1 C

P3200
SW600 10Mhz X600
1 3 2

IC402

IC700
B E C B E

1 2 3 2

Pin 1-2 3 *4-5

Run Gnd nc VA Voltage

Diode Check Gnd nc Open

1-4 (3.3V) IC53

Gnd 3.26V Gnd X1 0.02V 0.65V

Q1

P31 LVDS

HDMI3 Q3300 Q3301

C
A2 A1

1.38V 1.38V Open Gnd 1.85V Gnd 1.85V Open Gnd 1.85V Gnd 1.85V Gnd 1.85V 1.85V

P102
To Center X Board
3) 4.89V 2) 3.3V 1) Gnd

C72

4.89V

IC53

Black Lead on Floating Gnd P217 "Y-SUS" to "Lower Y-Drive" P211 Pin 1-4 5 6-12 Label Vscan n/c FGnd Run 107V n/c FGnd

1-4 (3.3V) IC53

P104
To Right X Board

P602 n/c
Q602
C E
C

2 1
C B

C B E

Q501

Q500

A2 A1

D716 HDMI2 IC601

A1 A2 2 C

FPC

Black Lead on Floating Gnd P216 "Y-SUS" to "Lower Y-Drive" P212 Pin 1-10 11-12 Label FGnd Vscan Run FGnd 107V

*Voltage varies with panel label

D715

IC503 IC600 IC801 Q1001

C E B E B C

MAIN BOARD p/n: EBT61381702

D2100
A1 A2 C

Black Lead on Floating Gnd

Black Lead on Floating Gnd

Chassis Gnd

9 10 11 12 13 14 15

To Test Control board: Disconnect all connectors. Jump STBY 5V from SMPS P813 Pin 13. Apply AC and turn on the Set. Observe Control board LED, if its on, most likely Control board is OK.

Note: IC53 (3.3V Regulator) routed to all X Boards * If the complaint is no video and shorting the points (AutoGen) causes video to appear suspect the Main board or LVDS cable. Note: LVDS Cable must be removed for Auto Gen to work.

3 4 3 4

2 1 2 1

Q102 Q101 IC802

A2 A1

D714 Q3205 Q710

E B C

1 4

D713

P600 n/c

HDMI1

IC803
C

P900

FPC

IR/Key Board p/n: EAB62028901

3D sync/ Motion Remote p/n: EBR72499601 B

Q1002

D810 IC1003 TUNER UDA55AL

C

Digital Video
C E B

IC2103

P1302

2 3 1

Q801

Q?

Analog Video

18. IF p 17. IF n 16. IF AGC 15. Reset 14. 3.3V 13. 1.26V 12. GND 11. CVBS 10. NC 9. SIF 8. NC 7. SDA 6. SCL 5. NC 4. NC 3. 5V 2. NC 1. NC

IC1004 IC3209
E

C B B E C

Q2105

P121 X Left to P203 Y-SUS Pin 1,2 3 4,5 Run VA Voltage nc Gnd Diode Check Open nc Gnd

P201

P204

P101
Power LED J1
To P900 Main A

P100
Ft Key Pad

TU2101

Motion To P1302 Main

Q2104 IC506 AV IN 2 L
123 2

Black Lead on Chassis Gnd

Y-DRIVE LOWER BOARD p/n: EBR69839201

Attached to front glass

P121 X-Board Left p/n: EBR71728101 P203 P204

P110 3.3V in on Pins 57~60

P202

P120 Va out on Pins 1~2 P205

P320 Va in on Pins 1~2 P201 P202

P310 3.3V in on Pins 57~60 P203

X-Board Center p/n: EBR71728401 P204

P321 Va out on Pins 1~2 P205

P320 Va in on Pins 1~2 P201

P310 3.3V in on Pins 57~60

P1302 3D Sync pin 12 (3.32V p/p) 60Hz Pin 10 should be high to turn on RF transmitter on Motion Remote board.

X-Board Right p/n: EBR71728501 P204 P205

P202

P203

50PZ950 LVDS P31 Control Board from P3200 Main Board Waveform Samples
P31 Control 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P3200 Main 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

RA1_- Video Signal

RXD TXD

RB1_- Video Signal P31 LVDS (Pin 14) 10Msec / 627.5mV Note: Pin 15 is Same but Inverted

RC1_- Video Signal P31 LVDS (Pin 16) 10Msec / 638mV Note: Pin 17 is Same but Inverted

CLK1_- Clock Signal P31 LVDS (Pin 19) 10Msec / 638mV Note: Pin 20 is Same but Inverted

P31 LVDS (Pin 12) 10Msec / 613mV Note: Pin 13 is Same but Inverted

Video Video Video Video CLK CLK Video Video Video Video Video Video

Video Video Video Video CLK CLK Video Video Video Video Video Video

Bottom Waveform at 2uSec RD1_- Video Signal P31 LVDS (Pin 22) 10Msec / 714.6mV Note: Pin 23 is Same but Inverted

Bottom Waveform at 2uSec RE1_- Video Signal P31 LVDS (Pin 24) 10Msec / 686.7mV Note: Pin 25 is Same but Inverted

Bottom Waveform at 2uSec RA2_- Video Signal P31 LVDS (Pin 28) 10Msec / 715.7mV Note: Pin 29 is Same but Inverted

Bottom Waveform at 2uSec RB2_- Video Signal P31 LVDS (Pin 30) 10Msec / 582.8mV Note: Pin 31 is Same but Inverted

Video Video Video Video CLK CLK Video Video Video Video Video Video

Bottom Waveform at 2uSec RC2_- Video Signal P31 LVDS (Pin 32) 10Msec / 695mV Note: Pin 33 is Same but Inverted

Bottom Waveform at 2uSec CLK2_- Clock Signal P31 LVDS (Pin 35) 10Msec / 716.5mV Note: Pin 36 is Same but Inverted

Bottom Waveform at 2uSec RD2_- Video Signal P31 LVDS (Pin 38) 10Msec / 778.2mV Note: Pin 39 is Same but Inverted

Bottom Waveform at 2uSec

Video Video Video Video CLK CLK

The reset of the waveforms look very similar to the ones shown.

Video Video Video Video Video Video

NOTE: LVDS P31 Information There are actually 40 pins carrying Video. 8 pins are carrying clock signals to the Control board.

WAVEFORMS: Waveforms taken using 1080P SMTP Color Bar input. All readings give their Time Base related to scope settings.

Disp_En

Bottom Waveform at 2uSec

Bottom Waveform at 2uSec

Bottom Waveform at 2uSec

50PZ950 Main Board (Front Side) Component Voltages

IC500 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC501 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC502 (+7V) Regulator 13.14V 17V 3.12V 1.79V 0.8V 0.67V 0V 7.11V (+0.9V_Core) Regulator 0V 5V 0V 0.8V 1.04V 3.29V 0.29V 0.99V IC505 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] IC506 Pin [1] [2] [3] (+3.3V_Normal / 3V3) Regulator 5V 5V 0V 0V 0V 0V Don't read 0.5V (freezes) 1.7V 3.3V 3.3V 3.3V 8.2V 0V 3.3V 5V (+5V_TU) Reg for Tuner 7.1V 5V 3.78V IC801 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] IC803 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] PC Sync Buffer 1.6V 1.6V 3.67V 1.87V 1.87V 4.43V Gnd 4.42V 1.88V 1.88V 3.67V 1.59V 1.59V 4 98V 4.98V RS232 Data Buffer 3.29V 5.56V 0V 0V (-5.46V) (-5.49V) 5.59V 0V 3.29V Gnd 3.28V 3.28V 0V (-5.5V) Gnd 3.29V IC1200 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC1201 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC1700 Pin [1] [2] [3] [4] [5] [6] [7] [8] USB1 5V Overcurrent 0V 5V 5V 3.28V 3.12V 5V 5V Gnd USB2 5V Overcurrent 0V 5V 5V 3.28V 3.12V 5V 5V Gnd IV0 Regulator 0V 5V 0V 0.8V 0.83V 5V 1.04V 1.04V Q2105 Q1002 Pin [B] [E] [C] Q2104 Pin [B] 0.2V [E] 0.9V [C] 0V Q710 Pin [1] [2] [3] [4] Q1001 3.25V 3.29V 3.25V 3.25V D716 Pin [B] 0V [E] Gnd [C] 17V Wireless 17V Control Pin [A1] [A2] [C] D717 Wireless 17V Switch 17V 0V 17V D2100 Tuner SIF Pin [A1] [A2] [C] HDMI CEC D714 HDMI CEC Pin Pull Up [A1] 3.28V [A2] 0V [C] 3.23V 5V Pull-Up for DDC_SCL/SDA3 0V 5V 4.84V 5V Pull-Up for DDC_SCL/SDA4 0V 5V 4.86V

(+2.5V_BCM35230) Pin Regulator [1] 5.02V [2] 2.54V [3] 1.28V (+3.3V_ST) Pin Regulator [1] 5.02V [2] 3.29V [3] 5.19V

LED +3.3V_TU Detection Pin [A1] 1.84V [A2] 0.14V [C] 0V

IC503

Tuner Pin CVBS [B] 3.6V [E] 4.28V [C] Gnd

50PZ950 Main Board (Back Side) Component Voltages

IC103 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC504 n/c Gnd 3.2V Gnd 3.02V 3.02V Gnd 3.2V IC1704 NRAM IC802 Pin [1] [2] [3] [4] [5] [6] [7] [8] Gnd Gnd Gnd Gnd 4.68V 4.68V 4.68V 4.68V PC EDID EPPROM IC3201 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC3204 Pin [1] [2] [3] Serial Flash 3.18V 3.18V 3.18V Gnd 0V 0V 3.18V 3.18V 3D_ASIC RESET_SWITCH 3 18V 3.18V Gnd 3.18V IC3203 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] Motion Remote 3.23V 3.23V 0.22V 0.22V 0.22V Gnd Gnd Gnd 3.20V 3.20V 3.29V 3 18V 3.18V 3.18V 3.20V Q101 Pin [1] [2] [3] [4] Q102 Pin [1] [2] [3] [4] Q602 RGB_DDC SDA Gnd 4.68V 3.20V 3.20V RGB_DDC SCL Gnd 4.68V 3.20V 3.20V Q801 PC Data Pin Buffer [B] 0.59V [C] 0.02V [E] Gnd Wireless Pin IR Pass [B] 0.50V [C] 0.02V [E] Gnd Wireless Pi P Pin IR Pass [B] 0.02V [C] 3.3V [E] Gnd EDID Write Pin Protect Buffer [B] 0V [C] 4.68V [E] Gnd D713 Pin [A1] [A2] [C] D715 Pin [A1] [A2] [C] D810 5V Pull-Up for DDC_SCL/SDA1 0V 5.01V 4.84V 5V Pull-Up for DDC_SCL/SDA2 0V 5.01V 4.84V

Q1003

(+1.5V_DDR) Pin Regulator 0 30V [1] 0.30V [2] 1.56V [3] 4.96V EEPROM for Micom Gnd Gnd 3.3V Gnd 3.3V 3.3V Gnd 3.3V

IV8 Pin Regulator G d [1] Gnd [2] 1.8V [3] 3.17V (+1.26V_TU) Pin Regulator [1] 0.04V [2] 1.28V [3] 3.17V

Q1004

IC601 Pin [1] [2] [3] [4] [5] [6] [7] [8]

IC2103

Wired IR Pin To Micro [B] 0.02V [C] 3.31V [E] Gnd Wired IR Pin To Micro [B] 0.60V [C] 0.02V [E] Gnd

5V Routing to Pi f Pin EDID for PC [A1] 4.97V [A2] 0.05V [C] 4.68V

Q3205

Q603

End of the 50PZ950 Presentation

This concludes the 50PZ950 Presentation

Updates 06/29/2011 g 1. Page 84 Y-Drive Waveform Checks corrected Peak to Peak values. 2. Page 185 Y-Drive Waveform Checks corrected Peak to Peak values. Updates 07/18/2011 Beginning on Page 45, Added additional 3D information and reorganized the 3D section. 1. Added pages 47 and 50 related to 3D information. 2. Corrected Jumper ID on SMPS slide 74. 3. Corrected SK101 connector information slide 75. 3 C t d t i f ti lid 75 4. Corrected waveform on slide 78. 5. Corrected connector number on slide 86.

Thank You.
Back to Pg 1

March 201 1

50PZ950

Plasma