Optimal Two-Dimension Common Centroid Layout Generation for MOS Transistors Unit-Circuit

Di Long1, Xianlong Hong1, Sheqin Dong1 Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, P. R. China longd02@mails.tsinghua.edu.cn We can express the mismatch of a parameter P mathematically in formula (1), Where Ap and S p are technology dependent area and distance proportionality constants for parameter P; variable D stands for the spacing between two transistors; W and L denote width and length of transistor channel respectively.

AbstractIn this paper, a general algorithm for fitting arbitrary channel width transistors in a two-dimension common centroid MOS transistors matrix is presented. The proposed algorithm guarantees the layout of transistors unitcircuit not only to be complete common centroid but also optimal in all the common centroid structures. A novel channel routing algorithm to implement common centroid routing is also proposed in the paper. Feasibility of the algorithm is demonstrated by practical analog transistors unit-circuits.

2 ( P ) =

2 Ap

I.

INTRODUCTION

Mismatch and parasitics induced by layout can greatly degrade the performance of analog circuits. It is well-known that the common centroid layout style can make the analog devices with strict match demands reach better match and less sensitive to the process variations. But it is very difficult for more than two match devices to generate completely optimal common centroid layout manually. Few trails can be found in the literature on common centroid layout generation for analog devices, which is an error-prone and laborious process manually. In [1], the algorithm can generate common centroid layout for capacitors with arbitrary capacitor ratio, but it is not applied to transistors. In [2], common centroid placement, symmetrical routing and parasitic balance are considered through a special optimization algorithm, but it is only restricted to device pairs. In [3], the algorithm can only construct one-dimension common centroid layout for MOS transistors, but one-dimension common centroid layout is sometimes slim and long, which is not desirable during placement and routing. Whats more, two-dimension common centroid layout generally provides better cancellation of gradients than one-dimension common centroid layout. In this paper, we advance a general algorithm for fitting arbitrary channel width transistors in a two-dimension common centroid MOS transistors matrix. Mismatch is defined as the process that causes processinduced, time-independent random variations in physical qualities of identically designed devices [4]. Nowadays, since the functionality of most analog circuits is based on relative characteristic parameters of analog devices rather than absolute value of those, mismatch puts a fundamental limit on the achievable circuit performance in a particular technology process.

According to the mismatch models, we can reduce the above two types of mismatches by reducing the distance between the centroids of the matched devices and the area of diffusion regions. Common centroid layouts can reduce the distance between the centroids to zero and cancel the effects of long-distance variations as long as these linear functions of distance. Even if the variations contain a nonlinear component, they still remain approximately linear over short distances. The more compact the common-centroid layout can be made, the less susceptible it becomes to nonlinear gradients. So the common centroid layouts can reduce the both items in formula (1) and is fit for all the matching analog devices. There are other layout styles, the mismatch of which has been measured and compared in [5]. It was found that the best layout style for minimizing mismatch of analog devices is common centroid layout. Definition 1: common centroid structure is a sequence or a matrix that is composed of device fingers and satisfies the following conditions: Coincidence: The centroid of the different matched devices should at least approximately coincide. Ideally, the centroids should exactly coincide, which is called the completely common centroid structure. Symmetry: The structure should be symmetric around both X-axe and Y-axe. Dispersion: The fingers of each device should be distributed throughout the structure as uniformly as possible. Compactness: The structure should be as compact as possible. Ideally, it should be nearly a square. Definition 2: chirality of a transistor is the value obtained by the fraction of right-oriented fingers it contains minus the fraction of left-oriented fingers it contains.

WL

2 + S p D2

(1)

This work is supported by National Nature Science Foundation of China: 90307005 and NSFC and Hongkong RGC joint Project: 60218004 and Hi-Tech Research & Development (863) Program of China 2004AA1Z1050.

0-7803-8834-8/05/$20.00 2005 IEEE.

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In Fig. 1, it is very clear that the chirality of M1 is 1, the chirality of M2 is -1/3 and the chirality of M3 is 0.
Finger=1

Finger=3

Finger=4

M1

M2

M3

0 (a) M1 M2 M2 M3 M3 M3 M3 M2 (b) 1 0 2 0 3 0 3 0 2

Fig. 1 (a) Common source current mirrors schematic (b) Stack of the schematic and the orientation of each finger

of the width must be the common-divisor of all the widths. So the vector W can be expressed as wNk, where Nk represents a k-dimension integer vector and w is an integer. According to the theorem 1 we can define the set of legal finger width, which is expressed in formula (2), where Ik represents a k-dimension integer vector. The smaller width is, the more fingers are, which makes the final routing more complex. So the finger width must be greater than a certain value, which can be determined by experiment. We set this value to be the length of channel. legal _ W = {w | wN k = W , N k / 2 = I k , w Lchnnel} (2) B. Convert the circuit schematic to diffusion graph To generate fingers sequence of MOS transistors with more shared source and drain regions and less dummy fingers, we must firstly construct the diffusion graph according to the original circuit schematics. The diffusion graph of a circuit is obtained by mapping each node in a CMOS circuit to a vertex of a graph and mapping each source and drain connection of transistor to multiple-edge, the number of which is the same with the finger number of the transistor. The diffusion graph of Fig. 2(a) is shown in Fig. 2(b). For each w in the set legal _ W , we can obtain a vector of fingers W/w, which describes finger numbers of all the transistors. Each vector W/w corresponds to a diffusion graph. Our algorithm is to find the optimal solution in all of these diffusion graphs.
Finger=4 d1 Finger=4 d2 Finger=4 d3 Finger=4 d4

Condition 1: chirality condition of transistor common centroid structure is that each matched device should possess equal chirality. The definition 1 is sufficient to construct common centroid structure for resistors and capacitors, but for transistors the definition 1 and condition 1 are together sufficient because the transistors having unequal chirality will experience orientation-dependent mismatch [6]. II. GENERATION ALGORITHM OF OPTIMAL TWODIMENSION COMMON CENTROID STRUCTURE FOR MOS TRANSISTORS Our algorithm is divided into the following five sub-steps. Inputs of the algorithm are transistor unit-circuit schematic and design rules. Outputs are optimal common centroid layouts of transistor unit-circuits. Before introducing the whole algorithm we will give some necessary definitions. Definition 3: stack is a chain of transistor fingers without any intervals, which partially builds an electronically correct layout and share the source and drain. In the stack each finger has the same channel width. Definition 4: common centroid array is a special stack, which must satisfy the definition 1 and condition 1. Definition 5: common centroid matrix is composed of multiple rows of stacks, which must satisfy the definition 1 and condition 1. In different rows the transistor fingers does not share source and drain. A. Decide the width of MOS transistor fingers Theorem 1: if there is a compact layout of completely common centroid array or matrix corresponding to a MOS transistor unit-circuit the finger number of each transistor must be even or at most there is only one odd number. Proof: if there is a finger ai of transistor A in the array or matrix and the finger ai is not located at centroid, there must be another finger aj of A centrosymmetric with ai. So the finger number of transistor A must be even. But if the finger ai is located at centroid the finger number of A must be odd. We use the vector W = {w1 , w2 ,..., wk }(wi N ) to represent the widths of all MOS transistors in the unit-circuit. Firstly, if we want to obtain the same width of fingers, value

M1 d1 M1 d4 M4 vss M3

M2 (a)

M3 vss

M4 d1 M1

M2 (b)

d2 d4

M4

vss M3

M2 (c)

d2

d3 d3 Fig. 2 (a) Common source current mirrors schematics (b) Diffusion graph corresponding to the schematics (c) Half diffusion graph of (b)

C. Generate Half-Euler trails To construct the common centroid array or matrix we firstly construct a stack composed by only half of the fingers and then abut the rest of mirrored copies. Definition 6: half diffusion graph G =< V , E > is a diffusion graph where the number of edges between any two vertices is half of that in original diffusion graph. Theorem 2: A transistors unit-circuit can be constructed as the style of stack if and only if there is at least an euler-trail in the diffusion graph.

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Proof: We can substitute all the edges with corresponding fingers and all the vertices with nets in the euler-trail. Connecting all the same gates and source/drain nets, we will obtain layout. We substitute all the fingers with edges and all the nets with vertices. Thus, the interlaced sequence of vertices and edges obtained by the above method is an euler-trail. If G is not an Euler graph, we must add additional edges to convert it to an Euler graph. According to the graphical theorem that the number of odd degree vertices must be even, we group all the vertices two by two and add a virtual edge between each group of the two vertices. Problem 1: pair-grouping problem is to generate all the grouping solutions if there are even different objects and group them two by two. Theorem 3: Algorithmic complexity of the problem 1 is

sequence. In Fig. 3, the capital characters represent edges in diffusion graph and the Arabic numerals represent vertices.
(a) 0A1A0B2B0C3C0D4D0 (b) 0A1A0B2B0C3C0D4D0D4D0C3C0B2B0A1A0 Fig. 3 (a) Half-Euler trail (b) Common centroid array induced by (a)

For the two-dimension structure, we list the algorithm to obtain the common centroid matrix as follows, which is applied to each Half-Euler trail: 1. Different numbers of rows corresponds to different twodimension common centroid structures, so we use the formula (4) to calculate the maximal numbers of rows;

RowNummax = EdgeNumof (halfEulerTrail ) (4)

2. For a given RowNum use the formula (5) to calculate the number of fingers in each row. 3. Divide the half Euler trail and the reverse Euler trail by EveryRowMOSNum respectively and then there will be several intact rows and possibly, there are two rows, the finger number of which is less than EveryRowMOSNum. We place the intact rows from top to bottom one by one and abut the two half-baked rows. If the two half-baked rows can not consist of an intact row we can add another more dummies between the intervals to make outline of the structure rectangular. In the Fig. 4, the character X stands for dummy and the character v stands for virtual net, which has no connections with any other nets.
(a) 0A1A0B2B0C3C0D4D0 0A1A0B2B0 0A1A0B2B0C3C0 0C3C0D4D0 (c) 0D4D0XvX0D4D0 (b) 0D4D0C3C0 0C3C0B2B0A1A0 0B2B0A1A0 Fig. 4 (a) the half-Euler trail (b) Common centroid matrix induced by (a) with four rows (c) Common centroid matrix induced by (a) with 3 rows EdgeNumof (halfEulerTrail ) 2 EveryRowMOSNum = RowNum

n! , where the n represents the number of the n/2 2 (n / 2)!

different objects. Though the algorithmic complexity obviously increases with the augmentation of n, we abandon the solutions with many dummies, which correspond to the virtual edges. Thus the value of n is often small. We use the set add _ edge to represent the added edge set, which is the minimal edge set to convert a non-Euler graph to an Euler graph. In formula (3), Spg represents the whole solution space of problem 1. G represents half-Euler graph. We name each Euler trail in G Half-Euler trail.

(5)

add _ edge = {(vi , v j ) | (i, j ) , S pg }

G =< V , E add _ edge >
Problem 2: searching all Euler trails problem.

(3)

The algorithmic complexity of problem 2 is nonpolynomial. Considering that the more concentrative fingers of the same transistor are, the simpler routing of source/drain regions and gates is, we should make the edges denoting the fingers of the same transistor as concentrative as possible. We use the following rules to obtain the simplified halfEuler graph Gs: for any two vertices in the graph G if the number of edges that belong to G is even we use two edges to substitute those edges; if that is odd we use one edge to substitute those edges. Theorem 4: Gs is also an Euler-graph. The substitution greatly decreases the number of edges, which will reduce the algorithmic complexity of problem 2. For each Half-Euler trail in Gs we use the method opposite to the above one to obtain intact Half-Euler trail in G . D. Convert Half-Euler trail to common centroid structure For one-dimension structure, we can directly abut the other Half-Euler trail with the original one in opposite

Theorem 5: All the one-dimension and two-dimension structures obtained by our algorithm must correspond to the correct circuit and satisfy the definition 1 and condition 1. E. Evaluate the solution We use the cost function (6) to evaluate each common centroid structure.

C = Cdiff + Carea + Cratio + Cdummy + Cconnect (6)

Cdiff minimizes the parasitics of all diffusion regions; Carea minimizes area of the whole layout; Cratio makes outline of the common centroid structure approximate square; Cdummy minimizes the number of dummies; Cconnect minimizes the parasitics of all interconnections. III. COMMON CENTROID ROUTING STYLE

Theorem 6: All the centroids of Nets in the common centroid structure are also coincident. The routing rules can be expressed as follows:

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In the top half matrix metals connecting the nets in the same row are routed in the top channel of this row and in bottom half matrix those are routed in the bottom channel; In the top half matrix metals connecting the odd number nets between rows are in the left channel of matrix and in the bottom half matrix those are in the right channel. In the top half matrix metals connecting the even number nets between rows are in the right channel of matrix and in the bottom half matrix those are in the left channel.

Fig. 7 (a) Common source current mirrors composed of four transistors with the same channel width (b) Common Centroid layout without dummies of (a)

Fig. 5 Common centroid routing style

In the Fig. 5, we only use lines with different colors to stand for different nets. In actual layout we use metal-1 for horizontal routing and metal-2 for vertical routing. IV. EXPERIMENTAL RESULT AND CONCLUSION

We have implemented the whole algorithm in C++. All the results of Fig. 6, Fig. 7 and Fig. 8 are gotten on the platform of Solaris 5.2 of Sun-V880. In this paper a general algorithm for fitting arbitrary channel width transistors in a two-dimension common centroid MOS transistors matrix is presented and we can guarantee it is the optimal. Feasibility of the algorithm is demonstrated by the practical unit-circuits.

Fig. 8 (a) Cascode current mirror schematics composed of four transistors with different channel width (b) Common Centroid layout without dummies of (a)

REFERENCES
[1] DiaaEldin Sayed and Mohamed Dessouky, Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio, in Proc. IEEE DATE, 2002. J. D. Bruce, H. W. Li, M. J. Dallabetta and R. J. Baker. Analog Layout using ALAS, IEEE J. of Solid-State Circuits, 31(2): 271-274, Feb. 1996. Ravindranath Naiknaware and Terri Fiez, COMS Analog Circuit Stack Generation with Matching Constraints, in Proc. ICCAD, pp. 371-375, Nov. 1998. M. J. M. Pelgrom, A. C. J. Duinmaijer, A. P. G. Welbers, Matching properties of MOS transistor, IEEE J. of Solid State Circuits, vol. SC-24, no. 5, pp. 1433-1440, Oct. 1989. J. Bastos, M. Steyaert, B. Graindourze, W. Sansen, Matching of MOS Transistors with Different Layout Styles, Proc. IEEE Int. Conference on Microelectronic Test Structures, pp. 17-18, March 1996. F. K. Baker and J. R. Pfiester, The Influence of Tilted Source-Drain Implants on High-Field Effects in Sub-micrometer MOSFETs, IEEE Trans. on Electron Devices, Vol. 35, #12, 1988, pp. 2119-2124.

[2]

[3]

[4]

[5]

Fig. 6 (a) Common source current mirrors composed of three transistors with different channel width (b) Common Centroid layout with dummies of (a)

[6]

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