Introduction to Memory Testing

Introduction to Memory Testing

Chip-Level

Logic

Embedded Memory Memory Access

PLL

TAP JTAG Boundary Scan

Figure 58.

Introduction to Memory Testing

Memory Test Fundamentals - 175

Types of Memories

Types of Memories
Row/Word-Address

Select

Select

Column/Bit-Data

Storage

Column/Bit-Data

6 Transistor SRAM Cell Row/Word-Address

Select Storage Column/Bit-Data 1 Transistor DRAM Cell Row/Word-Address

Storage

Select

Column/Bit-Data 2 Transistor EEPROM Cell Figure 59. Memory Types

Memory Test Fundamentals - 176

Memory Organization

Memory Organization

Data Bus : To Multiple Memory Arrays

Address Bus : To Multiple Memory Arrays

Bus Enable Data In Memory : data width by address depth 32 x 512 Address In Data Out

Read/WriteB

Output Enable

Memory Array Address Decode to Row Drivers Data Decode to Column Drivers Control Circuitry to Read, Write, and Data Output Enable

Control Signals : Individual Signals to this Memory Array

Figure 60.

Simple Memory Organization

Memory Test Fundamentals - 177

Memory Design Concerns

Memory Design Concerns

Chip FloorPlan

Memory 1 M e m o r y 3

Memory 2
- Aspect Ratio - Access Time - Power Dissipation

Memory 4

Figure 61.

Memory Design Concerns

Memory Test Fundamentals - 178

Memory Integration Concerns

Memory Integration Concerns

Chip FloorPlan

Memory 1 M e m o r y 3

Memory 2
- Routing - Placement & Distribution - Overall Power Dissipation

Processor Local Logic Memory 4

Figure 62.

Memory Design Concerns

Memory Test Fundamentals - 179

Embedded Memory Testing Methods

Embedded Memory Testing Methods

32 Embedded Microprocessor Core Data 24 Address 3 Embedded Memory Array

Control Functional Memory Test Data Address Control 32 24 3 Embedded Memory Array

Direct Access Memory Test BIST Controller Done Embedded Memory Array BIST Memory Test Fail

Invoke Reset Hold

Figure 63.

Embedded Memory Test Methods

Memory Test Fundamentals - 180

The Basic Memory Testing Model

The Basic Memory Testing Model

column # -->

row # --> 0

row # --> 1

data bit cell

row # --> 2

Figure 64.

Simple Memory Model

Memory Test Fundamentals - 181

The Stuck-At Bit-Cell Based Fault Models

The Stuck-At Bit-Cell Based Fault Models

Data in Bit Cells May be Stuck-At Logic 1 or Logic 0 word stuck-at data value 1110

single bit stuck-at 1

address A031-->

address A032-->

address A033-->

single bit stuck-at 0

Figure 65.

Bit-Cell and Array Stuck-At Faults

Memory Test Fundamentals - 182

The Bridging Defect-Based Fault Models

The Bridging Defect-Based Fault Models

Data in Bit Cells May be Bridged To Other Bit Cells

horizontal (row) bit bridging

1 vertical (column) bit bridging 1

random bit bridging

0 word bridging unidirectional one way short

word bridging bidirectional two way short

Figure 66.

Array Bridging Faults

Memory Test Fundamentals - 183

The Decode Fault Model

The Decode Fault Model

Column Decode X C O L Select Lines R O X Row Decode stuck-at faults result in always choosing wrong address R o w D e c X o d e Column Decode bridging faults result in always selecting multiple data bits 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 X 1 0 1 1 W 0 1 1 1 X X

Row Decode bridging faults result in always selecting multiple addresses

Column Decode stuck-at faults result in always choosing wrong data bit

Select Line faults result in similar array fault effects Figure 67. Decode Faults

Memory Test Fundamentals - 184

The Data Retention Fault

The Data Retention Fault

Data around target cell is written with complement data

Complementary Data Around Target Cell

Address 21 = A

Address 22 = 5

Address 23 = A

Address 24 = 5

alternating 5s and As make for a natural checkerboard pattern Figure 68. Data Retention Faults

Memory Test Fundamentals - 185

Diagnostic Bit Mapping

Diagnostic Bit Mapping

Blue: Pass Red: Fail Column Data Fault

Physical Memory Organization Row Address Fault

Logical Memory Organization Stuck-at Bit Faults

Physical Memory Organization Bridged Cell Faults

Physical Memory Organization Figure 69. Memory Bit Mapping

Memory Test Fundamentals - 186

Algorithmic Test Generation

Algorithmic Test Generation

Addr(00) to Addr(Max) Write(5)-Initialize Increment Address Address 00 --> Address 01 --> Address 02 --> 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0

Address 03 --> Addr(00) to Addr(Max) Read(5)-Write(A)-Read(A) Address 04 --> Increment Address Address 05 --> Addr(00) to Addr(Max) Read(A)-Write(5)-Read(5) Increment Address Address 06 --> Address 07 --> Address 08 -->

Address 09 --> Addr(Max) to Addr(00) Read(5)-Write(A)-Read(A) Address 10 --> Decrement Address Address 11 --> Addr(Max) to Addr(00) Read(A)-Write(5)-Read(5) Decrement Address Addr(Max) to Addr(00) Read(5) Decrement Address Read (A)-------> Write (5) Read (5) Increment Address Address 12 --> Address 13 --> Address 14 --> Address 15 --> Address 16 --> Address 17 --> Address 18 --> Address 19 --> Address 20 --> Address 21 --> Address 22 --> Address 23 -->

Figure 70.

Algorithmic Test Generation

Memory Test Fundamentals - 187

Memory Interaction with Scan Testing

Memory Interaction with Scan Testing

Boundary at some level of scanned registration or pipelining away from the memory array

Data Detection of incoming signals Address Memory Array

Data Control of outgoing signals

Control

scan-memory boundary Minimum Requirement Detection up to Memory Input and Control of Memory Output Concern: the Logic Between the Scan Test Area and the Memory Test Area is not Adequately Covered

Non-Scanned Registration Inside the Boundary but Before the Memory Test Area Results In a Non-Overlap Zone Figure 71. Scan Boundaries

Memory Test Fundamentals - 188

Scan Test Memory Modeling

Scan Test Memory Modeling

The Memory Array is Modeled for the ATPG Engine so the ATPG Tool can use the Memory to Observe the Inputs and Control the Outputs

Data In

Din Memory Array

Dout

Data Out

Address

Ain

ATPG Model

Control

Read/Write

Scan Architecture

Figure 72.

Memory Modeling

Memory Test Fundamentals - 189

Scan Test Memory Black-Boxing

Scan Test Memory Black-Boxing

Boundary at some level is blocked-off as if the memory was cut out of the circuit Scan Mode Control of outgoing signals Gated Data Out Memory Array can be Address Removed from Netlist for ATPG Purposes Control Multiplexed Data Out All Registers are in the Scan Chain Architecture

Data In Detection of incoming signals

scan black-box boundary Observe-Only Registers used for Detection of Memory Input Signals Gate or Multiplexor is used to Block -- fix to a known value -- the Memory Output Signals

Figure 73.

Black Box Boundaries

Memory Test Fundamentals - 190

Scan Test Memory Transparency

Scan Test Memory Transparency

Boundary at some level is blocked-off as if the memory was cut out of the circuit

Input is passed to Output as the Form of Output Control Bypass Data Out Memory Array can be Removed from Netlist for ATPG Purposes

Data In Detection of incoming signals Address

Control

scan black-box boundary Observe-Only Registers used for Detection of Memory Input Signals Multiplexor is used to pass the input directly to the Output

Figure 74.

Memory Transparency

Memory Test Fundamentals - 191

Scan Test Memory Model of The Fake Word

Scan Test Memory Model of The Fake Word

Detection of Incoming data signals done here Boundary at some level is blocked-off as if the memory was cut out of the circuit Input is passed to Output with Registration Data In Memory Array can be Address Removed from Netlist for ATPG Purposes Control Bypass Data Out In Ideal Sense Timing should also be matched

scan black-box boundary Observe-Only Registers not needed on data since register emulates memory Register and Multiplexor is used to emulate memory timing and output

Figure 75.

The Fake Word Technique

Memory Test Fundamentals - 192

Memory Test Requirements For MBIST

Memory Test Requirements For MBIST

Data Bus : Possibly to Multiple Memory Arrays

Address Bus : Possibly to Multiple Memory Arrays

Data In Memory : data width by address depth 32 x 512 Address

Data Out

Read/WriteB

Output Enable

Memory Array Address Decode to Row Drivers Data Decode to Column Drivers Control Circuitry to Read, Write, and Data Output Enable

Control Signals : Individual Signals to this Memory Array Test Must Access the Data, Address, and Control Signals in order to test this Memory

Figure 76.

Memory Test Needs

Memory Test Fundamentals - 193

Memory BIST Test Requirements

Memory BIST Test Requirements

Chip Level

Invoke Retention Debug

Algorithm Controller Address Generator Data Generator Memory Array(s) Comparator

Done Fail Debug_data

INPUTS Invoke : Start BIST Retention : Pause BIST and Memory Clocking Debug : Enable BIST Bitmap Output OUTPUTS Fail : A Memory has Failed a BIST Test Done : Operation of BIST is Complete Debug_data : Debug Data Output OPERATIONS Address : Ability to Apply Address Sequences Data : Ability to Apply Different Data Sequences Algorithm : Ability to Apply Algorithmic Control Sequences Comparator: Ability to Verify Memory Data
Figure 77. Memory BIST Requirements

Memory Test Fundamentals - 194

An Example Memory BIST

An Example Memory BIST

Invoke
Comparator

done Fail Hold_out Bitmap_out Dout

Retention Release Bitmap Din Ain Write_en Read_en

Algorithm Controller Address Generator Data Generator

Memory DI Array Do A WRB CEB

Clk INPUTS Invoke : invoke the BIST (apply muxes and release reset) Retention : enable retention algorithm and pause Release : discontinue and release pause Bitmap : enable bitmap output on fail occurrence OUTPUTS Fail : sticky fail flag -- dynamic under bitmap Done : operation of BIST is complete Bitmap_out : fail data under bitmap Hold_out : indication of pause
Figure 78. An Example Memory BIST

Memory Test Fundamentals - 195

MBIST Chip Integration Issues

MBIST Chip Integration Issues

Chip Level bitmap_out1 Memory Array with BIST done1 Memory Array with BIST done2 Hold_1 Memory Array with BIST Hold_2 done3 Hold_3 Memory Array with BIST Hold_4 done4 fail4 fail 1-4 done 1-4 Invoke : a global signal to invoke all BIST units Reset : a global signal to hold all BIST units in reset done Bitmap : a global signal to put all BIST units in debug mode Hold_# : individual hold signals to place memories in retention or to select which memory is displayed during debug done : all memory BISTs have completed fail : any memory BIST has detected a failure diag_out : the memory BIST not in hold mode will present debug data Figure 79. MBIST Integration Issues fail diag_out so s1 fail3 bitmap_out4 fail2 bitmap_out3 fail1 bitmap_out2

Invoke Reset Bitmap

Memory Test Fundamentals - 196

MBIST Integration Concerns

MBIST Integration Concerns

Invoke Reset Bitmap

bitmap_out1 Memory Array with BIST done1 Memory Array with BIST done2 fail2 bitmap_out3 fail1 bitmap_out2

Hold_1 Memory Array with BIST Hold_2 done3 Hold_3 Memory Array with BIST Hold_4 done4 fail4 fail 1-4 done 1-4 Invoke : must be a logic 0 when BIST is not enabled Reset : should be a logic 0 when BIST is not enabled Bitmap : should be a logic 0 when BIST is not enabled Hold_# : should be a logic 0 when BIST is not enabled

fail3 bitmap_out4

so s1

done

fail diag_out

done : should not be connected to package output pin when BIST not enabled fail : should not be connected to package output pin when BIST not enabled diag_out : should not be connected to package output pin when BIST not enabled Figure 80. MBIST Default Values

Memory Test Fundamentals - 197

MBIST Power Concerns

MBIST Power Concerns

done M A 1-n e r m r o a r y y s with fail 1-n I M n B debug d I e S hold_l1 p T e s hold_l2 n d hold_1m e n t Bank 1 scan_out 1-n n invoke 1-m done M A 1-m e r m m r o a r y y s with m I M n B d I e S p T e s n d e n t Bank 2 n m diag_out 1-m so s1 Invoke : global signal invokes bank 1 BIST Reset : global signal holds bank 1 BIST in reset Bitmap : global signal that enables BIST debug diag_out fail done Hold_# : paired hold signals to place memories in retention or to select which memory is displayed during debugz done : bank n memory BISTs have completed fail : any memory BIST has detected a failure diag_out : the memory BIST not in hold will present debug data Figure 81. Banked Operation fail 1-m

n Invoke n Reset n Bitmap

Hold_1 Hold_2 Hold_n

Memory Test Fundamentals - 198

MBIST Design -- Using LFSRs

MBIST Design -- Using LFSRs

LFSR - PRPG

DQ CLK

DQ

DQ

MBIST Address Functional 5 A 0 F MBIST Data In Functional Data In MBIST Functional Functional & MBIST Data Out Control Data Out

Memory Array
Data

DQ CLK LFSR - MISR Figure 82.

DQ

DQ

LFSR-Based Memory BIST

Memory Test Fundamentals - 199

Shift-Based Memory BIST

Shift-Based Memory BIST

The Address sequence can be shifted both forward and backward to provide all addresses The Data sequence can be shifted across the data lines, and can also provide data for a comparator 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0

Address

Memory Array
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Data

0 1 0 0 1 0

Read/Write

The Control sequence can be shifted across the read-write or output enable or other control signals

Figure 83.

Shift-Based Memory BIST

Memory Test Fundamentals - 200

ROM BIST

ROM BIST

MBIST Functional Address

Read-Only Memory Array

MBIST Functional Read Control

Functional Data Out

Data Out

MBIST

DQ CLK LFSR - MISR Figure 84.

DQ

DQ

ROM BIST

Memory Test Fundamentals - 201

Memory Test Summary

Memory Test Summary

Memory Testing Fundamentals Summary Memory Testing is Defect-Based Memory Testing Is Algorithmic Different Types of Memories - Different Algorithms A Memory Fault Model is Wrong Data on Read Memory Testing Relies on Multiple-Clue Analysis A Memory Test Architecture may CoExist with Scan A Memory Can Block Scan Test Goals Modern Embedded Memory Test is BIST-Based BIST is the Moving of the Tester Into the Chip BIST-Based Testing Allows Parallelism Parallel Testing Impacts Retention Testing Parallel Testing Impacts Power Requirements Parallel Testing Requires Chip-Level Integration
Figure 85. Memory Test Summary

Memory Test Fundamentals - 202