2009 Second International Conference on Future Information Technology and Management Engineering

A new subcarrier demodulator of satellite telemetry approaching to the ideality based on the digital signal
Liu Suxiao, Xiong Huagang, Feng Wengquan, Zhao Hongbo
School of Electronics and Information Engineering. Beijing University of Aeronautics and Astronautics, Beijing, China e-mail: liusuxiao@gmail.com
Abstract: In the deep space communication under the USB(Unified S-Band) system, the channel coding is generally used in the telemetry down-link. To get the coding gain, the subcarrier demodulation model needs to work reliably under the low Es/No. In this paper, a new BPSK subcarrier demodulation model of digital signal is introduced. This demodulation model is able to work well when the Eb/N0 is up to 1dB, also its demodulation loss is very low. So it is applicable for the bad telemetry channel Keywords: BPSK demodulation; demodulation; satellite communication; telemetry

CCSDS [1] (Consultative Committee for Space Data Systems) has convolution code, RS code etc. If we want to obtain coding gain in bad deep space exploration environment, subcarrier demodulator must be stability locked at very low Eb/N0. So BPSK demodulator with high performance, parameter programmable and stable demodulate under extraordinary low signal-to-noise is very helpful in satellites test and application. An all-digital BPSK subcarrier demodulator used in the deep space communication is introduced in this paper. II. STRUCTURE AND PRINCIPLE OF THE DEMODULATOR

I.

BACKGROUND

In order to communicate and ranging in deep space communication, Unified S-Band System was often employed in the deep space exploration. The telemetry under this system often uses BPSK modulation combined with channel coding in practical application. The ways of space transmit channel coding criterion suggested by the
I1 ( n )
cos(lTn + )

A. Structure Subcarrier demodulator is composed of downconversion module, carrier synchronous module and symbol synchronization module. Structure of the subcarrier demodulator is given in Fig. 1 [2, 3].

I 2 (n)
I 3 ( n)

L(n) = Ae j(1T n+) 2

'

y (t )

sin(lTn + )

Q3 (n)

Q1 ( n)

Q2 (n)

Figure 1. Block diagrams of demodulator

After adjusting input BPSK signal, subcarrier demodulator uses A/D sampling at constant Frequency. The signal sent into down-conversion module, then changed into zero intermediate frequency through quadrature down-conversion. Setting decimation and interpolation times to resample the sampling frequency according to BPSK bit rate makes Sampling frequency reduce to 16 times of bit rate, which in result, working parameter of demodulator becomes flexible and variable. Adjusting signal amplitude by AGC (Automatic Gain Control) can keep invariable of the baseband signal power which is input to carrier synchronous module. The key of demodulation is carrier synchronization, which means recovering inphase local carrier with input signal. Two quadrature signals I and Q are synchronized by Costas loop with hard limited at inphase branch [4], then the original data can be recovered. Symbol synchronization
978-0-7695-3880-8/09 $26.00 2009 IEEE DOI 10.1109/FITME.2009.53

module uses inphase - midphase symbol synchronizer to recovery modulated information. The advantages of this structure are as follows 1) The down-conversion, resample and symbol synchronization are divided from carrier synchronization. Carrier synchronization loop and symbol synchronization loop are completely independent, which is important to the system stability and has several merits compared with conventional demodulator: a) Short feedback branch, small delay and better system stability; b) Each parts of demodulator are independent and easy to simulation, analyze, design and hardware debug. 2) An improvement was made to Costas loop. That is eliminate carrier by complex multiplier which can

191

effectively avoid generating harmonic component. This improvement can remove branch filter, simplify Costas loop structure, shorten feedback branch length, and increase loop stability. B. Principle of demodulator Input PSK signals can be described as follows (1) y (t ) = Ad (t ) cos(c t + ) + n(t ) A stands for the input BPSK amplitude, d(t) is the base band data modulation, c is the angular frequency of the received carrier, is the initial phase of carrier and n(t) is the gaussian white noise. Let the sample frequency is f =1/T. The input signal can be changed into zero median frequency by digital down convertor, which can be written as I1(n) =1/ 2Ad(n){cos[(c l )Tn +( )] +cos[(c +l )Tn +( +)]}+ nI' (nT) (2) Where, l is local carrier frequency, is initial phase of local carrier. =c-l is the frequency differences between input carrier and local oscillator frequency. Input frequency l is close to c which makes the frequency of the output signal is close to zero. '=- is the phase differences of the input and local carrier. After decimation, interpolation and automatic gain control, the signal of the input carrier synchronizer can be written as I 2 ( n ) = 1 / 2 A1 d ( n ) cos( T ' n + ') + n I'' ( nT ' ) (3)
' '' ' Q 2 ( n ) = 1 / 2 A1 d ( n ) sin( T n + ') + nQ ( nT )
' Q (n) =1/ 2Ad(n){sin[(c l )Tn +( )] +sin[(c +l )Tn +( +)]}+ nQ(nT) 1

The main function of loop filter is filtering out high frequency component in error signal and supporting a short memory for phase-lock loop. The filter can make sure the loop rapidly recapture signal when it loses lock because of instantaneous noise. The tracking and stability character of the loop are decided by the loop filter. A parameter configurable ideal integrate loop filter [8] is used which can make demodulator adjust parameter according to its requirement. The continue time transfer function of the ideal integrate loop filter can be written as follows 1 + s 2 (6) F ( s) = It is transferred into discrete system by bilinear transformation and can be written in the following form (7) 2 T T 1 1
F ( z ) = F ( s)

s 1

Where C1 and C2 are given as follows [5, 9]

C1 = (

2 1 z 1 ) s= ( T 1+ z 1

=(

2 1

)+

1 1 z 1

= C1 + C2

1 z 1

2 T ) 1 2 1

(8) (9)

C2 =

Fig. 2 shows the structure of loop filter [9, 10].

Where T ' = M T , M N . By means of setting different M, N, input sampling rate of carrier synchronous loop can be kept constant or close to 16 times of the bit rate, in this way the demodulation loop structure keeps changeless as long as adjusting the decimation or interpolation times of the programming down-conversion module. Where Y(n) =I3(n)+ jQ(n) =1/2Ad(nej(Tn+') +ejn(T ) , the output NCO ) 3 1 (Number Controlled Oscillator) carrier signal is complex form, the output signal is L(n) = Ae j( T n+) , the signal will be 2 changed into I3(n)+ jQ(n) =Y(n)L(n) =1/2AAd(n)ej(( )Tn+(')) +ejn'(T ) after 3 1 2 handling by complex multiplication. Where K = 1/ 2 A1 A2 2 = 1 = ' (4) I 3 ( n ) = K d ( n ) c o s ( 2T 'n + ) + N I (T 'n )
' '

Figure 2. Block diagrams of loop filter

'

'

'

' Q 3 ( n ) = K d ( n ) s in ( 2T n + ) + N

(T 'n )

When the carrier loop is locked, 20 and is small. Ignoring noise, the output signal approximate is as follows (5) I3 (n ) K d (n ) Signal I3(n) contains demodulation information, all required information can be demodulated. C. carrier synchronous loop Improved Costas loop [5, 6] has been used in carrier synchronous. The differences between conventional and the improved Costas loop are that the I branch signal, after being hard-limited, is timed with Q branch signal to get the phase error signal. The improved Costas loop has simpler hardware structure with wider range of linearity and higher capture ability than the conventional Costas loop [5, 7].
Q 3 (n ) 0

D. Symbol synchronization loop Symbol synchronization loop is realized by inphasemidphase loop [11]. At the beginning NCO outputs PCM clock with 16 times bit rate, then inphase integrate and dump module finishes an integration and zero clearing at rising edge of PCM clock. Midphases integrate and dump module delays 1/2 clock cycle and finishes an integration and zero clearing at falling edge of PCM clock. The integration value, outputted by inphase and midphase integrates and dumps, enters phase detector to compute timing error. Timing error enters loop filter and then controls NCO to adjust output frequency. After synchronization, the output of NCO is PCM clock, and the latch value of inphase integrate and dump can get the corresponding PCM data by soft or hard decision. III. RESULTS AND DISCUSSION Loop signal-to-noise ratio is critical parameter to keep demodulator stable when working under low signal-tonoise ratio, and also a critical factor which affects error rate of telemetry subcarrier demodulator. The main reason of creating error code is the noise of the channel and demodulator itself. The channel noise can be described as input signal-to-noise ratio. The demodulator noise is composed of phase noise of carrier synchronous loop and timing noise of symbol synchronous loop. Furthermore, the square loss of carrier synchronous loop affects the loop signal-to-noise ratio directly.

192

A. phase noise of carrier synchronous loop The phase noise of carrier synchronous loop is caused by carrier phase jitter. Bit error rate performance has close relationships with signal-to-noise ratio at receiving end and the loop signal-to-noise ratio. The calculation formula of bit error rate is as follows [12] 1 (10) P ( ) = E r fc c o s ( )
E

stands for the signal-to-noise ratio at receiving end (Eb/N0), is phase noise of demodulator. the probability density of phase noise can be written as follows [12] (11) e c o s ( ) f ( ) = 2 I 0 ( ) is signal-to-noise ratio in loop (SNRL), I0() is modified Bessel function of first kind. When (11) is substituted into (10) and its mathematic expectation [12] is calculated, then the evaluated can be shown as follows c o s ( ) 1 (12) e PE ( ) = E r fc c o s ( ) d 2 2 I 0 ( ) Signal-to-noise ratio of the demodulator receiving end is usually invariable in short term. When the signal-tonoise ratio is fixed, the relationships of error rate and signal-to-noise ratio in loop under different signal-to-noise ratio can be obtained. Fig. 3 shows its relationships.

Figure 4. The SNR to the bit error rates of different loop bandwidth

The Fig. 4 illustrates that under the same signal-tonoise ratio when the loop bandwidth is small (n is small), the error rate performance will be better. So it should smallest the loop bandwidth as much as possible in the allowed capture time and range. B. Square loss of carrier synchronous loop Square loss [13] is another reason of the performance degradation of the demodulator. Square loss is created mainly by noise multiplying noise and noise multiplying component of signal. It makes deterioration of signal-tonoise ratio in loop, and then affects demodulator performance. When using NRZ code, calculation formula of Costas loop square loss can be written as follows [7] (16) S L = erc 2 ( Eb N 0 ) SL is the square loss of signal-to-noise ratio in loop. Fig. 5 shows the loss of signal-to-noise ratio in loop caused by square loss under different signal-to-noise ratio.

Figure 3. The loop SNR to the bit error rates of different SNR

Fig. 3 illustrates that with the same signal-to-noise ratio, the higher of the signal-to-noise ratio in loop is, the smaller of bit error rate is. Calculation formula of the signal-to-noise ratio in loop is given by E R (13) SN R = b b
L

N o BL

Where Eb is average signal energy of one bit, N0 is spectral noise power density, Rb is bit rate, BL is loop bandwidth. (14) n 2
BL =

Figure 5. The squaring lost to the loop SNR

The Calculation formula (13) illustrates that, the signal-to-noise ratio in loop is changed with signal-tonoise ratio, so the curve of error rate performance are different. usually equals with 0.707. When (14) is substituted into (13), it can be written as follows E R R b Eb R E 8 (15) SNR = b b = 1.886 b b
L

(1 + 4 )

When Eb/N0 is greater than 3dB, affection to the signalto-noise ratio in loop is less than 0.5dB. In order to find out the affection to error rate by square loss, the degradation of signal-to-noise ratio in loop is calculated and substituted into (12), and then relationships of error rate performance and signal-to-noise ratio can be obtained. Fig. 6 shows their rules.

N o BL

When (15) is substituted into (12), the variation rule of error rate performance will be changed with signal-tonoise ratio under different loop bandwidth. Fig. 4 shows the variation rule.

(1 + 4 )
2

No

n N o

193

loss is less than 1dB. With the same Eb/N0, high bit rate has higher error rate. Thats because with low bit rate the demodulation loss is increased (the out of band noise increases and negative feedback neutralizes part of signal powder). However, during space transmission, when the transmit power and the space environment is the same, the lower bit rate is, the bigger Eb/N0 is. For example, when the bit rate is changed from 4096bps to128bps, Eb/N0 will be increased nearly 15dB which is pretty bigger than demodulation loss. Thats why the demodulator has better error code performance with low bit rate under the same transmit power.
Figure 6. The SNR to the bit error rates of different loop bandwidth

IV.

CONCLUSION

The affection of square loss is limited when it has small loop bandwidth and high signal-to-noise ratio. Oppositely, the square loss will cause rather large affection to the demodulator. C. Timing error of symbol synchronous loop Symbol synchronous loop will create timing error (=T/2) because of clock jitter [12]. T is sampling period. Substituting T into probability density function will gets function (17) (17) 2 T T , 2 ) T 2 Code crosstalk is a problem for timing error. When it happens between the neighbor code-element, the code crosstalk can be calculated by autocorrelation function T (18) R ( ) = p ( t ) p ( t + )d t
f ( ) =
T e 2 I 0 (

The structure and principle of a new BPSK subcarrier demodulation model of digital signal is introduced in this paper. The character of the demodulator was analyzed and the test results were given. The demodulation loss is less than 1dB by designing loop parameter. The bit error ratio has better performance and can stablely work under low signal-to-noise ratio. REFERENCES
[1] [2] CCSDS, "TM Synchronization and Channel Coding," , C. C. F. S. Systems, Ed., 2003. M. R. Yuce, "A differential-based multiple bit rate PSK receiver: Theory, architecture, and SOI CMOS implementation,". vol. Ph.D.: North Carolina State University., 2004. T. M. Nguyen, "The behavior of a Costas loop in the presence of space telemetry signals," Communications, IEEE Transactions on, vol. 40, p. 190-198, 1992. M. Simon, "The False Lock Performance of Costas Loops with Hard-Limited In-Phase Channel," Communications, IEEE Transactions on [legacy, pre - 1988], vol. 26, p. 23- 34, 1978. B. Y. Chung, C. Chien, H. Samueli, and R. Jain, "Performance analysis of an all-digital BPSK direct-sequence spread-spectrum IF receiver architecture," Selected Areas in Communications, IEEE Journal on, vol. 11, p. 1096-1107, 1993. M. Simon, "Tracking Performance of Costas Loops with HardLimited In-Phase Channel," Communications, IEEE Transactions on [legacy, pre - 1988], vol. 26, p. 420- 432, 1978. M. Simon and W. Kai, "Alias Lock Behavior of Sampled-Data Costas Loops," Communications, IEEE Transactions on [legacy, pre - 1988], vol. 28, p. 1315- 1325, 1980. J. B. Berner, M. J. Layland, and P. W. Kinman, "Flexible loop filter design for spacecraft phase-locked receivers," Aerospace and Electronic Systems, IEEE Transactions on, vol. 37, p. 957-964, 2001. R. Jain, H. Samueli, P. T. Yang, C. Chien, G. G. Chen, L. K. Lau, B. Y. Chung, and E. G. Cohen, "Computer-aided design of a BPSK spread-spectrum chip set," Solid-State Circuits, IEEE Journal of, vol. 27, p. 44-58, 1992. Y. Linn, "Efficient loop filter design in FPGAs for Phase Lock Loops in high-datarate wireless receivers-theory and case study," in Wireless Telecommunications Symposium, 2007. WTS 2007, 2007, p. 1-8. W. Hurd and T. Anderson, "Digital Transition Tracking Symbol Synchronizer for LOW SNR Coded Systems," Communication Technology, IEEE Transactions on , vol. 2, p. 141 - 147 , 1970. D. R. Stephens, "Phase-Locked Loops for Wireless Communications Digital, Analog and Optical Implementations," , 2002. M. Simon, "On the Calculation of Squaring Loss in Costas Loops with Arbitrary Arm Filters," Communications, IEEE Transactions on [legacy, pre - 1988], vol. 26, p. 179- 184, 1978.

cos

[3]

p(t) is waveform of baseband signal. Substitute (17), (18) into (10), and then the relationships of timed error and error rate can be obtained. R ( ) + R (T ) (19) + co s 2 E rfc
PE ( ) =

[4]

[5]

2T

R (0 )

R ( ) R (T ) E rfc R (0 )

T e d 2 I 0 ( )

[6]

D. Results and discussion The emphasis of telemetry PSK demodulation is the error performance and the loop stability under low signalto-noise ratio. Fig. 7 compares testing result of bit error rate with different bit rate and different signal-to-noise ratio under 65536Hz carrier frequency.

[7]

[8]

[9]

[10]

[11]

[12]

Figure 7. Bit error performance of PSK demodulator

[13]

Fig. 7 illustrates that when Eb/N0 is greater than 1dB, the demodulator can stablely locked and the demodulation

194