JVC 2000 Basic DVC Models Technical Guide

VIDEO TECHNICAL GUIDE
DIGITAL VIDEO CAMERA
2000 Basic DVC Models
COPYRIGHT 2000 VICTOR COMPANY OF JAPAN, LTD.
No. 86056 September 2000
INDEX
SECTION 1 OUTLINE OF THE PROCUCTS
1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR.............1-1 1.1.1 Comparison table of DV models specification by products year .....................................1-1 1.1.2 Specification of the DVC models....................................................................................1-3
SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT

2.1 CIRCUIT OUTLINE ..............................................................................................................2-1 2.1.1 Basic block diagram.......................................................................................................2-1 2.2 CCD (ICX220AK/ICX221BK)................................................................................................2-2 2.2.2 CCD Image Sensor........................................................................................................2-3 2.2.3 Numbers of pixel for main models..................................................................................2-6 2.3 EXPLANATION OF CAMERA CIRCUIT ...............................................................................2-7 2.3.1 Present AW / AE control system ....................................................................................2-7 2.3.2 AF (Auto Focus) control .................................................................................................2-13 2.3.3 EIS (Electric Image Stabilizer) control ............................................................................2-14 2.4 CAMERA SYSREM IC'S FUNCTION ...................................................................................2-15 2.4.1 Camera DSP (IC4301: JCY0120) function .....................................................................2-15 2.5 EXPLANATION OF DECK CIRCUIT ....................................................................................2-22 2.5.1 Deck system overall structure ........................................................................................2-22 2.5.2 PB equalizer and ATF ....................................................................................................2-23 2.5.3 PLL operation ................................................................................................................2-24 2.5.4 Basic principle of Viterbi detection .................................................................................2-25 2.5.5 Audio recording mode....................................................................................................2-26 2.5.6 Audio signal processing .................................................................................................2-27 2.5.7 Clock system for audio data...........................................................................................2-28 2.5.8 Deck DSP IC function ....................................................................................................2-29 2.5.9 Audio AMP IC function...................................................................................................2-35 2.6 SYSCON CPU .....................................................................................................................2-38 2.6.1 Contents of SYSCON CPU processing ..........................................................................2-38 2.6.3 System composition.......................................................................................................2-39 2.6.4 SYSCON CPU block diagram ........................................................................................2-40 2.6.5 SYSCON CPU (IC1001: MN1021617HL) pin functions..................................................2-41 2.7 DECK CPU...........................................................................................................................2-44 2.7.1 Contents of DECK CPU processing ...............................................................................2-44 2.7.2 DECK system composition.............................................................................................2-44 2.7.3 Tracking Error information..............................................................................................2-45 2.7.4 1394 interface control ....................................................................................................2-46 2.7.5 JLIP Video Capture........................................................................................................2-46 2.7.6 DECK CPU block diagram .............................................................................................2-47 2.7.7 Deck CPU (IC1401: MN103004KRH) pin functions........................................................2-48
INDEX-1
SECTION 3 HEAD CLOG WARNING

3.1 HEAD CLOG WARNING OF DVC........................................................................................3-1 3.1.1 Structure of Sync Blocks and Error correction................................................................3-1 3.1.2 Error Rate of DVC..........................................................................................................3-3 3.1.3 Previous method of head clog detection ........................................................................3-4 3.1.4 New method of head clog detection ...............................................................................3-5
SECTION 4 DOCTOR SYSTEM

4.1 WHAT IS DOCTOR PROGRAM? .........................................................................................4-1 4.1.1 Matching of Doctor Program with Microcomputer Program ............................................4-1 4.1.2 Use of Doctor Program for Camcorder...........................................................................4-2 4.1.3 Revision of Service Support System Software for Doctor Program ................................4-2 4.1.4 Procedure to Rewrite Doctor Program ...........................................................................4-3 4.2 DOCTOR PROGRAM SYSTEM IN THE PRESENT CIRCUMSTANCES .............................4-5 4.2.1 ON/OFF address and Program address.........................................................................4-5 4.2.2 Writing function of EEPROM data ..................................................................................4-7 4.2.3 Upgrade of the service support system ..........................................................................4-7
INDEX-2
SECTION 1 OUTLINE OF THE PROCUCTS

1.1 COMPARSION TABLE OF DV MODELS SPECIFICATION BY PRODUCTS YEAR
1.1.1 Comparison table of DV models specification by products year (1/2)
Model Function Battery 1998 Fusion DV Model BN-V11 Ni-Cd (6V, 1100 mAh) BN-V12 Ni-Cd (6V, 1200 mAh) BN-V20 Ni-MH (6V, 2000 mAh) Continuous shooting time: when VF is used: BN-V12: 1hr.10min. BN-V20: 1hr.50min. 1999 Fusion DV Model BN-V207 Lithium-ion (7.2V, 700 mAh) BN-V214 Lithium-ion (7.2V, 1400 mAh) 2000 Fusion DV Model BN-V408 Lithium-ion (7.2V, 800 mAh) BN-V416 Lithium-ion (7.2V, 1600 mAh) BN-V428 Lithium-ion (7.2V, 2800 mAh) Continuous shooting time: when VF is used: BN-V408: 1hr.15min. BN-V416: 2hrs.30min. BN-V428: 4hrs.20min. BN-V856: 8hrs.40min. when LCD is used:
Continuous shooting time: when VF is used: BN-V207: 1hr. BN-V214: 2hrs.20min. BN-V856: 8hrs.30min.
when LCD is used: BN-V12: 1hr. BN-V20: 1hr.40min. Charging the battery Charging time: AA-V15 used 70 min. (BN-V11) 70 min. (BN-V12) 110 min. (BN-V20) Color LCD 0.55" 113k pixels B/W CRT Non 2.5" 480 234 = 112k pixels 3" 480 234 = 112k pixels Horizontal resolution: 240 lines Amorphous silicon transistor 766 596 = 460k pixels (*799 711 = 540k pixels) Effective aria 611 480 = 290k pixels (*601 576 = 350k pixels) Horizontal resolution Electric image stabilizer Sensitivity Lens specification Tele macro Zoom ratio 360 Lines Yes 10 lux (*12 lux) 50 IRE Level, Slow Shutter off F1.6 f = 3.9 to 62.4 mm Yes Optical zoom: 16 Digital zoom: 4/10 or 8/20 Max. zoom: 160 or 320 5 mode With frame Full Pin-up Pin-up 4-division Pin-up 9-division Yes 1/4" Total
when LCD is used: BN-V207: 50min. BN-V214: 1hr.55min. BN-V856: 7hrs. Charging time: AA-V20 used 90 min. (BN-V207) 180 min. (BN-V214) Color LCD 0.55" 113k pixels B/W LCD 0.24" 76k pixels 2.5" 480 234 = 112k pixels 3" 480 234 = 112k pixels 3.5" 480 234 = 112k pixels Horizontal resolution: 240 lines Amorphous silicon transistor 1/4" Total 998 677 = 680k pixels (*998 797 = 800k pixels) Effective aria 711 485 = 340k pixels (*702 575 = 400k pixels) 400 Lines 16 lux (*18 lux) 50 IRE Level, Slow Shutter off
Charging time: AA-V40 used 90 min. (BN-V408) 120 min. (BN-V416) 200 min. (BN-V428) Color LCD 0.44" 113k pixels B/W LCD 0.24" 76k pixels
Viewfinder LCD monitor
Image device
18 lux 50 IRE Level, Slow Shutter off F1.8 f = 3.6 to 36.0 mm Optical zoom: 10 Digital zoom: 4/10,25 or 45 Max. zoom: 100 ,250 or 450
Snapshot
Playback snapshot
Yes 4 RM-V711U
Yes 10 or 25 RM-V716U
Playback digital zoom Yes 10 RM-V712U
Table 1-1-1 Comparison table of DV models specification by products year (1/2)

1-1
Comparison table of DV models specification by products year (2/2)

Model Function 1998 Fusion DV Model 1999 Fusion DV Model 2000 Fusion DV Model
Slow motion Video auto light Audio Snapshot search Record end search Audio dubbing V.insert editing Time code
Headphone terminal AV output terminal S output terminal JLIP terminal PC terminal
Yes RM-V712U Yes 2ch(48kHz,16-bit) /4ch(32kHz,12-bit) No No No (Yes:PAL model,32kHz only,RCU only) No Yes
No RCA (Video Audio L/R) Yes Yes No
Yes (Frame Advance) RM-V711U (optional: GR-DVF11U) Yes ( /No) Yes (32kHz only,RCU only)
Yes (Frame Advance) RM-V716U Yes Yes (SP only)
3.5 mini
Yes (No: GR-DVF11U)
Yes (No: GR-DVF10,DVL100U,DVL305U, DVL307U) Yes (No: GR-DVF10,DVL100U,DVL305U, DVL307U) Yes (Output only: GR-DVL100EG/EK, DVL108EG/EK,DVL200EG/EK, DVL300EG/EK,DVL308EG/EK) Provided CD-ROM or optional HS-V14KIT (No: GR-DVF10,DVL100U,DVL305U, DVL307U) JLIP video capture Ver.3.1 JLIP video producer Ver.2.0 Picture Navigator (DSC model only)
Digital still image output terminal
No
Yes (No: GR-DVF11U)
DV terminal
No
Yes (EG/EK Model Output only)
JLIP related software
GV-CB3 JLIP video capture box (optional) JLIP video capture Ver.2.0 JLIP video producer Ver.1.13
Provided CD-ROM or optional HS-V4KIT (No: GR-DVF11U) JLIP video capture Ver.3.0 JLIP video producer Ver.1.16
JLIP ID number Remote control sensor Button battery (only for clock backup)
06 Yes Yes: CR-2025 type
Yes: CR-2032 type (built-in)
Table 1-1-1 Comparison table of DV models specification by products year (2/2)
1-2
1.1.2 Specification of the DVC models

SIGNAL FORMAT LDC MONI 3.0 INCH 3.0 INCH 3.0 INCH 2.5 INCH 2.5 INCH 2.5 INCH 3.0 INCH 3.0 INCH 3.0 INCH 3.5 INCH 3.5 INCH 2.5 INCH 3.0 INCH 3.5 INCH 2.5 INCH 3.5 INCH 2.5 INCH 2.5 INCH 2.5 INCH 2.5 INCH 3.0 INCH 3.5 INCH 3.5 INCH 3.5 INCH 3.5 INCH 2.5 INCH 2.5 INCH 2.5 INCH 2.5 INCH 2.5 INCH 3.5 INCH 3.5 INCH 2.5 INCH 2.5 INCH 3.5 INCH 2.5 INCH 2.5 INCH 3.5 INCH 2.5 INCH 3.5 INCH 2.5 INCH 3.0 INCH 3.0 INCH 3.5 INCH 3.5 INCH 3.5 INCH 3.0 INCH DV TERMINAL IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT OUT IN/OUT OUT IN/OUT OUT OUT IN/OUT OUT IN/OUT OUT IN/OUT OUT IN/OUT OUT OUT OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT DIGITAL STILL OUTPUT YES YES YES YES YES YES YES YES YES YES YES YES OPTION YES YES YES YES YES YES YES YES OPTION OPTION YES YES YES YES YES OPTION YES YES OPTION YES YES OPTION YES YES YES YES YES YES YES DIGITAL ZOOM 250 X 100 X 100 X 250 X 250 X 250 X 250 X 250 X 250 X 250 X 250 X 250 X 250 X 250 X 250 X 250 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 100 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 450 X 250 X
MODEL
CCD
VF
DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC DSC -
MMC MMC MMC MMC MMC MMC MMC MMC MMC -
GR-DVF10 NTSC 1/4" 680K B/W GR-DVA10 NTSC 1/4" 680K COLOR GR-DVA11/K NTSC 1/4" 680K COLOR GR-DVL100U NTSC 1/4" 680K B/W GR-DVL300U NTSC 1/4" 680K B/W GR-DVL305U NTSC 1/4" 680K COLOR GR-DVL307U NTSC 1/4" 680K B/W GR-DVL500U NTSC 1/4" 680K COLOR GR-DVL505U NTSC 1/4" 680K B/W GR-DVL507U NTSC 1/4" 680K B/W GR-DVL805U NTSC 1/4" 680K COLOR GR-DVL300UM NTSC 1/4" 680K B/W GR-DVL505UM NTSC 1/4" 680K B/W GR-DVL805UM NTSC 1/4" 680K COLOR GR-DVL300KR NTSC 1/4" 680K B/W GR-DVL805KR NTSC 1/4" 680K COLOR GR-DVL100EG PAL 1/4" 800K B/W GR-DVL107EG PAL 1/4" 800K B/W GR-DVL108EG PAL 1/4" 800K B/W GR-DVL109EG PAL 1/4" 800K B/W GR-DVL200EG PAL 1/4" 800K B/W GR-DVL300EG PAL 1/4" 800K COLOR GR-DVL307EG PAL 1/4" 800K COLOR GR-DVL308EG PAL 1/4" 800K COLOR GR-DVL309EG PAL 1/4" 800K COLOR GR-DVL100EK PAL 1/4" 800K B/W GR-DVL107EK PAL 1/4" 800K B/W GR-DVL108EK PAL 1/4" 800K B/W GR-DVL109EK PAL 1/4" 800K B/W GR-DVL200EK PAL 1/4" 800K B/W GR-DVL300EK PAL 1/4" 800K COLOR GR-DVL308EK PAL 1/4" 800K COLOR GR-DVL105A PAL 1/4" 800K B/W GR-DVL300A PAL 1/4" 800K B/W GR-DVL800A PAL 1/4" 800K COLOR GR-DVL105A-S PAL 1/4" 800K B/W GR-DVL300A-S PAL 1/4" 800K B/W GR-DVL800A-S PAL 1/4" 800K COLOR GR-DVL100EA PAL 1/4" 800K B/W GR-DVL300EA PAL 1/4" 800K COLOR GR-DVL300ED PAL 1/4" 800K B/W GR-DVL400ED PAL 1/4" 800K B/W GR-DVL500ED PAL 1/4" 800K COLOR GR-DVL600ED PAL 1/4" 800K B/W GR-DVL707ED PAL 1/4" 800K B/W GR-DVL800ED PAL 1/4" 800K COLOR CC9370 NTSC 1/4" 680K B/W OPTION: HS-V14KITE (CD-ROM and Cables)
Table 1-1-2 Specification of the DVC models
1-3
SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT

2.1 CIRCUIT OUTLINE
2.1.1 Basic block diagram
0 4 CCD
IC5001
OPTICAL BLOCK CCD
0 1 MAIN
IC4201
CCD_OUT
IC4302
FIELD MEMORY
TMY(8) TMC(4) CAM_AD(10) FMY(8) FMC(4) LCD_Y LCD_R-Y LCD_B-Y CLK27,CLK18,CLK13 XAVD, XAHD RD(16) RA(10)
0 2 MONITOR
IC7601 LCD DRIVER
R G B
MONI LCD
CDS/AGC A/D
DATA_OUT
IC3002
16M DRAM
DATA_OUT
IC7604 EEP ROM IC7603 IC7101 LCD DRIVER

*only for B/W VF model
IC4301
CAMERA_DSP
DYO(4),DCO(4) DYI(4),DCI(4) ATF_GAIN, M_VCOCTL PBVCOCTL, FSPLLCTL
IC3001
DECK_DSP
PD(4) PBDATA HSE ADDT(16) DODAT AIDAT
SW
R G B
VF LCD
IC5501
SUB IRIS PWM H1, H2, RG V1,V2,V3,V4 DATA_OUT VF_R, VF_G, VF_B, VBLK VC1, BLK1 H_GAIN,H_OFFSET MY(8),MC(4) DV_C DV_Y
RECC_ADJ
BUS(16)
TG V.DRV
VF LCD
54MHz X5501
SP
IC4851
FOCUS (4)
0 6 JACK
ZOOM (4)
FOCUS DRIVER & ZOOM DRIVER
DATA_OUT
IC1003
E 2P R O M X1002
IC1002
ON SCREEN
OSD_DATA ADDT(16) PD(4)
IC3101
1394PHY
TPA+,TPATPB+,TPB-
J502
DV
IC1004
RTC
AD(16)
IC4802-IC4805
DRIVE+,-
32kHz
IRIS PWM H_GAIN,H_OFFSET DATA_OUT IRIS_O/C
IRIS DRIVER & HALL AMP
IC3201
S_DT_OUT S_DT_IN
IC1001
SYSCON CPU
EDIT_CTL RXD TXD
S_DT_OUT S_DT_IN M32_DTOUT M32_DTIN
IC3301
PBO PB_ENV
IC1401
DECK CPU
MDA_IN
DVEQ
ATFO
DVANA
0 7 REAR
J552 PC
IF_TX
GND TX RX
IC1014 IC1302
PC_TX IF_RX PC_RX
IF_RX ADDT(16) SRV_TX TXD RXD ANA_IO DATA_OUT ANA_IO ATF_GAIN, M_VCOCTL, PBVCOCTL, FSPLLCTL DODAT AIDAT
J553 JLIP
EDIT RX TX GND
JLIP_RX A_OUT / L JLIP_TX A_OUT / R
IC2201
AUDIO AMP
SPK+,SPK-
IC3501
PB_ENV HSE
M32_DTOUT
MY(8),MC(4)
0 6 JACK
J501
AV OUT A_OUT / R AV_DET A_OUT / L TXD RXD
M32_DTIN
1 0 DSC
IC8003
32D(16) 32A(25) 32A(19)
INT_MIC / R
INT_MIC / L
JLIP_L
REC AMP & PB AMP
1F 1S 2F 2S
VIDEO HEAD
RECC_ADJ C_COIL_U C_COIL_V C_COIL_W D_COIL_U D_COIL_V D_COIL_W
IC8001
DSC_IF
16Mb FLASH
IC1601
DRUM_REF CAP_REF DRUM_PG DRUM_FG CAP_FG
CAPSTAN MOTOR
J503
S_OUT
V_OUT DV_Y Y_OUT C_OUT
IC8002
VIDEO OUT
DV_C
MDA
DRUM MOTOR
M32_R/D CPU
MIC UNIT
LOAD_FWD LOAD_REV MDA_IN
M
0 5 JUNCTION
M14D2 Series
LOADING MOTOR
Fig. 2-1-1 Basic block diagram

2-1
2.2 CCD (ICX220AK/ICX221BK)

This IC functions as an interline CCD (Charge Coupled Device = one of solid-state pickup devices). Since this CCD conforms to the SD mode of the DV standard, it has an optimum number of vertical pixels for the MPEG2 main level and it realizes a horizontal resolution of 450 TV lines. As same as general CCD's currently in use, this CCD is capable of camera shaking correction and electronic panning and tilting owing to the extension area of 33 percent extra in both the vertical and horizontal directions. Moreover, this CCD provides high quality wide picture whose aspect ratio is exactly 16:9 without vertical interpolation. High sensitivity and low dark current are realized thanks to adoption of the Super HAD CCD technology with the color filters of yellow, cyan, magenta and complementary green mosaic filters. This CCD has an electronic shutter function that is able to vary charge storage time by the field period read system. Frame period read system is realized by joint use of the newly developed TG IC.
ELEMENT STRUCTURE Optical size Total pixels Effective pixels 4:3 NTSC 16:9 18MHZ 16:9 5fsc OB Board material 1/4 inch size format NTSC: 998 (H) 677 (V) approx. 680,000 pixels, PAL: 998797 approx. 800,000 pixels NTSC: 962 (H) 654 (V) approx. 630,000 pixels, PAL: 962774 approx. 740,000 pixels NTSC: 711 (H) 485 (V) approx. 340,000 pixels, PAL: 702575 approx. 400,000 pixels NTSC: 948 (H) 485 (V) approx. 460,000 pixels, PAL: 936575 approx. 540,000 pixels NTSC: 942 (H) 485 (V) approx. 460,000 pixels, PAL: 922575 approx. 530,000 pixels H direction: Front 4 pixels, Rear 32 pixels V direction: Front 11pixels, Rear 12 pixels Silicon
TEST GND VDD V1 V2 V3 V4
1
Ye G Ye Mg Ye G
Cy Mg Vertical-Register Cy G Cy Mg
Ye G Ye Mg Ye G
Cy Mg Cy G Cy Mg
Horizontal-Register
8 9 10 11 12 13 14
Photo Sensor
RG
GND
H1
VOUT
H2
Fig. 2-2-1 CCD block diagram
Interline type CCD image sensor
Table 2-2-1 CCD functions

Pin No. Label 1 V 4 2 3 4 5 6 7 V 3 V 2 V 1 GND TEST VDD In/Out Description In Vertical register transfer clock In In In Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Ground Open Power supply Pin No. Label 8 VOUT 9 10 11 12 13 14 GND In/Out Description Out Video signal output In In In In Ground Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Substrate clock Protect transistor bias
RG
H 1 H 2
SUB
VL
Table 2-2-2 CCD pin function
2-2
SUB
VL
2.2.2 CCD Image Sensor Main difference in CCD adopted with DVC and VHS-C.
960H-type 1/4" C C D (w/ EIS area) for DVC
(GR-DVX7, GR-DVF31/DVL40, GR-DVL300 etc.) N T S C : effective 630,000 (I m a g e 3 4 0,000) pixels
33% EIS Area Picture Area 654(V) 485(V) 4.15 m (Pixel)
PAL: effective 740,000 (Im a g e 4 0 0,000) pixels

33% EIS Area Picture Area 575(V) 774(V) 3.50 m 4.65 m 4.7 m 7.3 m (Pixel) 4.85 m (Pixel)
711(H) 962(H) 13.5MHz 18MHz 3.80 m
702(H) 962(H) 13.5MHz 18MHz 3.85 m
510H-type/760H-type 1/4" CCD for VHS-C

N T S C : effective250,000 pixels PAL: effective 290,000 pixels
492(V)
510(H) 9.54545MHz
5.55 m
(Pixel)
582(V)
(Pixel)
7.15 m
500(H) 9.45833MHz
PAL (760H-type): effective 440,000 pixels
752(H) 14.1875MHz
DVC NTSC PAL 18MHz: 1144fH Picture area:13.5MHz: 858fH 13.5MHz = 18MHz 3/4 NTSC 9.54545MHz 910fH 2/3 910fH = 4 fsc
VHS-C PAL 9.45833MHz 908fH 2/3 PAL (760H) 14.1875MHz 908fH
Horizontal drive frequency
13.5MHz: DVC format Y signal sampling frequency fH = 15.734264KHz (PAL: 15.625KHz): Horizontal sync frequency fSC = 3.579545MHz (PAL: 4.433618MHz): Color sub-carrier frequency
Fig. 2-2-2
Pixel number and pixel size of various CCD

2-3
582(V)
1. Feature of CCD for this model This CCD adopts the drive frequency and the number of pixels conforming to the DVC format. The horizontal drive frequency is 18MHz based on 13.5MHz that is Y signal sampling frequency of the DVC format. And the number of pixels secures the horizontal resolution of 400 lines that conforms to the high resolution DVC format. Moreover, to keep resolution even if EIS is switched on, the CCD having EIS (Electric Image Stabilizer) area (approx. 33% in area) is adopted. Adoption of the usual 1/4-type CCD realizes miniaturization of the lens unit with keep the zoom ratio of 10 times, and it also realizes miniaturization of whole body. On the other hand, a pixel size gets smaller as the evil effect of miniaturization and large numbers of pixel. It becomes unfavorable in the point of CCD sensitivity and dynamic range. For such reason, the minimum object illumination is determined as 18 Lux EIA standard. 2. Improvement of the CCD for DVC It is elaborated the following idea to make up for the decline of the sensitivity of CCD at all. 1) Optimization of the on-chip microlens Loss of incident light is minimized by reduction of ineffective area between microlenses on the pixels.
On-chip microlens Ineffective Light
On-chip microlens Ineffective Light
Effective Photo shielding AI Transfer section Transfer section
Effective Photo shielding AI Transfer Sensor Transfer section section
Fig. 2-2-3 Structural drawing of CCD image sensor
2-4
2) Construction of internal lens Since the internal lens is constructed between the color filter and gobo, the light condensation efficiency is improved even for inclined incident light.
On-chip microlens Color filter Internal lens Gobo Gobo
On-chip microlens Color filter
Poly Si Sensor V. Register Sensor
Poly Si V. Register
Fig. 2-2-4 Structural drawing of internal lens
2-5
2.2.3 Numbers of pixel for main models

Models DVC NTSC GR-DV1 GR-DVM1 GR-DVX GR-DVL /DVL9000U GR-DVL7 /DVL9600U Optical size 1/3 Total pixels approx. 570,000 908H 616V Effective pixels (EIS) approx. 530,000 858H 614V practical pixels approx. 350,000 704H 499V
1/3 Progressive scan 1/4
approx. 380,000 758H 504V
approx. 420,000 724H 582V
approx. 360,000 724H 494V
GR-DVY GR-DVM5U /DV3U GR-DVF10U /20U GR-DVX7 GR-DVM70U /50U GR-DVA1 /F1 GR-DVF11 /21 /31U GR-DVA10 /F10 /A11 GR-DVL100 /200 /300U GR-DVL700 GR-DVL9800U
approx. 460,000 766H 596V
approx. 290,000 611H 480V
1/4
approx. 680,000 998H 677V
approx. 630,000 962H 654V
approx. 340,000 711H 485V
1/3 Progressive scan
approx. 680,000 1002H 662V
approx. 630,000 962H 654V
approx. 340,000 720H 480V DSC XGA: 630,000 962H 654V approx. 420,000 704H 594V
DVC PAL
GR-DV1E GR-DVM1E GR-DVXE GR-DVL9000E GR-DVL9500E /9600E
1/3
approx. 670,000 908H 728V
approx. 620,000 858H 726V
1/3 Progressive scan 1/4
approx. 450,000 758H 592V
approx. 500,000 724H 697V approx. 740,000 962H 774V
approx. 420,000 724H 582V
GR-DVM5E /DV3E GR-DVF1E /DVF10E GR-DVX4E /DVX7E GR-DVL20 /30 /40E GR-DVL100 /200 /300E GR-DVL9200E GR-DVL9700E /9800E
1/4
1/3 Progressive scan
approx. 800,000 1002H 782V
approx. 740,000 962H 774V
approx. 420,000 720H 576V DSC XGA: 740,000 962H 774V
VHS-C PAL
GR-SXM46 /SX41E GR-SXM26 /SX21E GR-FX11 /FXM16E GR-FX102 /FXM106S
1/4
approx. 470,000 795H 596V approx. 320,000 537H 597V approx. 270,000 537H 505V
approx. 440,000 752H 582V approx. 290,000 500H 582V approx. 250,000 510H 492V
1/4
VHS-C NTSC
GR-AXM220U GR-SXM920U
1/4
Table 2-2-3 Numbers of pixel for main models

2-6
2.3 EXPLANATION OF CAMERA CIRCUIT

2.3.1 Present AW / AE control system The signal-processing block of the present camera system is composed as shown below (Fig. 2-3-1)
PROCESS MATRIX ENCODER Y GCA R AGC CCD A/D COLOR SEPARATION
LPF
G GCA B
TG DRIVE
3 4
CAMERA CPU
2
IRIS DRIVE
IR SENSOR
1 Iris control 2 Shutter speed setting 3 Analog amp gain (AGC gain) 4 WB setting (RED gain, BLUE gain) 5 Parameter for picture compensation (color reproducibility, S/N ratio) Fig. 2-3-1 Camera block configuration
2-7
1. AE (Auto Exposure) control The luminance level of camera output picture is controlled to always be proper exposure regardless of the brightness and illumination of the object. 1) AE input information Average of luminance level divided a frame picture into 48 blocks passed through the LPF. The area ratio of the sections having luminance components higher than a certain level to the whole sections.
AE control
Weighting of sectioned data
Caluculation of evaluation value
Target > Evaluation?
AGC gain down Slow shutter OFF Iris close
Iris open AGC gain up Slow shutter ON
RET
Fig. 2-3-2 AE control flow chart 2) Weighting of data on sections Though the respective data on 48 sections are weighted, the basic setting is to weight the center part high.
Low
High
Low
Low
High
Low
Fig. 2-3-3 Weighting of data on sections
2-8
3) AE control and output luminance signal level Gain-up mode: AUTO (OFF and AGC modes are the same as the VHS-C camcorder)
LUMINANCE 100 IRE
(2)
50 IRE
0 IRE 5000 lux BRIGHT IRIS APERTURE Open 300 lux 40-50 lux ILLUMINATION 10 lux DARK
(6)
Close
AGC GAIN MAX
(1) (4)
MIN
(3)
SHUTTER SPEED 1/30
1/60
1/240
AUTO LIGHT ON
(5)
OFF
Fig. 2-3-4 AE control and output luminance signal level
2-9
(1) When the intensity of illumination is high and iris aperture is stopped down, the iris is opened for compensating drop of the signal level by changing the shutter speed to high (1/250 sec). (2) Since raising the AGC gain deteriorates the S/N ratio, the E-E level is slightly lowered in the exposure compensation by controlling the AGC as compared with the iris control mode. (3) As the intensity of illumination becomes low and AGC gain rises to maximum, the camera enters the slow shutter mode (1/30 sec). (4) When the camera enters the slow shutter mode, the signal level rises by 6 dB and the AGC gain drops in inverse proportion to the signal level. (5) The auto-light is turned on when the illumination turns down a little more after the camera entered the slow shutter mode and AGC gain rose to the maximum. There is a hysteresis to prevent hunting as the auto-light is switched on/off. (6) The intensity of illumination shown in the figure is just an example and it varies depending on the object, angle of view, etc.
2-10
2. AW (Auto White balance) control AW control compensates the Red component gain and Blue component gain shown in the camera block diagram to keep the white balance in the camera picture under every kind of light source. Basic input data for AW control are three of the following. (1) R, G, B levels of sections divided a picture into 48 sections. (2) Data on existence/absence of infrared rays in the light source. This data is used for judging the sort of the light source. (3) Illumination judged with the exposure compensation parameters (iris/ AGC gain/ shutter speed). The white balance is controlled by the following setting referring to the R, G, B data on the section that is judged as a white (uncolored) part of the picture according to the three kinds of data mentioned above. Red component gain = Green level / Red level Blue component gain = Green level / Blue level Besides the white balance control, balance among color phases is controlled by the parameter control in the color signal processing from RGB to C signal depending on the light source.
1) Light source judging process

IR DC component FLICKER AC component BRIGHT (Over 4000 Lx) LIGHT SOURCE
Yes Yes Yes Yes No No No No
Yes Yes No No Yes Yes No No
Yes No Yes No Yes No Yes No
HAROGEN OUT DOOR OUT DOOR FL LIGHT FL LIGHT FL LIGHT FL LIGHT
: OUT DOOR or HAROGEN (not FL LIGHT) Table 2-3-1 Light source judging process
2-11
2) AWB control algorithm

AWB control
Light source judgment (Gain limiter setting)
The upper and lower limits of each gain are set according to the ratio between R and B components and judgment of the light source by the infrared sensor.
Sunlight?
YES
NO Gain calculation from white block data (Calculation value = Target gain) Gain setting (adjustment) for the sunlight (Adjustment value = Target value)
Optimum time constant setting for gain control
Setting of the control time constant to avoid unnatural color variation.
Is the WB deviating to blue? YES
NO
R-gain up / B-gain down
Is the WB deviating to red? YES
NO
R-gain down / B-gain up
RET
Fig. 2-3-5 AW control flow chart The light source of the natural light (sunlight), halogen lamp (indoor) or fluorescent lamp is judged according to data of the infrared sensor and data on the illumination. Since the gain to be compensated by the white balance control greatly varies depending on the device used (CCD, IR cut filter, lens, etc.) and parameter for color separation, settings of limiter, control time constant and color reproducing parameters differ from model to model.
2-12
2.3.2 AF (Auto Focus) control 1. Auto Focus operation during slow shutter mode Though the basic Auto Focus operation is the same as usual, the interval of Auto Focus operation varies conforming to the timing of the picture data renewal when the camera is in the slow shutter mode. For example, in case the Gain-up mode is set to Auto, the shutter speed is changed to 1/30(2V) according to the illumination of the object. Therefore, the Auto Focus operation also works every 2V. The Auto focus operation works every 4V in Slow-4X mode and every 10V in Slow-10X in the same way.
1/30 1/60 VD
Data Renewal/processing 2V
Focus operation
Fig. 2-3-6 AF operation timing in slow shutter mode 2. Improvement of the Low-contrast performance To improve the AF performance in the low contrast subject (such as the man's face), a route that has low stage filter (HPF1) is added newly. The low contrast subject contains the frequency element that is not comparatively high.
BPF HPF2 Rectifier Peak Addition Peak Addition Peak Addition AFE HPE
HPF1
Rectifier
HPF1
HPF2
Rectifier
HPF2
Previous
HPF1 BPF HPF2
Rectifier
Peak Addition Peak Addition Peak Addition Peak Addition
AFE1 HPE1 AFE2 HPE2
Rectifier
HPF1
Rectifier
HPF1
HPF2
Rectifier
HPF2
HPF1: 500KHz HPF2: 1.7MHz
New
Fig. 2-3-7 Addition of AFE low stage filter
2-13
2.3.3 EIS (Electric Image Stabilizer) control The accurate compensation without picture quality deterioration is possible by using CCD with expansion area and correcting it two times.
VRAM
(3)
CCD
(1)
CDS / AGC / ADC
IWD
18 MHz
(2)
13.5 MHz
FMC DSP
(4)
TG/ V_DRIVER
CPU
Vector
Fig. 2-3-8 EIS system block diagram

(1) Cutting out at TG
962 800 654(*774) 245(*292) 2 lines mixing transfer 720 240(*288)
(2) Cutting out at IWD
(3) Cutting out at Field Memory
(4) Camera output
Fig. 2-3-9 EIS operation
2-14
2.4 CAMERA SYSTEM IC'S FUNCTION

2.4.1 Camera DSP (IC4301: JCY0120) function 1. Camera DSP (IC4301: JCY0120) internal block diagram
MCLK RAD FMWR WAD RAE1 WAE1 RAE2 WAE2 IE1 FMRE1 FMWE1 I E 2 F M R E 2 F M W E 2 TMY [7:0] FMY [7:0] O M T TMC [3:0] FMC [3:0]
FLDDSC CLKDSC H D D S C DSYO [7:0] DSYI [7:0] V D D S C DSCO [7:0] DSCI [7:0]
AYO [3:0] ACO [3:0]
INHA INVA ANACNT
CLKENC1 CLKYCA ADIN [9:0] CLKYCA ADKZ ADYC DSC interface CLK13 CLK13 CLK13X CLK27 CLK13 YO
KIZU
White noise compensation
DSC I/F
EIS/FMC
VRAM Contol Vector Detect
ANA I/F
Analog input interface
YDAC
D/A Converter
YOUT
CLKENC2 CO SLDS LHFO CLKYCA CLKYCA CLK14 IRSI DSSL SLFM FMSL CLK13 CLKENC1 SLEN SLCV CLKENC2
CDAC
D/A Converter
COUT
Y/C
ID Y/C signal process YCIN
IWD
Frequency converter
SELECT
Test signal generator / Wipe / OSD mix Hadamard NR / Mix / Signal select DVSL SLDV VBLK0 BLK10 BLK20 OSY_V OSY_1 OSR_V OSY_2 OSB_V CLK13 CLK13X VBDAT
ENC
NTSC/PAL Color Encoder CLK13
HDTG VDTG CLKYCA PWM BEND AFBEND CLKYCA CLK27 CLK13
Y2DAC
CLK13 Y2O RYO RYO CLK13 D/A Converter
Y2OUT
CLK13
AUTO
Auto operation process
SSG1
SSG for TG/YCA
DVC I/F
DVC Interface
OSD I/F
OSD Interface
VBGEN
VBID/WSS Generator VBSTART
CVF
Interface for Color Viewfer
RYDAC
D/A Converter
RYOUT
VDMDA HDCPU VDCPU FRP FLDCPU
HDYCA VDYCA FLDYCA CLKYCA CLK13 CLK13X CLKENC1 CLKENC2
OUTH13 OUTV13 CLK13
HDANA13 VDANA13
CLK18I CLK13I CLK27I CLK45
CLK13
CLKGEN
Clock generate
SSG2
Main SSG
HDFMC VDFMC FLDFMC
ESSG
SSG for Encoder
CBLK CSYNC BF LSW HRST4T VRST4T
CLK13
BYDAC
D/A Converter
BYOUT
BUS [15:0] RE DSTB LWE HWE CS RWSEL ALE USEL0 USEL1 CLR TVSEL0 H D A N A O U T H DYI [3:0] INH V D A N A O U T V DCI [3:0] INV CSYNC1 DYO [3:0] DCO [3:0]
CPU I/F
CPU Interface
CONTROL SINGNAL DBI[15:0]
CLK13
EDAC
12ch EVR DAC
KASHA
Shutter sound occurrence
KO
KDAC
D/A Converter
KOUT
VC1 VR VBLK H D O S D EOUT1 V C 2 VG BLK1 V D O S D E O U T 2 VB BLK2 C L K O S D E O U T 3 EOUT4
EOUT5 EOUT6 EOUT7 EOUT8
EOUT9 CSYNC EOUT10 EOUT11 EOUT12
Fig. 2-4-1 Camera DSP (IC4301: JCY0120) internal block diagram
2-15
2. Camera DSP (IC4301: JCY0120) pin functions (1/6)

Pin No. 100 158 20 1 251 255 191 117 36 33 113 186 32 35 34 187 114 188 115 138 256 64 69 137 208 270 61 136 207 60 59 140 210 272 142 139 209 63 62 211 141 212 143 70 271 146 215 145 Label VDMDA PWM CLK45 VSS VDDE CSYNCI HDANA VDANA ANACNT AY00 AY01 AY02 AY03 AC00 AC01 AC02 AC03 INHA INVA ADDVSS VDDE VSS ADDVDDE DSYO0 DSYO1 DSYO2 DSYO3 DSYO4 DSYO5 DSYO6 DSYO7 DSCO0 DSCO1 DSCO2 DSCO3 DSCO4 DSCO5 DSCO6 DSCO7 CLKDSC HDDSC VDDSC FLDDSC ADDVSS VDDE DSYI0 DSYI1 DSYI2 In/Out Out Out Out Description Vertical reference signal output for MDA PWM output 4.5MHz output Ground for Digital Power supply for Digital (I/O)
Not used
Ground for add Digital Power supply for Digital (I/O) Ground for Digital Power supply for add Digital (I/O)
Not used
Out Out Out In
Clock for DSC Horizontal reference pulse output for DSC Vertical reference pulse output for DSC Ground for add Digital Power supply for Digital (I/O) Digital luminance signal input for DSC
Table 2-4-1 Camera DSP (IC4301: JCY0120) pin functions (1/6)
2-16
Camera DSP (IC4301: JCY0120) pin functions (2/6)

Pin No. 65 276 214 144 213 217 148 68 278 216 67 147 66 30 112 185 273 275 106 178 245 179 105 31 252 21 22 125 184 250 248 249 26 28 111 29 25 110 27 182 24 247 109 23 107 181 183 108 Label DSYI3 DSYI4 DSYI5 DSYI6 DSYI7 DSCI0 DSCI1 DSCI2 DSCI3 DSCI4 DSCI5 DSCI6 DSCI7 TVSEL CPUSEL0 CPUSEL1 VDDI ADDVDDE TCK TMS TRST TDIN TDOUT ADDVSS VDDI ADDVSS VSS DACTEST AVDDA DVDDM AVDDV2 AVSSA AVSSV2 VREFHK VREFLK K_OUT IREFVF VREFVF B-Y_OUT R-Y_OUT IREFC VREFC C_OUT IREFY VREFY Y_OUT Y2_OUT AVSSV1 In/Out Description
In
Digital luminance signal input for DSC
In
Digital color difference signal input for DSC
In In In In In In In Out In/Out In Out Out In/Out In Out In/Out In Out Out -
Not used TV system select (L: NTSC, H: PAL) CPU select (L: n, H: M) CPU select 1 (L: MN2_H: MN3) Power supply for Digital (I/O, internal) Power supply for add Digital (I/O) Not used Test terminal (for JTAG with pull-up) Not used Ground for add Digital Power supply for Digital (I/O, internal) Ground for add Digital Ground for Digital Test terminal for DAC Power supply for Analog sound Power supply for DAC Power supply Analog video Ground for Analog sound Ground for Analog video Reference voltage input, top side (for shutter sound) Reference voltage input, bottom side (for shutter sound) Shutter sound output Reference register terminal for current adjustment, (for VF signal) Reference voltage input terminal for adjustment, (for VF signal) BY signal output for VF RY signal output for VF Reference register terminal for current adjustment,(for chromatic signal) Reference voltage input terminal for adjustment,(for chromatic signal) Modulation color signal output Reference register terminal for current adjustment,(for luminance signal) Reference voltage input terminal for adjustment,(for luminance signal) Luminance signal output Luminance signal output for VF Ground for Analog video
2-17

Pin No. 246 180 222 79 75 78 223 220 221 74 75 279 71 150 218 72 149 280 219 73 281 151 152 282 77 153 283 154 162 126 167 284 286 269 266 254 263 192 177 101 102 176 175 242 103 15 274 267 Label AVDDV1 NC AVSSE3 VREFL3 VREFH3 AVDDE3 DVDDM AVSSE2 VREFL2 VREFH2 AVDDE2 NC AVSSE1 VREFL1 VREFH1 AVDDE1 EOUT1 EOUT2 EOUT3 EOUT4 EOUT5 EOUT6 EOUT7 EOUT8 EOUT9 EOUT10 EOUT11 EOUT12 ADDVDDE ADDVSS ADDVDDE VSS VDDE VSS VDDE VSS ADDVDDE ADDVSS ADDVDDE NAND2_O NAND2_B NAND2_A NAND1_O NAND1_B NAND1_A ADDVDDE VSS VDDI In/Out In In In In In Out Out Out Out Out Out Out Out Out Out Out Out Out In In Out In In Description Power supply for Analog video Not used Ground for EVR Reference voltage input for bottom side Power supply for EVR Power supply for EVR Power supply for DAC Ground for EVR Reference voltage input for bottom side Reference voltage input for top side Power supply for EVR Not used Ground for EVR Reference voltage input for bottom side Reference voltage input for top side Power supply for EVR EVR output 1 EVR output 2 EVR output 3 EVR output 4 EVR output 5 EVR output 6 EVR output 7 EVR output 8 EVR output 9 EVR output 10 EVR output 11 EVR output 12 Power supply for add Digital (I/O) Ground for add Digital Power supply for add Digital (I/O) Ground for Digital Power supply for Digital (I/O) Ground for Digital Power supply for Digital (I/O) Ground for Digital Power supply for add Digital (I/O) Ground for add Digital Power supply for add Digital (I/O) NAND 2 output NAND 2 input B NAND 2 input A NAND 1 output NAND 1 input B NAND 1 input A Power supply for add Digital (I/O) Ground for Digital Power supply for Digital (I/O, internal)
2-18

Pin No. 99 238 174 18 19 240 239 243 16 17 97 98 173 172 13 14 169 12 277 244 95 170 94 11 171 96 241 203 49 130 48 200 201 50 129 265 258 259 206 51 131 202 52 53 134 205 56 55 Label CSYNC ADDVSS DYO0 DYO1 DYO2 DYO3 VSS VDDI DCO0 DCO1 DCO2 DCO3 INH INV DYI0 DYI1 DYI2 DYI3 VDDI VSS DCI0 DCI1 DCI2 DCI3 OUTH OUTV VDDE MCLK IE1 FMWE1 WAD RAD FMRE1 RAE1 FMWR WAE1 VDDI VSS ADDVDDE IE2 FMWE2 FMRE2 RAE2 WAE2 TMY0 TMY1 TMY2 TMY3 In/Out Out Out Description Internal composite sync. Signal output Ground for add Digital Digital luminance signal output for DVC
Out
Ground for Digital Power supply for Digital (I/O, internal) Digital colon difference signal output for DVC
Out Out In
Horizontal reference pulse output for DVC REC Vertical reference pulse output for DVC REC Digital luminance signal input for DVC
In
Power supply for Digital (I/O, internal) Ground for Digital Digital colon difference signal input for DVC
In In Out Out Out Out Out Out Out Out Out -
Horizontal reference pulse input for DVC PB Vertical reference pulse input for DVC PB Power supply for Digital (I/O) Clock output for field memory Input enable Memory write enable Write address Read address Memory read enable Read address enable Memory write transfer Write address enable Power supply for Digital (I/O, internal) Ground for Digital Power supply for add Digital (I/O)
Not used
Out
Digital luminance signal output for field memory

2-19

Pin No. 204 133 54 132 135 58 268 57 47 128 261 197 260 196 195 194 193 257 199 46 127 198 262 236 237 43 190 44 42 45 123 189 116 253 86 264 118 37 119 38 120 39 121 40 122 41 232 7 Label TMY4 TMY5 TMY6 TMY7 TMC0 TMC1 TMC2 TMC3 ADDVDDE ADDVSS FMY0 FMY1 FMY2 FMY3 FMY4 FMY5 FMY6 FMY7 FMC0 FMC1 FMC2 FMC3 VDDI VDDE VDDI VSS ADDVDDE CLK27 CLK18 CLK13 ID VDTG HDTG LHFO ADDVDDE VSS ADIN9 ADIN8 ADIN7 ADIN6 ADIN5 ADIN4 ADIN3 ADIN2 ADIN1 ADIN0 VDDI ADDVSS In/Out Description
Out
Digital luminance signal output for field memory
Out -
Digital colon difference signal output for field memory Power supply for add Digital (I/O) Ground for add Digital
In
Digital luminance signal intput form field memory
In In In Out Out Out -
Digital colon difference signal input form field memory Power supply for Digital (I/O, internal) Power supply for Digital (I/O) Power supply for Digital (I/O, internal) Ground for Digital Power supply for add Digital (I/O) Clock input Line discriminate pulse input Vertical reference pulse output for TG Horizontal reference pulse output for TG LHF signal output Power supply for add Digital (I/O) Ground for Digital
In
Digital signal input from A/D
Power supply for Digital (I/O, internal) Ground for add Digital
2-20

Pin No. 6 9 235 8 168 230 87 163 231 2 88 164 89 3 90 4 165 233 5 91 166 234 124 160 228 159 227 85 161 287 229 92 104 10 93 288 157 84 226 225 156 81 224 155 82 285 80 83 Label ADDVDDE RE HWE LWE ALE BUS15 BUS14 BUS13 BUS12 BUS11 BUS10 BUS9 BUS8 BUS7 BUS6 BUS5 BUS4 BUS3 BUS2 BUS1 BUS0 VSS CLR VDCPU HDCPU FRP OMT AFBEND FLDCPU BEND VSS DSTB VPD CS RWSEL VDDI CLKOSD HDOSD VDOSD BLK1 BLK2 VC1 VC2 VR VG VB VBLK ADDVSS In/Out In In In In Description Power supply for add Digital (I/O) Read enable High address write enable Low address write enable Address latch enable
In/Out
CPU bus I/O
In Out Out Out Out Out Out Out In In In In Out Out Out In In In In In In In In -
Ground for Digital Clear input Vertical reference pulse output for CPU Horizontal reference pulse output for CPU Frame detect pulse output EIS read-out data enable flag output CPU interrupt pulse output Field discriminate pulse output for CPU Block average data interrupt pulse output Ground for Digital Data strobe Test pin for pull-up Chip select Read write select Power supply for Digital (I/O, internal) Clock output for OSD Horizontal reference signal for OSD Vertical reference signal for OSD Blank signal 1 Blank signal 2 Character signal 1 Character signal 2 Character signal 3R Character signal 3G Character signal 3B Blank signal 3 Ground for add Digital
2-21
2.5 EXPLANATION OF DECK CIRCUIT

2.5.1 Deck system overall structure The DVC deck system has such the IC construction as shown in Fig. 2-5-1. The DV-MAIN IC (IC3001) serves as the center IC of the deck system IC construction, and this system has been incorporated in the models of the GR-DVX7 and after. In recording, the deck system processes image data input from the camera section by shuffling and DV compression and adds parity codes to it as well as the audio data and sub code data input to the deck system, and saves those data as sync blocks. The formatter inside the DV-MAIN IC serves as the 24-25 converter for generating ATF pilot signal and the data column converter for adapting the data to the digital magnetic recording/playback system (scrambled interleaved NRZI), and it outputs the processed data to the PRE/REC IC as recording data. In playback the playback signal transmitted from the PRE/REC IC is input to the DV-ANA (IC3301) and DV-EQ (IC3201) for waveform equalization, and then supplied to the DV-MAIN IC as playback data. The DV-EQ IC takes charge of various functions such as playback clock generation, VITERBI decoding, ATF detection, and so on. For details of its functions, refer to the next page. The DV-MAIN IC processes playback data by the reverse procedure of recording and it transmits playback data to the camera section and audio section. Since the DV-MAIN IC has the 1394 LINK function, it inputs and outputs DV data from/to the camera through the 1394 PHY IC (IC3101). The 16-Mbits DRAM (IC3002) is used as the memory for shuffling/de-shuffling and ECC error correction.
IC3001 DV_MAIN
Shuffling / De-shuffling Compress / De-compress ECC Encode / Decode Formatter / Deformatter 1394 LINK
CAMERA
IC3201 DV_EQ
Auto EQ Viterbi PLL det
IC3301 DV_ANA
AGC PB VCO
IC3501 PRE/REC
HEAD
AUDIO
IC3002
16M DRAM
IC3101
1394 PHY
DV IN/OUT
Fig. 2-5-1 DVC deck IC structure
2-22
2.5.2 PB equalizer and ATF

To: DV MAIN PB_DATA
IC3201
VITERBI
DV_EQ
1+D AUTO EQ AD1 PLL DET PWM
AINAD1 PBO
IC3301
DV_ANA
AGC LPF
PB_ENV
PB_CLK
2CH DAC
VOA VOB
PLLE REFV PLLO VCOC

+ -
To: DECK CPU ADDT 0:15
IC3202
41.85MHz CLK
VCO
CLKO
CPU I/F DISCRI

41.85MHz DISCR
PB:H
DTR CTL1 SW
JIG CONN RECCTL PB_VCO REC:H
ATF
AD2
AINAD2
ATFO
GCA
BPF
RECCLK
ATF_GAIN
Fig. 2-5-2 PB equalizer and ATF block diagram In the playback mode the PB ENV signal output from the PB amplifier is branched into two in the IC3301 DV ANA; one is the signal for playback data and the other is that for ATF. The PBO signal output through the LPF and AGC is sent to the IC3201 DV EQ as that for playback data, while the ATFO signal output through the BPF and GCA is also sent to the IC3201 DV EQ as that for ATF. In the IC3201 DV EQ, the playback signal undergoes digitalization (AD1), waveform equalization (AUTO EQ), SI-NRZI channel decoding (1+D), and Viterbi-decoding (VITERBI). The resultant signal processed as mentioned above is output from the IC3201 as the playback data signal. At the same time, the PLL circuit constructed in this circuitry controls phase correction in order to generate the PB clock synchronizing with the playback signal. The 41.85MHz signal oscillated by the internal VCO of the IC3301 is output as the PB clock (PB CLK). Since the internal switch of the IC3301 varies the capacitance of the capacitor, the switch is turned off to minimize the capacitance of the capacitor when the level of the REC CTL is H, namely, in the Audio-Dubbing mode. As a result, the response time is shortened in that mode. The discriminator (DISCRI) compares the 41.85MHz signal oscillated from the VCO with the other 41.85MHz signal produced from the 81MHz of the main clock in order to detect a difference between the two frequencies. In the general playback mode, the discriminator outputs a Low-level signal when the frequency difference is +1% or more or a High-level signal when the difference is 1% or more. In the other modes, a Low-level signal is output when the frequency difference is +3% or more or a High-level signal is output when the difference is 3% or more. When the frequency difference is within 1% in the general playback mode or within 3% in the other modes, the output signal has high impedance. Therefore, a frequency difference, if there is, is roughly corrected. Regarding the signal for the ATF, the frequency component of the ATF pilot signal is extracted from the playback signal by the BPF and the ATF gain is adjusted by the GCA. Then, the ATF circuit in the IC3201 DV EQ detects a tracking difference using the pilot signals of F0, F1 and F2, and data on the detection result is transmitted to the servo CPU.
2-23
2.5.3 PLL operation

X5501 IC5501 TG V.DRV VCO405I 54MHz CLK27 81MHz IC3001 FRP GEN DVDSP MAIN_VCO ADJ JIG CONN MAIN_VCO IC3301 X3301
27MHz IC3101 1394 PHY PHYCLK 1394 LINK
FRP FRP
81MHz DVANA
REF FRP GEN PC PWM405
VCXO VCO405 VCO
CLK OSC X3001
MAIN CLK 40.5MHz REC CLK 41.85MHz
Not used
Serial I/F 12.288MHz 11.289MHz 8.192MHz ANA_DATA From DECK_CPU VCOAUD
REF 24.576MHz DOMCK PC PWMAUD
VCO
FS_PLLADJ VCOAUD FS_PLL JIG CONN IC3007 ANA_PD
Fig. 2-5-3 PLL operation block diagram The main clock for the deck section operates at a frequency of 40.5MHz, which is equivalent to 18MHz for the previous models. Since two memories of the SHUFFLE memory and the ECC memory that are needed for the previous models are integrated into one DRAM, the clock frequency is raised in order to increase the processing speed. For setting the clock duty ratio exactly at 50%, 40.5MHz clock is produced from the 81MHz clock. The PLL circuit of the main clock system produces 81MHz clock by the X'TAL X3301 and VCXO, and sends the 81 MHz clock to the IC3001 DV DSP. Using the frame pulse produced from the 81MHz pulse as the comparison signal of the PLL, the frame pulse (29.97Hz in NTSC or 25Hz in PAL) is produced from the 27MHz pulse output from the camera and this frame pulse is used as the reference signal of the PLL in the general recording and playback modes. However, the frame pulse produced by decoding the input DV signal is used as the PLL reference signal for phase comparison in the 1394 input mode. A phase error is output as the PWM405 signal, which passes through the filter circuit and controls the VCXO. For PLL adjustment, the filter output voltage is set nearly at the center (1.2V 0.1V) of the tolerance in the condition that the PLL is locked. There are three audio sampling frequencies (32kHz, 44.1kHz and 48kHz) provided, therefore, master clocks (8.192MHz, 11.289MHz and 12.288MHz) are produced by the VCO in the IC3301 for the respective sampling frequencies, and those master clocks are output to the IC3001 DV DSP. For adjusting the FS-PLL, the respective frequencies are adjusted in the free-run status.
2-24
2.5.4 Basic principle of Viterbi detection

Recording signal 1V point A "1" Threshold level PB signal 0V "0" Threshold level "-1" -1V Usual detection (Hard decision) Viterbi decoder A / D converter 1.0 "1" "1" 0.0 "0" "0" -0.4 "0" "-1" 0.8 "1" "1" 0.0 "0" "0" (V) Select the most reliable line "1" "0" "0" "1" ERROR !! "0"
Fig. 2-5-4 Basic principle of Viterbi detection Fig. 2-5-4 is a conceptual chart showing the basic principle of Viterbi decoding method. Decoding means a ternary decision that judges differential waveform at the identification point by the ternary criteria when NRZI-recorded signal is played back. The previous detection method is based on the ternary criteria of the preset identification level, and this method is called the hard decision because of the fixed identification level. By this method, for example, the identification value at the point "A" (in Fig.2-5-4) is "0", which represents an error occurrence. On the other hand, the Viterbi decoding adopts the soft decision method. In the Viterbi decoding, playback signal is converted from analog to digital data and then the signal level is read. If the signal level is 0.4V at the point "A" by ways of example, the previous method judges it as "0", but the Viterbi decoding method detects a possibility that it may be "0" or "1" and it assumes two kinds of bit strings of "10010" and "10110". Next, the Viterbi method introduces another criterion in decision. In the NRZI recording, there is a regularity in the recording signal and playback waveform. That is to say, there is a fall point between two rise points in the recording signal. This means that there must be "1" between "1" and "1". According to this principle, the bit string of "10010" is theoretically non-existent, and "10110" is consequently selected. As mentioned above, the Viterbi decoding method utilizes the regularity between bits or the redundancy of NRZI-recorded signal for error correction. The above explanation of the Viterbi decoding method is just a conceptual description, and a high degree of data processing system such as to select the most possible bit string from a great deal of probabilities is introduced in the actual Viterbi decoding.
2-25
2.5.5 Audio recording mode There are four basic modes in the DVC audio mode as shown in Table 2-5-1, and it is recommended that the DVC can cover all of the four basic modes by the specifications.
Mode 48K mode 44.1K mode 32K mode 32K-4ch mode 4 2 Channel Sampling frequency 48kHz 44.1kHz 32kHz 32kHz 12-bit non- linear 16-bit linear Quantiazation
Table 2-5-1 Audio basic modes

Tape travel
VIDEO
n tio mo ad He
VIDEO
AUDIO
CH 1
CH 2
1 Frame (10 Tracks)
NTSC 525/60 system

Tape travel
n tio mo ad He
AUDIO
CH 1
CH 2
1 Frame (12 Tracks)
PAL 625/50 system
Fig. 2-5-5 Audio track pattern
2-26
The audio recording system of this model is as follows. In the 2-channel mode, quantiazation is linearly processed in a data unit of 16-bits and the sampling frequency is 48kHz. In regard to the recording pattern, the first 5 tracks (6 tracks in PAL) of 10 tracks (12 tracks in PAL) in a frame is used for CH1 recording and the second 5 tracks in a frame is used for CH2 recording. Since audio data for one channel is interleaved extending over 5 tracks (6 tracks in PAL), it is possible to interpolate audio data by 1/5 (or 1/6 in PAL) if there is a data error in a track. In the 4-channel mode, quantiazation is non-linearly processed to convert 16-bits input data into 12-bit data and the sampling frequency is 32kHz. In regard to the recording pattern, the CH1 is used for recording sound-1 while the CH2 is used for recording sound-2 which is used for audio dubbing. The previous models show the audio mode by the sampling frequency of 48kHz or 32kHz, however, the recent models show it by 16-BIT or 12-BIT to meet the market trend.
Sound mode (MENU) 16 BIT Sampling frequency 48kHz CH 2 CH1 12 BIT 32kHz CH2 SOUND 2 SOUND 1 R ch L ch R ch L ch R ch Channel CH 1 L ch
Audio dubbing
Table 2-5-2 Channel format 2.5.6 Audio signal processing This model adopts a new audio signal processing IC, which comes equipped with AD and DA converter.
IC2201 Audio & A/D_D/A MIC
OFF EE/REC
Lch
EQ PHASE
ON
ALC MIX
PB
MUTE AUDIO I/F
A/V OUT
HPF
OFF
ADC MIX
DAC
PB
Rch
EQ PHASE
ON
ALC HPF
EE/REC
MUTE
VOL MIX VOL
SP
SHUTTER
IC3001 DECK DSP

16 12bits CONVERT DRAM I/F
CH1 CH2 CH1 CH2
MIX
AD I/F
AIDAT DOMCK DOBCK DOLRCK DODAT
CLK
12 16bits CONVERT
FADER
MIX
DA I/F
Fig. 2-5-6 Audio block diagram
2-27
2.5.7 Clock system for audio data DOMCK (Master Clock)

REC Sampling frequency 48kHz 32kHz 48kHz 44.1kHz 32kHz 32kHz DOMCK 256fs: 12.288MHz 384fs: 12.288MHz 256fs: 12.288MHz 256fs: 11.2896MHz 256fs: 8.192MHz 256fs: 8.192MHz
PLAY A. Dubbing
DOBCK (Serial Clock)

REC Sampling frequency 48kHz 32kHz 48kHz 44.1kHz 32kHz 32kHz DOBCK 36fs: 1.536MHz 36fs: 1.024MHz 36fs: 1.536MHz 36fs: 1.4112MHz 36fs: 1.024MHz 36fs: 1.024MHz
PLAY A. Dubbing
DOLRCK (LR Clock)

REC Sampling frequency 48kHz 32kHz 48kHz 44.1kHz 32kHz 32kHz DOLRCK 48kHz 32kHz 48kHz 44.1kHz 32kHz 32kHz
PLAY A. Dubbing
Table 2-5-3 Clock frequencies
DOLRCK
0 1 2 13 14 15 0 1 2 13 14 15
DOBCK
DODAT AIDAT
15
MSB
14
13
0
LSB
15
14
13
L ch DATA
R ch DATA
Fig. 2-5-7 Timing chart
2-28
2.5.8 Deck DSP IC function 1. Deck DSP (IC3001: JCY0106-2) pin functions (1/6)
Pin No. 69 1 134 70 2 71 3 135 189 226 72 4 136 73 190 5 227 137 74 6 191 138 75 7 8 76 139 192 228 9 77 140 193 229 10 78 141 230 194 11 79 142 231 OSC32O OSC44I OSC44O OSC48I OSC48O GND AUDIOTESTI AUDIOTESTIO VDDS DILRCK DIBCK DIMCK DIDAT AILRCK AIBCK AIMCK PHYCLK GND AIDAT [0] AIDAT [1] DOLRCK DOBCK DOMCK DODAT VDD AOLRCK AOBCK AOMCK AODAT [0] AODAT [1] VDDS GND Out Audio serial data output, (To ADC: IC2101) Open (Not used) Power supply Ground Open (Not used) Power supply Open (Not used) Out Out Out Out In Serial I/O interface channel clock for ADC, (To ADC: IC2101) Audio serial data clock, (To ADC: IC2101) Audio master clock, (To ADC: IC2101) IEEE 1394 crystal oscillator output (27MHz), (To 1394 PHY: IC3101) Ground Audio serial data input, (From ADC: IC2101) L: Fixed (Not used) VDD GND PWMAUDO VDDS VDD VCOAUDI VCOAUDO GND VDD OSC32I Label In/Out Out In Out In Out Power supply Ground Audio PLL control signal, (To DVANA: IC3301) Power supply PB audio b PLL input, (From DVANA: IC3301) PB audio b PLL adjustment voltage output Ground Power supply L: Fixed (Not used) Not used Open (Not used) L: Fixed (Not used) Open (Not used) 24.5MHz clock input 24.5MHz clock output Ground L: Fixed H: Fixed Power supply Description
Table 2-5-4 Deck DSP (IC3001: JCY0106-2) pin functions (1/6)

2-29
Deck DSP (IC3001: JCY0106-2) pin functions (2/6)

Pin No. 195 12 80 143 232 13 81 196 144 14 233 82 197 145 15 83 16 146 84 17 147 85 18 148 86 19 87 20 149 196 234 88 21 150 89 199 22 235 151 90 23 200 152 VDDS YSI [0] YSI [1] YSI [2] YSI [3] BRSI [0] BRSI [1] BRSI [2] BRSI [3] VDD OUTH OUTV INH INV GND VDD OSC27I OSC27O GND VDD RAMADRS [0] RAMADRS [1] RAMADRS [2] RAMADRS [3] VDDS RAMADRS [4] RAMADRS [5] RAMADRS [6] RAMADRS [7] GND RAMADRS [8] RAMADRS [9] Out Ground DRAM address output, (To 16M_DRAM: IC3002) Out DRAM address output, (To 16M_DRAM: IC3002) Power supply Out DRAM address output, (To 16M_DRAM: IC3002) Out Out In In In Power supply Horizontal reference pulse output for DVC PB, (To CAMERA DSP: IC4301) Vertical reference pulse output for DVC PB, (To CAMERA DSP: IC4301) Horizontal reference pulse input for DVC REC, (From CAMERA DSP: IC4301, ) Vertical reference pulse input for DVC REC, (From CAMERA DSP: IC4301) Ground Power supply 27MHz clock input, (From CAMERA DSP: IC4301) Open (Not used) Ground Power supply Not used In DVC record digital color difference signal input (From CAMERA_DSP: IC4301, ANALOG VIDEO I/O: IC3801) In DVC record digital luminance signal input (From CAMERA_DSP: IC4301, ANALOG VIDEO I/O: IC3801) YSO [0] YSO [1] YSO [2] YSO [3] BRSO [0] BRSO [1] BRSO [2] BRSO [3] Not used Power supply Out DVC playback digital color difference signal output, (To CAMERA_DSP: IC4301) Out DVC playback digital luminance signal output, (To CAMERA_DSP: IC4301) Label In/Out Not used Description
2-30

Pin No. 91 24 25 92 153 201 235 26 93 154 202 237 27 94 155 238 203 28 95 156 239 204 29 96 157 240 30 97 205 158 31 241 98 206 159 32 99 33 160 100 34 161 101 XINT CPUWAIT CPUAD [0] CPUAD [1] CPUAD [2] CPUAD [3] VDD CPUAD [4] In/Out Power supply Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401) In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401) VDD RAMWE RAMRAS RAMCAS [0] RAMCAS [1] RAMOE VDDS RAMDATA [0] RAMDATA [1] RAMDATA [2] RAMDATA [3] RAMDATA [4] RAMDATA [5] RAMDATA [6] RAMDATA [7] VDD RAMDATA [8] RAMDATA [9] RAMDATA [10] RAMDATA [11] RAMDATA [12] RAMDATA [13] RAMDATA [14] RAMDATA [15] GND XRESET GND CPUALE XCPUDSTB [0] XCPUDSTB [1] XCPURW XCPUCS In In In In In In In Ground Reset pulse input, (From DECK CPU: IC1401) Ground Bus address strobe signal input, (From DECK CPU: IC1401) Bus memory write enable signal input, (From DECK CPU: IC1401) Bus memory read enable signal input, (From DECK CPU: IC1401) Bus read/write select signal input, (From DECK CPU: IC1401) Chip select input, (From DECK CPU: IC1401) Not used Open (Not used) Wait command, (From DECK_CPU: IC1401) In/Out Audio/Shuffle/ECC memory data I/O, (From/To 16M_DRAM: IC3002) Power supply Not used In/Out Audio/Shuffle/ECC memory data I/O, (From/To 16M_DRAM: IC3002) Label In/Out Out Out Out Out Out Not used Power supply Write enable output, (To 16M_DRAM: IC3002) Lower address strobe, (To 16M_DRAM: IC3002) Address strobe (Lower bit), (To 16M_DRAM: IC3002) Address strobe (Upper bit), (To 16M_DRAM: IC3002) Output enable (L: active), (To 16M_DRAM: IC3002) Power supply Description
2-31

Pin No. 35 162 102 36 103 37 163 207 242 104 38 164 105 208 39 243 165 106 40 209 166 107 41 42 108 167 210 244 43 109 168 211 245 44 110 169 246 212 45 111 170 247 213 VDDS TESTIO [8] TESTIO [9] TESTIO [10] TESTIO [11] TESTIO [12] TESTIO [13] TESTIO [14] TESTIO [15] GND GND TESTIO [16] TESTIO [17] TESTIO [18] TESTIO [19] TESTIO [20] TESTIO [21] Open (Not used) Ground Open (Not used) Label CPUAD [5] CPUAD [6] CPUAD [7] GND CPUAD [8] CPUAD [9] CPUAD [10] CPUAD [11] VDDS CPUAD [12] CPUAD [13] CPUAD [14] CPUAD [15] VDD CPUWAITH VDD TESTIO [0] TESTIO [1] TESTIO [2] TESTIO [3] TESTIO [4] TESTIO [5] TESTIO [6] TESTIO [7] Not used Power supply Open (Not used) Power supply H: Fixed (Not used) Power supply In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401) Power supply In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401) Ground Not used In/Out Data (16bits)/Address (15bits) I/O, (From/To DECK CPU: IC1401) In/Out Description
2-32

Pin No. 46 112 171 248 47 113 214 172 48 249 114 215 173 49 115 50 174 116 51 175 117 52 176 118 53 119 54 177 216 250 120 55 178 121 217 56 251 179 122 57 218 180 123 Label TESTIO [22] TESTIO [23] VDD SCANENABLE SCANMODE TRST TDI TCK TMS TDO TEST VDD PHYDATA [3] PHYDATA [2] PHYDATA [1] PHYDATA [0] VDDS SCLK LOCONT XPHYISO PHYCTL [1] PHYCTL [0] PHYLREQ GND VDD EXTCLKIN EXREQ EXRW EXREADEMPTY EXWRITEFULL VDDS EXTDATA [0] EXTDATA [1] EXTDATA [2] EXTDATA [3] EXTDATA [4] EXTDATA [5] EXTDATA [6] EXTDATA [7] VDD GND Power supply Ground Open (Not used) Out Out In/Out Power supply IEEE1394 system clock (49.152MHz), (To 1394PHY:IC3101) H: Fixed Link interface isolation status (H: Enable), (To 1394PHY: IC3101) Link interface control (H: output), (From/To 1394PHY: IC3101) IEEE1394 link request signal output, (To 1394PHY:IC3101) Ground Power supply L: Fixed (Not used) H: Fixed (Not used) Open (Not used) Power supply Not used In/Out Link interface data input/output, (From/To 1394PHY: IC3101) In/Out In Open (Not used) Power supply Not used L: Fixed (Not used) Reset signal input for boundary scan H: Fixed (Not used) L: Fixed (Not used) H: Fixed (Not used) Open (Not used) L: Fixed (Not used) Power supply Description
2-33

Pin No. 58 59 124 181 219 252 60 125 182 220 253 61 126 183 254 221 62 127 184 255 222 63 128 185 256 64 129 223 186 65 225 130 224 187 66 131 67 188 132 68 133 PBDATA PBCLK VDDS TPNO [0] TPNO [1] TPNO [2] RECDATA RECCTL SPA RECCLK GND VCCA VCO4185 GNDA GND OSC4185I OSC4185O VDD VDD GND Out Out Out Out HSE (record data) output, (To PRE/REC: IC3501) Recording current control (H: ON), (To DVANA: IC3301) Pulse output for ATF sample, (To DVEQ: IC3201) Recording reference clock 41.85MHz Ground Power supply Constant for 41.85MHz VCO Ground L: Fixed (Not used) Open (Not used) Power supply Ground Open (Not used) PF [0] PF [1] SBE HID HSP VDDS VDD VCO405I VCO405O GND VDD CLK81SEL FRRES FRREF SERVOFRREF TRKREF SERVOTRKREF GND Label PWM405O In/Out Out In In In In Out Out In In Description 40.5MHz (PLL control output) 1/2 frequency of VCO405I, (To DVANA: IC3301) Power supply 81MHz VCO reference clock input, (From DVANA: IC3301) Open (Not used) Ground Power supply H: Fixed (Not used) L: Fixed Frame reference signal input, (From DECK CPU: IC1401) Open (Not used) Drum servo reference signal input (150Hz), (From DECK CPU: IC1401) Open (Not used) Ground Not used Open (Not used) Sync block error (Error pulse output) Head switch pulse (CH1: H, CH2: L), (To DECK CPU: IC1401) Not used VITERBI processing termination playback data input, (From DVEQ: IC3201) VITERBI processing termination playback clock input, (From DVEQ: IC3201) Power supply
2-34
2.5.9 Audio AMP IC function 1. Audio AMP (IC2201: AK4560VQ) pin locations and block diagram
GND (SVDD) SVDD 4.8V
MIC_IN_R
HPF_O_R
HPF_P_R
EQ_O_R
MIC SEL
EQ_P_R
MCLK
LRCK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
EQ_N_R PRE_O_R PRE_N_R MPWR 3.3V EXT MIC Rch INT MIC Rch MRF MVCM 2V GND (MVDD) MVDD INT MIC Lch EXT MIC Lch MA BIAS 2V PRE_N_L PRE_O_L EQ_N_L
49 50 51 52
EXT INT
HPF OFF
ON INT EXT
CCLK
33
BCLK
SPK+
SPK-
ND
PD
Clock Divider
Control Register I/F
32 31 30 29 28
CS DATA SDTI SDTO GND (VD) VD 3V A_MUTE HP OUT Lch HP OUT Rch HVDD 4.8V HVCM 2.4V LINE OUT Rch LINE IN Rch LINE OUT Lch LINE IN Lch SP IN
A/D Converter D/A Converter
HPF
Audio I/F Controller
53 54 55 56 57
Lch ALC AMP MIC Rch ALC AMP LINE
27 26 MIX 25 24 23
MIX
58
MIC LINE
59 60
EXT INT BEEP
22 21 20
BEEP SIG SIG
61 62
EXT
MIX
19 18
63 64
INT HPF OFF
ON VOL. VOL. AVR OUT
17
10
11
12
13
14
15
16
VREF1.5V
HPF_P_L
LINE OUT2 Rch
HPF_O_L
LINE OUT2 Lch
EQ_P_L
VCOM 1.5V
VA3V
MIC_IN_L
EQ_O_L
BEEP
GND (VA)
Fig. 2-5-8 Audio AMP (IC2201: AK4560VQ) pin locations and block diagram
2-35
AVR OUT
OPGR
OPGL
SHT
2. Audio AMP (IC2201: AK4560VQ) pin functions (1/2)

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Label EQ_P_L EQ_O_L HPF_P_L HPF_O_L MIC_IN_L VCOM (1.5V) VREF (1.5V) GND (VA) VA (3V) LINE OUT2 (Rch) OPGR LINE OUT2 (Lch) OPGL BEEP SHT AVR OUT SP IN LINE IN (Lch) LINE OUT (Lch) LINE IN (Rch) LINE OUT (Rch) HVCM (2.4V) HVDD (4.8V) HP OUT (Rch) HP OUT (Lch) A_MUTE VD (3V) GND (VD) SDTO SDTI DATA CS In/Out In Out In Out In Out Out Out In Out In In In Out In In Out In Out Out Out Out In Out In In/Out In L-ch EQ-Amp positive input L-ch EQ-Amp output L-ch HPF-Amp positive input L-ch HPF output L-ch MIC input Common voltage output, (1/2VA) ADC, DAC reference level, (1/2VA) Analog ground Analog power supply, (3.0V) R-ch No. 2 line output -5.5dBVVA=2.8V R-ch analog volume input L-ch No. 2 line output , -5.5dBVVA=2.8V L-ch analog volume input Beep signal input Shutter signal input Analog mixing output ALC2 input L-ch line input L-ch No. 1 line output, +2dBVVA=2.8V, VOL=+7.5dB R-ch line input R-ch No. 1 line output, +2dBVVA=2.8V, VOL=+7.5dB LINEOUT & HP-Amp common voltage output, (1/2HVDD) LINEOUT & HP-Amp power supply, (4.8v) R-ch Headphone-Amp output L-ch Headphone-Amp output Mute control, (L: Normal operation, H: Mute) Digital power supply, (3.0V) Digital ground Audio serial data output Audio serial data input Control data I/O Chip select Description
Table 2-5-5 Audio AMP (IC2201: AK4560VQ) pin functions (1/2)
2-36
Audio AMP (IC2201: AK4560VQ) pin functions (2/2)

Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CCLK BCLK LRCK MCLK PD SPK+ ND SPKMIC SEL GND (SVDD) SVDD (4.8V) MIC_IN_R HPF_O_R HPF_P_R EQ_O_R EQ_P_R EQ_N_R PRE_O_R PRE_N_R MPER (3.3V) EXT MIC (Rch) INT_MIC (Rch) MRF MVCM (2V) GND (MVDD) MVDD (4V) INT_MIC (Lch) EXT_MIC (Lch) MA_BIAS (2V) PRE_N_L PRE_O_L EQ_N_L Label In/Out In In In In In Out In Out In In Out In Out In In Out In In In Out Out In In In In Out In Control clock input Audio serial data clock Input/Output channel clock Master clock input Power down & reset, (L: Power- down & reset, H: Normal operation) Speaker Amp positive output Noise decrease (L: Disable, H: Enable) Speaker Amp negative output Internal/External MIC detect, (L: Internal MIC, L: External MIC) Speaker Amp ground Speaker Amp power supply, (4.8V) R-ch MIC input R-ch HPF output R-ch HPF-Amp positive input R-ch EQ-Amp output R-ch EQ-Amp positive input R-ch EQ-Amp negative input R-ch Pre-Amp output R-ch Pre-Amp negative input Not used External MIC Rch input Internal MIC Rch input MIC power supply ripple filter MIC block common voltage output MIC block ground MIC block power supply Internal MIC Lch input External MIC Lch input MIC-Amp bias L-ch Pre-Amp negative input L-ch Pre-Amp output L-ch EQ -Amp negative input Description
Table 2-5-5 Audio AMP (IC2201: AK4560VQ) pin functions (2/2)
2-37
2.6 SYSCON CPU

2.6.1 Contents of SYSCON CPU processing 1) User I/F control Recognition of Operation Keys and Menu Holding the User Configurations 2) Camera signal process control TG/CDS IC Camera DSP IC (Y/C Process, Special Effect, Encoder, OSD Mix, EVR etc.) 3) Camera Auto system control Transferring Auto system data with Camera DSP IC AF / AE / AW / EIS control Lens MDA control 4) Audio control 5) VF / LCD Monitor control 6) Servo CPU control 7) PC I/F control (TCCS / JLIP) 8) Remote control 9) Power control (Power ON / OFF) 10) RTC, Auto Light, RAE and others 2.6.2 Power ON process
START 1
S W Stable ? Yes
No
Reset start ? No EEPROM Data read
Yes
SW Position ON DC/DC Converter O N
OFF
Sleep mode setting
Prepherals CPU Initialize
END CAMERA DSP Reset relese V D Pulse ? Yes No END No
V D Pulse ? Yes 1
Fig. 2-6-1 Power ON process flow chart

2-38
2.6.3 System composition SYSCON CPU adopted with this model has five data communication systems and communicates with each peripheral device using those ports. There are three synchronous serial communication systems; one of these is used only for the model having DSC function. The communication with the Camera DSP is required a high-speed performance for transferring the information and command of camera auto processing. Therefore, it is adopted the 16-bit parallel bus communication. And the asynchronous serial communication (UART) is used for communication with external (PC, etc.).
TG V.DRV CDS / AGC ADC FOCUS ZOOM MDA VF / LCD DRVER
AUDIO
Synchronous Serial Communication 16-bit Multiplex bus
CAMERA DSP
REMOTE
SYSCON CPU
POWER SUPPLY UART
KEY PC I/F (TCCS / JLIP)
Synchronous Serial Communication
* D S C model only
RTC Back Up Built-in Lithium Battery
EEPROM
DECK CPU
DSC IF
DECK DSP
MDA
MECHA
M32 R/D CPU
FRASH ROM
Fig. 2-6-2 SYSCON CPU system structure
2-39
2.6.4 SYSCON CPU block diagram

IC7601 LCD DRV IC7603 EEP ROM
IC1001 SYSCON CPU

EDIT_CTL 118 JLIP_L 93 111 LCD_CS1 TXD 63 59 DATA_IN 47 LCD_LOAD 108 MONITOR_SW 85 MONI_RVS 54 MONI_UD 53 MONI_CTL 46 VF_MONI 1 EL_CTL RXD 62 JLIP_INT 38
JLIP
PC_IF
PC
MONITOR
KEY_A STOP REW FF PLAY/PAUSE DSC KEY_B LIGHT_SW
DSC_IF IC1401
DECK_OPE LIGHT_SW
73 KEY_A V_MUTE 37 ODD_EVEN 125 74 KEY_B
DECK CPU
AUDIO
127 126 128 123
PD_L ND_H A_MUTE S_MUTE
SRV_CS 26 SRV_RST 89 SRV_RDY 17
IC1004
S_DT_OUT 57 S_DT_IN 56 S_CLK 58 EEPROM_CS 49
64 AUDIO_CS
EE P R O M
Li +
IC5601 CDS/AGC A/D IC5502 TG V.DRIVER

61 CLK_OUT 60 DATA_OUT 80 TG_CS 122 TG_RST
IC1003
124 CDS_CS RTC_CS 92 RTC_INT 44 REG_4.8V TRIG_SW 101 PWR_LED DIAL_MN 102 DIAL_AUTO 103 DIAL_OFF 104 DIAL_PLAY 105 MENU_SET_SW 91 MENU_P_B 110 MENU_P_A 42 PHOTO_SW 36 SEL_SW 100 ZOOM_SW 75
RTC X1002
LITHIUM
IRIS DRV & HALL AMP IC4851 FOCUS/ ZOOM DRIVER

IRIS_PWM
120 IRIS_O/C
ZOOM UNIT
77 HOLE_AD
28 F/Z_CS 114 F/Z_RST CAM_VD CLK4M5
WB_IR_DET IR_A/D REMOTE TALLY AV_DET S_DET
27 76 55 52 45 43
JACK
OPTICAL BLOCK IC4001
79 F_PTR_AD 78 Z_PTR_AD 82 OP_THRMO
EJECT_SW 106 CAS_SW 107
JUNCTION REAR
IC1010 IC1009
MECHA
BATT_SW 84
16
3-6,9-15 BUS0-15 18-22 94 CLWE 95 CHWE 96 CRE 97 CALE 115 RWSEL 117 KRST/CLR 39 VD 33 MFLD 40 OMT 124 CCD_KIZU
RST 35
RST
3V
CAMERA DSP
PWR_CTL 16 BATT_CHK 72 VF_CTL 48 LAMP_ON 2
REG IC8001
DC LIGHT
24 16 IC8002 IC8003 16Mbits (2MB) FLASH ROM
V OUT
113 ASPECT1 116 ASPECT2
M32_CLK M32_DOUT M32_DIN M32_CS DSC_RST DSC_PCTL
67 66 65 41 81 88
DSC_IF
M32_R/D CPU
Fig. 2-6-3 SYSCON CPU block diagram

2-40
2.6.5 SYSCON CPU (IC1001: MN1021617HL) pin functions (1/3)

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Label EL_CTL LAMP_ON BUS0 BUS1 BUS2 BUS3 VDD VSS BUS4 BUS5 BUS6 BUS7 BUS8 BUS9 BUS10 PWR_CTL SRV_RDY BUS11 BUS12 BUS13 BUS14 BUS15 MODE0 MODE1 MODE2 SRV_CS WB_IR_DET F/Z_CS VDD OSCI OSCO VSS MFLD NMI RST PHOTO_SW V_MUTE JLIP_INT VD OMT M32_CS MENU_P_A S_DET In/Out Out Out Description Strobe emission control (To EL driver: IC756) Video light ON/OFF
In/Out
Address/Data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)
Power supply GND
In/Out
Address/Data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)
Out In
Power control Ready signal (From DECK_CPU: IC1401)
In/Out
Address/data MPX BUS 16bits (From/To CAMERA_DSP: IC4301)
In In In Out In Out In Out In In In In Out In In In In In In
L: Fixed L: Fixed H: Fixed (VDD) Chip select (To DECK_CPU: IC1401) Flicker detect Chip select (To F/Z DRIVER: IC4851) Power supply System clock (24MHz) System clock (24MHz) GND Field discrimination signal H: Fixed Reset Snap shot switch input Video mute JLIP interrupt Vertical sync signal EIS data readout timing Chip select (From DSC_IF: IC800) Menu dial pulse S terminal connection detect signal input
Table 2-6-1 SYSCON CPU (IC1001: MN1021617HL) pin functions (1/3)
2-41
SYSCON CPU (IC1001: MN1021617HL) pin functions (2/3)

Pin No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Label RTC_INT AV_DET VF_MONI LCD_LOAD VF_CTL EEPROM_CS VDD TIMER_OUT TALLY MONI_CTL MONI_UD REMOTE S_DT_IN S_DT_OUT S_CLK DATA_IN DATA_OUT CLK_OUT RXD TXD AUDIO_CS M32_DIN M32_DOUT M32_CLK VDD VSS AVSS VRefL BATT_CHK KEY_A KEY_B ZOOM_SW IR_AD HALL_AD Z_PTR_AD F_PTR_AD TG_CS DSC_R_ST OP_THRMO BATT_SW MONI_RVS VRefH In/Out In In Out Out Out Out Out Out Out Out In In Out Out In Out Out Out In Out In Out In In In In In In In In In Out Out In In In Description Clock 1 sec. Interrupt AV plug connection detect signal input VF/MONI select signal LCD data load pulse VF_REG4.8V ON/OFF control Chip select signal (To EEPROM: IC1003) Power supply Not used Tally lamp MONI_LCD back light control MONI_LCD L/R UP/DOWN reverse control Remote control input Serial data input (From DECK_CPU EEPROM RTC) Serial data output (To DECK_CPU TG/VDRIV CDS/AGC/ADC EEPROM RTC) Serial clock Serial data input (From: IC7603 LCD_SD) Serial data output Serial clock output RS232C data input RS232C data output Chip select signal to AUDIO IC2200 Serial data input (From DSC_IF: IC8001) Serial data output (To DSC_IF: IC8001) Serial clock input (From DSC_IF: IC8001) Power supply GND GND Reference power supply Battery DC input Deck operation switch input Camera operation switch input Zoom switch input AWB IR sensor AD input Iris hall generator AS input ZOOM position sensor AD input FOCUS position sensor AD input Chip select signal to TG/V.DRV IC5501 Reset signal output (To DSC_IF: IC8001) OP thermo detect signal input Not used DC pulg installation detect LCD reverse switch input ADC power supply (REG3V)
2-42
SYSCON CPU (IC1001: MN1021617HL) pin functions (3/3)

Pin No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Label AVDD DSC_PCTL SRV_RST OEM_REG5_CTL MENU_SET_SW RTC_CS JLIP_L CLWE CHWE CRE CALE VDD VSS SEL_SW TRIG_SW DIAL_MANUAL DIAL_AUTO DIAL_OFF DIAL_PLAY EJECT_SW CAS_SW MONITOR_SW MENU_P_B LCD_CS1 RESERVE ASPECT1 F/Z_RST RWSEL ASPECT2 KRST/CLR EDIT_CTL VDD(VPP) IRIS_O/C CDS_CS TG_RST S_MUTE CCD_KIZU ODD_EVEN ND_H PD_L A_MUTE In/Out Out Out Out In Out Out Out Out In Out In In In In In In In In In In Out Out Out Out Out Out Out Out Out Out Out Out In Out Out Out Description Power supply Power control (To DSC_IF: IC8001) Reset signal (To DECK_CPU: IC1401) Not used Menu set switch input Chip select signal (To RTC: IC1004) PC connection terminal switch (L: JLIP terminal, H: PC terminal) Write enable Write enable Read enable Address latch enable Power supply GND Snap shot mode switch Trigger switch Dial MANUAL Dial AUTO Dial OFF Dial PLAY EJECT switch detect Cassette switch detect Monitor OPEN/CLOSE switch detect Not used Menu dial pulse Chip select signal (To LCD EEPROM: IC7603) L: fixed S2 terminal output Reset signal (To F/Z DRIVER: IC4851) Read and write select (To CAMERA_DSP: IC4301) S2 terminal output Shutter sound reset/clear signal (To CAMERA_DSP: IC4301) JLIP remote pause output terminal (Edit terminal) Power supply Iris OPEN/CLOSE Chip select signal (To CDS/AGC/AD: IC5601) Reset signal (To TG/V.DRV: IC5501) Shutter sound mute Blanking ON/OFF control (at white noise adjustment) Odd/Even field discrimination signal at slow playback Noise decreasing circuit control (L: OFF, H: ON) Power down signal output (L: power down) Audio mute
2-43
2.7 DECK CPU

2.7.1 Contents of DECK CPU processing 1) Mechanism control Loading motor control Drum motor control Capstan motor control 2) Deck LSI control DV DSP IC control PRE / REC IC control 3) OSD control On screen process 4) 1394 control 5) Sensor control Tape sensor Reel sensor DEW sensor Emergency process 2.7.2 DECK system composition
ON SCREEN SYSCON CPU
PC I/F
UART
16-bit Multiplex bus MDA
DECK CPU
MECHA 16-bit Parallel bus Synchronous Serial Communication
PRE / REC
DV_EQ
DECK DSP
DV_ANA
16M DRAM
1394 PHY
DV Terminal
Fig. 2-7-1 DECK CPU system structure

2-44
2.7.3 Tracking Error information

Flame Pulse
Track Pulse (Track reference Number) HID (HEAD SW)
(9)
(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(0)
(1)
(CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2) (CH1) (CH2)
HEAD
Tape pattern (Pilot signal) ( f1 ) FFh 80h 00h Tracking is the center ( f0 ) ( f2 ) ( f0 ) ( f1 ) ( f0 ) ( f2 ) ( f0 ) ( f1 ) ( f0 ) ( f2 ) ( f0 ) ( f1 )
Tracking Error
Tracking is off (1)
Tracking is off (2)
Fig. 2-7-2 Tracking Error explanation (NTSC) Fig. 2-7-2 shows the tracking error detection method. The DVC multirecords three kinds of pilot signals of f0 (0), f1 (465 kHz) and f2 (697.5 kHz) on each track. When the CH1 head traces the track on which the f0 pilot signal is recorded in playback, the crosstalk component of the pilot signals of f1 and f2 recorded on the preceding and following tracks are detected and compared. When the tracking is well controlled, the error rate is 80h that is the intermediate value between 00h and FFh. When the tracking deviates in the f1 track side, the error rate is lower than 80h. When the tracking deviates in the f2 track side, the error rate is higher than 80h. When the CH2 head is tracing the track, the error rate is 00h or FFh because only the f1 or f2 component is detected. Such the tracking error information is digitally processed by the ATF inside the DV-EQ IC and the processed data is transmitted to the DECK CPU through the 16-bit bus. The DECK CPU controls the capstan servo according to the data transmitted from the DV-EQ IC.
2-45
2.7.4 1394 interface control The DECK CPU has the function of the host microcomputer of the 1394 interface. It mainly controls the LINK IC, PHY IC and 1394 bus besides AV/C command processing. The AV/C command is classified into the VCR control commands such as for PLAY, STOP, FF, REW, REC operations and for status information such as time code, mode status, etc. For details of the 1394 interface (i.LINK), refer to the Technical Guide to the i.LINK.
IC3001 IC1401 DECK_DSP IC3101 1394 PHY DV Terminal
DECK CPU
1394 LINK
Fig. 2-7-3 1394 interface block 2.7.5 JLIP Video Capture The DECK CPU incorporates the asynchronous serial communication (UART) port for communication with external equipment (personal computer, etc.). The UART port is used for image data transmission for inputting DVC playback picture that is captured by use of the JLIP Video Capture into a personal computer. When a DVC playback picture is captured, playback data for 1 frame is once held by the DRAM and then transmitted to the DECK CPU through the 16-bit bus and it is finally output from the UART port to a personal computer. The image data transmitted to a personal computer is formatted in the DV stream, and the personal computer encodes the DV data with the software.
IC1401 IC3001 IC3002 DECK_DSP 16M DRAM
PC Terminal
PC IF
DECK CPU
UART
16-bit Parallel bus
Fig. 2-7-4 JLIP Video Capture output
2-46
2.7.6 DECK CPU block diagram

IC5501 TG V.DRV IC1001
180 MSELECT 89 SYS_CLK 74 SYS_OUT 78 SYS_IN 237 SRV_RDY 55 RESET 100 ODD_EVEN 16 VMUTE_IN 2 4 PD0-3 PC0-1 DV_INT 226 DV_INT 204 HID 207 HID_IN 219 FRP 190 TSR 218 TSR 231 SPA 174
IC1401 DECK CPU

72 OSCI PHY_RST 61 PHY_PD 3 PHY_CNA 15
IC3101 1394 PHY
DV
IC3001
SYSCON CPU
16
JLIP PC_IF PC
DECK_DSP
10
77 TXD DV_RST 99 DV_CS 104 OK 37 16 ADM0-15 WE0 12 RE 24 RWSEL 5 AS 47
59 RXD
DSC_IF IC4301 CAMERA DSP IC1002 ON SCREEN

28 OSD_CS 75 OSD_CLK 58 OSD_DATA 188 VD
IC3201
DV_EQ
EQ_CS 85 EQ_RST 120 EQ_TRST 83
A_REG_3V SYSCON CAS_SW EJT_SW 29 MIC_CTL 42 MIC_SDA 57 MIC_SCL 184 BCID1 181 BCID2 183 BCID3 135 REC_SAFE A_REG_3V
ANA_PD 45
VCOAUD
IC3301
ANA_CS 14 ANA_CLK 109 ANA_OUT 93 ANA_IN 108 V_PB_L 84
DV_ANA
REG_4.8V
IC3501 PRE/REC
JUNCTION
MECHA SENSOR
134 REEL_LED 187 TAPE_LED
PBH 117 REC_I 116 HID_3 119
199 S_SENS 182 E_SENS 230 S_REEL 189 T_REEL
IC1601
MDA_CS 195 MDA_CLK 91 MDA_IN 94 DRUM_PG DRUM_FG DRUM_FG DRUM_FG DRUM_REF 196 238 229 201 191
DEW SENSOR ROTARY ENCODER
200 DEW_SENS
148 CAM0 132 CAM1 136 CAM2
MDA
CAP_FG 173 CAP_REF 221 CAP_BRAKE 1
REG
65 D_GAIN LD_ON 27
Fig. 2-7-5 DECK CPU block diagram

2-47
16M-DRAM
2.7.7 Deck CPU (IC1401: MN103004KRH) pin functions (1/5)

Pin No. 1 27 14 28 2 29 3 61 15 45 16 46 4 30 31 62 5 47 17 63 49 32 18 79 6 48 64 7 65 19 33 20 82 50 66 8 67 51 34 9 35 21 52 10 36 22 23 Label CAP_BRK LD_ON ANA_CS OSD_CS VSS MIC_CTL PHY_PD PHY_RST PHY_CNA ANA_PD VMUTE_IN VDDH RWSEL AS VSS D_GAIN VDDB ADM15 ADM14 ADM13 ADM12 ADM11 ADM10 ADM9 ADM8 VSS ADM7 ADM6 ADM5 ADM4 ADM3 ADM2 ADM1 ADM0 In/Out Out Out Out Out Out Out Out In Out In Out Out Description Capstan motor brake control Loading motor ON/OFF control Chip select signal (To DV_ANA: IC3301) Chip select signal (To OSD: IC1002) GND Power supply control to MIC Power down control (To PHY: IC3101) Reset output (To PHY: IC3101) IEEE1394 connection detect (Connect: L) Power down control (To DV_ANA: IC3301) Video mute input Not used Power supply (REG_3V) Not used Read/write select signal of Bus Address strobe signal of Bus Not used GND
Not used
Out -
Drum error gain control Power supply (REG_3V)
In/Out
Address/Data MPX BUS 16bits (From/To DECK_DSP: IC3001, DVEQ: IC3201)
GND
In/Out
Address/Data MPX BUS 16bits (From/To DECK_DSP: IC3001, DVEQ: IC3201)
Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (1/5)
2-48
Deck CPU (IC1401: MN103004KRH) pin functions (2/5)

Pin No. 11 37 24 38 12 40 53 56 54 55 70 71 69 68 72 88 86 87 85 104 102 103 101 100 84 99 83 120 118 119 116 117 134 135 133 136 132 148 149 152 150 151 147 Label VDDB DK(L) RE(L) WE1(L) WE0(L) PVDD PVSS MMOD1 MMOD0 RESET(L) FRQS VSS EXMOD1 EXMOD0 OSCI OSCO VDDH SYSCLK EQ_CS DV_CS CS1(L) CS0(L) VDD ODD_EVEN V_PB_L DV_RST EQ_TRST EQ_RST VSS HID_3 REC_I PBH REEL_LED REC_SAFE VDDH CAM2 CAM1 CAM0 AVSS In/Out In Out Out In In Out Out Out Out Out Out Out Out Out Out Out In In Description Power supply (REG_3V) Servo CPU ready signal (Low: Deck mode) Read enable signal Test terminal (TL1401) Write enable signal Power supply (REG_3V) GND Control port for FLASH CPU Reset input (From SYSCON CPU: IC1001) L: fixed GND H: fixed H: fixed 27MHz clock input (Form TG/V.DRV: IC5501) Test terminal (TL1423) Power supply (REG_3V) Test terminal (TL1433) Chip select signal (To DV_EQ: IC3201) Chip select signal (To DECK_DSP: IC3001) Test terminal (TL1402) Test terminal (TL1403) Power supply (REG_3V) Odd/Even field discrimination signal at slow playback (FRAME ADVANCE) Video track area recording off signal Reset signal output (To DECK_DSP: IC3001) Reset signal output (To DV_EQ: IC3201) (For Boundary scan) Reset signal output (To DV_EQ: IC3201) GND Head switch pulse (control of recording current measure circuit) ON/OFF control for recording circuit (To PRE/REC IC) ON/OFF control for playback circuit (To PRE/REC IC) Reel sensor LED control REC safety switch Power supply (REG_3V) Mechanism position detect from rotary encoder GND Not used
2-49

Pin No. 164 166 167 163 168 165 183 181 184 200 182 199 198 216 214 239 213 240 197 227 212 226 196 238 180 225 195 237 179 211 210 236 194 224 209 235 178 223 193 208 Label BCID3 BCID2 BCID1 DEW_SENS E_SENS S_SENS VREFH AVDD ADTRG(L) NMI(L) VSS DV_INT DRUM_PG DRUM_FG MSELECT VDD MDA_CS SRV_RDY AGC_RST VSS In/Out Description
Not used
In In In In In In In In In In Out Out Out
Cassette tape ID board information Dew sensor detect End sensor detect Start sensor detect Reference voltage Power supply (REG_3V) H: fixed H: fixed GND Not used DV_DSP interrupt signal Drum PG Drum FG DECK_CPU chip select input (Form SYSCON CPU: IC1001) Power supply (REG_3V) Chip select signal to MDA IC1601 DECK_CPU ready signal output (To SYSCON CPU: IC1001) Video output clamp control (To A/V OUT SECTION)
Not used
GND
Not used
2-50

Pin No. 162 222 177 234 192 207 176 233 191 221 175 232 159 220 206 231 190 204 174 219 205 230 189 218 173 229 203 201 187 185 188 186 171 169 172 170 158 154 156 153 157 155 Label VDDH HID DRUM_REF CAP_REF VSS STR FRP DV_INT SPA HID_IN VDD S_REEL T_REEL STR CAP_FG DRUM_FG DRUM_FG TAPE_LED VSS VD VDD VSS In/Out Out Out Out In In In In In In In In In In In Out In Not used Power supply (REG_3V) Head switch pulse output Not used Not used Drum offset voltage output (To MDA: IC1601) Capstan offset voltage output (To MDA: IC1601) Not used GND HID reference (Drum 150Hz reference) Frame pulse (From DECK_DSP: IC3001) DV_DSP interrupt signal Pulse for ATF sample Head switch pulse input Power supply (REG_3V) SUP reel pulse TU reel pulse HID reference (Drum 150Hz reference) Capstan FG Drum FG Not used Drum FG Tape sensor LED control GND Vertical reference pulse (Form CAMERA_DSP: IC4301) Not used Power supply (REG_3V) Description
Not used
GND
2-51

Pin No. 140 138 142 139 141 137 124 122 123 121 125 106 107 105 109 108 93 91 94 90 92 89 78 74 76 73 77 59 75 58 60 57 43 42 44 41 Label VDDH VPP BR(L) VSS ANA_CLK ANA_IN ANA_OUT MDA_CLK MDA_IN VDD MDA_OUT SYS_CLK SYS_IN SYS_OUT VSS TXD RXD OSD_CLK OSD_DATA MIC_SCL VDDH MIC_SDA In/Out Description
Not used
Out Out In Out Out In In Out In Out In Out Out Out In -
Power supply (REG_3V) Not used Power supply (REG_3V) H: fixed GND Serial clock (To DV_ANA: IC3301) Serial data bus output (To DV_ANA: IC3301) Serial data bus input (From DV_ANA: IC3301) Serial clock (To MDA: IC1601) Serial bus data output (To MDA: IC1601) Power supply (REG_3V) Serial bus data input (From MDA: IC1601) Serial clock (From SYSCON CPU: IC1001) Serial bus data output (To SYSCON CPU: IC1001) Serial bus data input (From SYSCON CPU: IC1001) Not used GND RS232C output RS232C input Serial clock (To OSD: IC1002) Serial bus data (To OSD: IC1002) Not used Serial clock for MIC Power supply (REG_3V) Serial data for MIC Not used
2-52
SECTION 3 HEAD CLOG WARNING

3.1 HEAD CLOG WARNING OF DVC
The method and criterion of DVC head clog detection have been changed from this DVC series. Differently from the previous models which detect head clog in the recording mode only, the new system incorporated in this series detects head clog in both the recording and playback modes based on the new detection criterion that is much more strict with possible error as compared with the previous system. When the head clog warning is occurred on the DVC with the previous detection system, it is impossible to play back the data correctly rather than the recording data is deteriorated. On the other hand, the DVC with the new detection system warns the user about deterioration in recording signal because of head clog. 3.1.1 Structure of Sync Blocks and Error correction The structure of sync blocks and error correction of the DVC will be explained first. In the digital magnetic recording and playback system, there is a possibility that random error and burst error caused by signal dropout in tape occur. Generally, the data transmission systems which quality is not so good adopt the packet data transmission system for the necessity of frequent reproducing (playback) synchronization. Therefore, the DVC records data in the form of sync blocks. One sync block of the AUDIO/VIDEO sector consists of 2 bytes of sync area, 3 bytes of ID code to identify the attribute of data, and 85 bytes of inner codes. A definite sync pattern is recorded in each sync area. If the definite sync pattern is not detected in playback, the data in the sync block cannot be restored and played back. An ID code consists of 3 bytes, namely, 2 bytes of ID and 1 byte of ID parity. The content of the ID of the AUDIO/VIDEO sector is 4 bits of a sequence number showing the continuity of frames, 4 bits of track pair number showing the track number, and 8 bits of sync block number showing the row of sync blocks. Since the 8-bytes inner parity is added to the AUDIO/VIDEO sector, maximum four errors can be corrected by this 8-bytes parity and considerable random errors can be corrected also. Moreover, the 11-bytes outer parity is added to the VIDEO data and 5-bytes outer parity is added to the AUDIO data. Therefore, burst error caused by signal dropout in tape can be corrected by those parities. As mentioned above, the optimum error correction strategy with the inner and outer parities is constructed for intermingled random errors and burst errors in consideration of the dropout characteristic of the tape medium to be used. Number of sync blocks in the AUDIO sector is 17 (14 in the data area besides 2 pre-sync blocks and 1 post-sync block). Number of sync blocks in the VIDEO sector is 152 (149 in the data area besides 2 presync blocks and 1 post-sync block).
Sync Block length : 90 Byte 5 Sync block number Pre-sync block (2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 5 9 72 Byte-position number 81 8 89
Data-sync block (14)
Sync Area
AUDIO AUX (AAUX) ID Code
AUDIO DATA Inner Parity
Outer Parity
Post-sync block (1)
Fig. 3-1-1 Structure of sync blocks in audio sector

3-1
Sync Block length : 90 Byte 77 Sync block number Pre-sync block (2) 17 18 19 20 21 0 1 2 3 4 5 9 Byte-position number 81 8 89
VIDEO AUX (VAUX)
Sync Area
Data-sync block (149) 156 157
VIDEO DATA ID Code VIDEO AUX (VAUX) Outer Parity Inner Parity
Post-sync block (1)
167 168
Fig. 3-1-2 Structure of sync blocks in video sector The length of sync blocks of the sub code is just 12 bytes. The sub code has the fast search function to search the target point at a high speed. In the fast search mode, if the tape speed is increased, the angle that the head scans the track is decreased and the form of signals that can be read by one scanning becomes like beads on an abacus. If data of signals read by one scanning are not grouped as a sync block, those data cannot be decoded and played back. Therefore, the length of a sync block is shortened to secure the reproducibility of data. Since the probability to pick up the outer parity is very low in the fast search mode, no outer parity is prepared in the sub code differently from the AUDIO/VIDEO sector. In order to secure the reproducibility and reliability of playback data, the same data is not only written twice in different parts of a track but also written in a half of a frame (in 5 or 6 tracks). In other words, the same data is written over and over 10 times or 12 times in the tracks of the first half of a frame. The next data is multiply written in the second half of the frame in the same manner, namely, written 10 times or 12 times repeatedly.
Sync Block length : 12 Byte Sync block number 0 1 2 3 4 5 6 7 8 9 10 11 Byte-position number 0 1 2 3 4 5 6 7 8 9 10 11
Data-sync block
ID Code
Sub-code DATA
Fig. 3-1-3 Structure of sync blocks in subcode sector
3-2
Inner Parity
Sync Area
3.1.2 Error Rate of DVC The error rate of the DVC is shown by the average number of error corrections by the inner parity in the AUDIO/VIDEO sector (A/V inner errors) per 1 second (300 tracks). Error correction is carried out by the ECC inside the DV-DSP IC, and the ECC outputs Error Flag SBE (Sync Block Error). The SBE is classified into 7 levels from 0T pulse to 12T pulse according to number of error connections, and it is output for each of 14 sync blocks of the AUDIO sector and 149 sync blocks of the VIDEO sector. For evaluating the error rate actually, all SBE pulses that were output in 1 second are weighted by a certain method and the total of the weighted SBE's is used as the DVC error rate.
Weighting for SBE 0 0 1 2 3 4 5
0T: Sync failuer 2T: Error free 4T: 1-error correction 6T: 2-error correction 8T: 3-error correction 10T: 4-error correction 12T: Correction-disabled 1T=18MHz 1clock
Fig. 3-1-4 Particulars of SBE The error rate jig in its infancy shows the total of weighted data of input SBE's by a frequency counter. However, the error rate of the recent DVC models (GR-DVM5 and after) is output by the TCCS and can be shown on the display of a personal computer by use of the Service Support Software (SSS).
Graph showed a change in the Error Rate visually White line: CH1 Pink line: CH2 Green line: 500 reference
Percentage of sync block counting in Audio/Video sector
Numerical value of Error Rate
Fig. 3-1-5 Error Rate window in SSS

3-3
3.1.3 Previous method of head clog detection The previous head clog detection system (for the models of GR-DVL9800 and before) is based on the count of sync blocks as the criterion. The count of sync blocks that a head plays back per frame is: NTSC: ( Audio 17 + Video 152 ) 5 Track = 845 PAL: ( Audio 17 + Video 152 ) 6 Track = 1014 Strictly explaining, number of sync blocks of the ITI sector and sub code sector must be added to the above count. However, these additional counts cannot be detected by the system of the third generation models (GR-DVX7 and after). If some sync block is not detected, the data in the sync block is treated as an error that is impossible to correct. If the status that the count of sync blocks in the AUDIO/VIDEO sector per 1 frame is lower than 240 of the threshold level continues in the short-playback mode just after start of recording for a certain period (more than 0.5 second), the system judges that the head is clogged. In other words, the system recognizes the head clog when the quantity of playback data is one-fourth as little as the normal. Therefore, if the system detects head clog in recording, it recognizes the recording part as impossible for playback (regards as no-signal recording). The short-playback mode just after restart (resuming) of recording is the status that the tape is rewound for 1.5 second (back-space) according to the absolute track number that is memorized as recording is suspended (by pause operation). When recording is resumed (restarted), the tape is transported in the play mode first and then recording is actually resumed with the point of the memorized track number. This period is called the short-playback period (mode). Head clog detection is not started at the first start of recording but done at every resuming of recording for the second time, third time, and so on.
REC stop REC start REC Back Space Track No. Finding REC
1.5 sec
Short PB
Fig. 3-1-6 Short Play Back
3-4
3.1.4 New method of head clog detection The new head clog detection system (for this DVC series and after) performs detection in the normal (usual) playback mode besides the short-playback mode just after resuming of recording as well as the previous system. The criterion of the new detection system is not the count of sync blocks but number of A/V inner errors per frame. 1) Detection in normal playback Only when sync data recorded on both channels or one channel is read in the normal playback mode (after detection of non-signal part), the new system judges that the head is clogged and warns the user about it if number of A/V inner errors per frame continuously exceeds the threshold level for 7 seconds (for 210 frames: 30 x 7). If errors less than the threshold level are continuously detected for 2 seconds after that, the system judges the head as not clogged and cancels the warning indication. If the playback is suspended or discontinued in the head clog status, the warning indication remains as it was until the system detects no clog, or Eject or Power Off operation is performed. 2) Detection in short playback In the period of short-playback just after recording is resumed, the servo controls the track position according to the self-recording just before recording is suspended and the detection system judges the head clog and warns the user about it if the status that number of A/V inner errors per frame exceeds the threshold level continues for 6 frames (for about 0.2 second) after the capstan phase was locked. If recording is suspended (by pause operation) as the head is clogged, the warning indication remains until the system detects no clog in the short-playback mode or Eject or Power Off operation is performed. 3) Setting of threshold level The error threshold level is set by the EEPROM as follows. 5 low-order bits in 8 bits: Threshold level in normal playback (0 ~ 31) 3 high-order bits in 8 bits: Coefficient in short-playback (0 ~ 7) The actual threshold level in the normal playback is 10 times as high as the standard setting value, and that in the short-playback is several times as high as the actual threshold level in the normal playback because of the short detection time. If this detection level is converted into number of A/V inner errors per second (the error rate), it approximates to 10,000. In other words, the system judges that the head is clogged when number of A/V inner errors per second exceeds 10,000. If the threshold level of the previous sync block count system is converted into the error rate, it approximates to 1,000,000. As compared with the sync block count system, the detection capacity of the new detection system is improved by 20 dB or so.
3-5
Previous method (GR-DVL9800 and before) Detection period Judgment element Threshold level and Continuation period Error rate conversion During Short PB at recording start The number of Sink block counts par 1 frame Below 240 0.5 sec Rough estimate: 1,000,000
New method (GR-DVL300 series) During Normal PB and Short PB at recording start The value of A/V inner error par 1 frame Normal PB Short PB
Over 600 Over 150 7 sec 0.2 sec Rough estimate: 10,000
Note: The threshold level of new method is decoded by data in EEPROM. EEPROM Address: 3AEh Data: 8Fh 10001111 Lower 5 bits: Setting of threshold level in normal PB 01111 15 Value of threshold level in normal PB: 15 10 = 150 Upper 3 bits: Coefficient of short PB 100 4 Value of threshold level in short PB: 150 4 = 600 Above addresses and threshold levels are for GR-DVL300 series, and those may vary in the model. Table 3-1-1 Difference of the head clog method 4) History of head clog warning With detection of head clog, the EEPROM counts the data and the history of head clog warnings can be checked on the display of a personal computer with the SSS (Service Support Software). Other specifications are as follows. If sync block data is read from neither of two channels for 10 continuous frames, the system recognizes that no signal is recorded in the part and does not perform clog detection. (The cleaning tape is recognized as a non-recorded tape.) Head clog detection in the short-playback mode is not performed at the first start of recording. Head clog detection is not performed in any mode other than the normal playback mode such as the FF/REW, Special Playback, Audio-dubbing/Insert modes. Method to display marks and messages conforms to the specifications of respective models.
3-6
SECTION 4 DOCTOR SYSTEM

4.1 WHAT IS DOCTOR PROGRAM?
The function and performance of a product (an electric/electronic appliance in this case) generally depends on the program of the internal microcomputer. If there is some fault in the electrical function and performance of a product, the program of its microcomputer should be changed (upgraded) at the expenses of the manufacturer. To prepare for an unexpected trouble, recently manufactured articles store a part of the program data in the EEPROM coupled with the microcomputer so that the program of the microcomputer can be easily revised. Such the program data written in the EEPROM coupled with the microcomputer is called the "Doctor Program". If the microcomputer of an article has no need of support of the Doctor Program, no program data is written in the EEPROM. Even in such the case, the EEPROM of recent products prepares specific addresses (several bytes to dozens of bytes) as the area to write the Doctor Program. The area (addresses) differs from model to model. Since the Doctor Program must vary depending on the program of the microcomputer and expected troubles, its matching with the microcomputer (program) is very important. 4.1.1 Matching of Doctor Program with Microcomputer Program The program of the microcomputer can be revised by rewriting the Doctor Program stored in the EEPROM coupled with the microcomputer. However, if the program of the microcomputer is changed by upgrading or so, the Doctor Program conforming to the previous program stored in the EEPROM is useless. If the microcomputer that is consistent with the Doctor Program stored in the EEPROM is replaced with a new microcomputer of an upgraded one, continuous use of the Doctor Program to cope with a trouble may develop an unexpected situation. An example of progress of revisions (upgrading) of the microcomputer program and EEPROM Doctor Program is shown below.
Microcomputer A Microcomputer B
No Doctor Program
Doctor Program A
Doctor Program B
No Doctor Program
Doctor Program B
Fig. 4-1-1 Example of progress of revisions If there is such the change in production of a series of products, matching of the microcomputer and Doctor Program with each other is as follows. Microcomputer A + No Doctor Program, Doctor Program A, or Doctor Program B = OK, Microcomputer B + No Doctor Program or Doctor Program C = OK, Microcomputer A + Doctor Program C = NG, Microcomputer B + Doctor Program A or Doctor Program B = NG. If the Doctor Program mismatches the microcomputer program, the product falls into troubles showing various symptoms when the Doctor Program is rewritten and it is difficult to specify the cause of the trouble, for example, the product fails in power supply or shows the picture abnormally depending on the situation. Such being the case, pay careful attention to matching of the Doctor Program with the microcomputer program (version).
4-1
4.1.2 Use of Doctor Program for Camcorder Doctor Programs have been widely used for stationary video decks, however, the function of the Doctor Program is an obstacle to repair of the product, namely, it occasionally brings about secondary troubles if the program data stored in the EEPROM mismatches the microcomputer program as mentioned previously. Under the circumstances that most of stationary video decks are not backed up by service support system software and there is no means to read and write data stored in the EEPROM's of them, the only way to cope with mismatching between the microcomputer program and Doctor Program is to replace the EEPROM with a new one conforming to the microcomputer program or to kill the Doctor Program electrically (to remove the resistor or to add a resistor). Although it is easy to replace the EEPROM, the manufacturer is burdened with severe inventory management of spare parts because it is required to have a large stock of differently written EEPROM's to supply them properly to various microcomputer programs. No Doctor Program had been adopted for camcorders until quite recently, however, late camcorder models such as the GR-DVL9500 series and after adopt the Doctor Program. Fortunately such the camcorders don't need to replace the EEPROM's with those which proper data are written in, because data stored in the EEPROM can be rewritten by means of the service support system software. In such the case servicemen are required to pay careful attention to matching between the microcomputer program and the EEPROM data including the Doctor Program. 4.1.3 Revision of Service Support System Software for Doctor Program To rewrite camcorder's Doctor Program in the field and to avoid trouble caused by mismatching between the microcomputer program and Doctor Program, the Service Support System Software is reexamined and revised as follows.
Doctor Load
Fig. 4-1-2 EEPROM Utility window
4-2
1. Specification of Doctor Program area If there is a Doctor Program area in the EEPROM data, the area is specified by coloring (gray) the cell on the EEPROM utility map. 2. Deletion of Data Editing Function in Doctor Program Area To avoid trouble caused by data editing in the Doctor Program area, data editing is disabled for the colored cell (Doctor Program area). 3. Addition of Data Rewriting Function in Doctor Program Area Only If there is a need of rewriting of the Doctor Program in the field, the manufacturer announces it through the MCI or Service Bulletin and supplies an EEPROM initial data file including revised Doctor Program data to the dealers, service stations and others concerned. For rewriting the Doctor Program data, it is required to use the "Doctor Load" (refer to "Procedure to Rewrite Doctor Program" to be mentioned later) that is the special function to renew the Doctor Program area only without disturbing other data such as adjustment data, fixed data and so on. In other words, this special function secures the productivity of the camcorder. 4. Deletion of Doctor Program from Initial Data File Every service support system software is supplied together with the initial data file. The initial data file to be used for servicing the model that is designed to be doctored by the Doctor Program from the first stage of the production should contain the Doctor Program. However, the initial data file for service use is supplied without the Doctor Program in order to avoid possible trouble caused by mismatching of the Doctor Program with the microcomputer program as mentioned previously, because the initial data file is prepared based on the initial data at the beginning of the production. Such being the case, the service support system software may not demonstrate full of the original function in doctoring the product with the Doctor Program, however, this demerit is ignored from a viewpoint that doctoring with the Doctor Program is a simple and easy measures against trouble. In the case the microcomputer is replaced with new one and it is programmed by the backup data, pay heed the Doctor Program whether it matches the microcomputer program or not, because the aforementioned way of thinking does not apply to backup data. 4.1.4 Procedure to Rewrite Doctor Program The special function "Doctor Load" is newly added to the service support system software. The "Doctor Load" function facilitates renewal of data in the Doctor Program area only and deletion of the Doctor Program. 1. Data Renewal in Doctor Program Area Only In case of necessity of field service to revise the Doctor Program, the manufacturer supplies a data file necessary for the service. The revision data file is the same format as the initial data file supplied with the service support system software. If the initial data is rewritten in the EEPROM in the usual manner when revising the Doctor Program, it brings about such a trouble as other data, for example adjustment data and data to be fixed, are also rewritten at the same time. To avoid such a trouble, the new function "Doctor Load" can be used. 1. Read out the EEPROM data. 2. Open the supplied data file (including Doctor Program data) using the "Doctor Load" function After the data file is loaded, data only in the Doctor Program area is read in the map on the EEPROM utility (data stored in the EEPROM of the camcorder is not yet rewritten at this stage). 3. Confirm that the Doctor data is read in the map. 4. Write the data in the EEPROM in the usual way. It is possible that the data only in the Doctor Program is rewritten with this process.
4-3
2. Data Deletion from Doctor Program Area Only If the microcomputer is replaced, it occasionally needs to delete the Doctor Program stored in the EEPROM. Although the service support system software has no data deletion function like the emergency utility, the Doctor Program can be deleted by the "Doctor Load" function. 1. Read out the EEPROM data. 2. Open the initial data file supplied with the service support system software by the "Doctor Load" function. Since nothing of the Doctor Program is written in the initial data file as mentioned previously, all data in the Doctor Program area are reset to "FEh" respectively as the initial data file is loaded, in other words, all data are apparently deleted from the Doctor Program area (data stored in the EEPROM of the camcorder is not yet rewritten at this stage). 3. Confirm that the Doctor data are reset to "FEh" in the map. 4. Write the data in the EEPROM in the usual way. It is possible that the data only in the Doctor Program is deleted with this process.
4-4
4.2 DOCTOR PROGRAM SYSTEM IN THE PRESENT CIRCUMSTANCES

Though it explained about the outline of the Doctor Program and the doctor complying with of the service support system software in the preceding clause, it explains here about the present circumstances of the Doctor Program system. 4.2.1 ON/OFF address and Program address The Doctor Program system is stored in the EEPROM. The system is divided into two blocks; one is the ON/OFF address block and the other is the program address block. Each address varies in the model. Moreover, those blocks may be away. In case of this model, the ON/OFF addresses are (1ACh ~ 1AFh), and program addresses are (2A4h ~ 2F4h, 77h, DAh ~ DFh). For other models, refer to the table 4-2-3. Address list of Doctor Program of the postscript. The contents of the ON/OFF address and the program address are as mentioned in the following. For the ON/OFF addresses, write as follows. To answer to the Doctor system: 1ACh = 12h / 1ADh = 34h / 1AEh = 56h / 1AFh = 78h Not to answer to the Doctor system: 1ACh to 1AFh = 00h For the program addresses, write as follows. To answer to the Doctor system: Programmed data Not to answer to the Doctor system: "FEh" or any data It can be considered that there are four kinds of combinations in theory, and those combinations determine ON or OFF of the Doctor Program system. As shown in the Table 4-2-1, the combination that turns the Doctor Program system on is the pattern (1) only. The pattern (2) turns the Doctor Program system off because "FEh" is written for all the program addresses, in which "FEh" is a cancelable data even when the ON/OFF address is in the ON status. The pattern (3) is invalid even when an optional data is written in, because the ON/OFF address is in the OFF status. In practice there are two patterns of (1) and (4). In case of the pattern (1), if 33h is written for the address 1ADh for example, the Doctor Program system turns off. When all aforementioned data are written in four addresses properly, and Doctor Program system becomes on for the first time.
Program Address Programmed Data 1ACh = 12h 1ADh = 34h 1AEh = 56h 1AFh = 78h (ON) 1ACh = 00h 1ADh = 00h 1AEh = 00h 1AFh = 00h (OFF) "Feh" or any data
ON(1)
OFF(2)
ON/OFF Address
OFF(3)
OFF(4)
Table 4-2-1 Combinations of ON/OFF Address and Program Address
4-5
As mentioning above, it is unacceptable by using the service support system software to edit the doctor area directly at the time of the repair. However, when writing of the initial data or the backup data is done, the doctor area is also rewritten at the same time. Also, it is possible to turn off or renew the Doctor Program by using the "Doctor Load" function. Table 4-2-2 shows the combinations that may be probably programmed in practice now.
Original Data ON/OFF Address ON ON OFF ON ON OFF Program Address Correct Incorrect FEh Correct Incorrect FEh Writing Data ON/OFF Address ON ON ON OFF OFF OFF Program Address Correct Correct Correct FEh FEh FEh Yes: Normal No: Locked Yes Yes 1 No Yes 2 Yes Yes 3 Yes Yes 4 No Yes 5 Yes Yes 6
Change
Table 4-2-2 Changing situations of Doctor Program The following explains each pattern from 1 to 6. 1: For the camcorder that Doctor Program System has been turned on, but it is replaced with another Doctor Program System for improvement of the performance. 2: For the camcorder that has been locked because the data of the Doctor Program was broken for some reason, the same Doctor Program is written again to release the set from the locked status. 3: For the camcorder that Doctor Program System has been turned off, the Doctor Program is written for improving the performance. 4: For the camcorder that Doctor Program System has been turned on, the microcomputer is replaced with an upgraded one. 5: It is required to release the set temporarily from the same locked status as the case 2. 6: For usual EEPROM data writing, which does not affect the Doctor Program System. Under the locked condition such as 2 or 5, if the camera system fails in communication such as it completely dead, the camera system cannot be recovered by rewriting the data of the EEPROM. In such the case, it needs to replace the EEPROM with a new one and to write original data in it or to adjust all items after writing the initial data in the new EEPROM. However, the communication may be recovered by turning on in the deck mode after disconnecting the DC power supply once and connecting it again if the deck system does not affected by the trouble. If the communication is recovered by the above means, turn off the Doctor Program System using the Doctor Load function. Unless there occurs a trouble, don't use the Doctor Load function. Usual editing of the EEPROM and rewriting the initial data don't bring on any trouble.
4-6
4.2.2 Writing function of EEPROM data The writing function of the previous service support system software (before complying with the doctor system) was the method which data are written in one after another as the turn of the address. If the ON/OFF address is younger than the Program address, the data renewal process becomes the following. A problem occurs when it tries to write the data that the Doctor Program system is on in this method. Rewriting of ON/OFF address data first Rewriting of program address data next The Doctor system becomes on the moment "78h" is written at the end of the ON/OFF address. There is actually no problem at this moment if all program addresses are "FEh" that means cancellation. But after that, the Doctor Program area begins to be written. The camera system becomes locked condition the moment data were written in the first address. The Doctor Program handles the whole of the program addresses as a lump. The locked condition happens because the program is destroyed by different data's there being written. So, the present service support system that is complying with the doctor system is programmed by the following process to prevent the camera from such the trouble as mentioned above. This process does not bring on such the trouble, because the Doctor Program System is turned on at the last stage of the process. Memorizing the ON/OFF address data from the EEPROM Writing "00h" in all the ON/OFF addresses Rewriting the data of the program addresses Writing the memorized data in the ON/OFF addresses 4.2.3 Upgrade of the service support system At present, though the initial data attached to the service support system should turn off all the Doctor Programs in consideration of the safety, that is not necessarily the best way. To make the initial data with the Doctor Program, it is indispensable that the congeniality decision with the microcomputers version on the camera can be done easily. So, the function which congeniality is judged automatically now is being developed. The microcomputers version is read at the time of writing, then it is checked whether the Doctor Program corresponds to the microcomputer or not. For the purpose of this, the microcomputers version information corresponded with the Doctor Program is included into the initial data file. Also, it is possible to make the backup data containing the microcomputers version information. This is convenient when data are returned after replacement of the circuit board. If this is realized, the trouble that relates to Doctor Program will be dissolved. As for Upgrade, it will be able to be released soon.
4-7
4.2.4 Address list of the doctor program area

Models GR-DVL7 GR-DVL9500U GR-DVL9500EG/DVL9500EK GR-DVL9600EG/DVL9600EK GR-DVL9600EA/DVL9600A Doctor ON/OFF Address 3ACh 3ADh 3AEh 3AFh GR-DVX7/DVM50U/DVM70U GR-DVX4EG/DVX7EG/DVX4EK/DVX7EK GR-DVX40A/DVX70A/DVX40SH/DVX70SH GR-DVX4EA/DVX7EA VMD8 1C4h 1C5h 1C6h 1C7h GR-DVA1/DVF1/DVF11U/DVF21U/DVF31U GR-DVL40EG/DVL40EK/DVL30EG/DVL30EK GR-DVL20EG/DVL20EK GR-DVL25A/DVL20EA/DVL28ED/DVL33SH GR-DVL45A/DVL40EA/DVL48ED/DVL38SH VMD2/VMD3 1C4h 1C5h 1C6h 1C7h GR-DVL700 GR-DVL9800U GR-DVL9800EG/DVL9800EK GR-DVL9700EG/DVL9700EK VMD10/VMD20 6F0h 6F1h 6F2h 6F3h GR-DVA10/DVF10 series GR-DVL300U/DVL300UM series GR-DVL300KR/DVL805KR series GR-DVL300EG/DVL300EK series GR-DVL300A/DVL300A-S series GR-DVL300EA/DVL300ED series CC9370 1ACh 1ADh 1AEh 1AFh Data 12h 34h 3B0h to 3CFh 56h 78h 12h 34h 1A0h to 1C3h 56h 78h 12h 34h 290h to 2F4h 56h 78h 12h 34h 600h to 61Bh 56h 78h 12h 34h 56h 78h 77h DAh to DFh 2A4h to 2D6h Doctor Program Address
Table 4-2-3 Address list of the doctor program area
4-8
VICTOR COMPANY OF JAPAN, LIMITED
Printed in Japan 2000-09 (TM1)

JVC 2000 Basic DVC Models Technical Guide

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VIDEO TECHNICAL GUIDE

DIGITAL VIDEO CAMERA

2000 Basic DVC Models

COPYRIGHT 2000 VICTOR COMPANY OF JAPAN, LTD.

No. 86056 September 2000

SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT

SECTION 3 HEAD CLOG WARNING

SECTION 4 DOCTOR SYSTEM

SECTION 1 OUTLINE OF THE PROCUCTS

Viewfinder LCD monitor

Playback digital zoom Yes 10 RM-V712U

Table 1-1-1 Comparison table of DV models specification by products year (1/2)

Comparison table of DV models specification by products year (2/2)

Yes (Frame Advance) RM-V716U Yes Yes (SP only)

Yes (No: GR-DVF11U)

Digital still image output terminal

Yes (No: GR-DVF11U)

Yes (EG/EK Model Output only)

JLIP related software

06 Yes Yes: CR-2025 type

Yes: CR-2032 type (built-in)

Table 1-1-1 Comparison table of DV models specification by products year (2/2)

1.1.2 Specification of the DVC models

MMC MMC MMC MMC MMC MMC MMC MMC MMC -

Table 1-1-2 Specification of the DVC models

SECTION 2 EXPLANATION OF ELECTRICAL CIRCUIT

IC7604 EEP ROM IC7603 IC7101 LCD DRIVER

DYO(4),DCO(4) DYI(4),DCI(4) ATF_GAIN, M_VCOCTL PBVCOCTL, FSPLLCTL

FOCUS DRIVER & ZOOM DRIVER

IRIS DRIVER & HALL AMP

S_DT_OUT S_DT_IN M32_DTOUT M32_DTIN

JLIP_RX A_OUT / L JLIP_TX A_OUT / R

REC AMP & PB AMP

RECC_ADJ C_COIL_U C_COIL_V C_COIL_W D_COIL_U D_COIL_V D_COIL_W

V_OUT DV_Y Y_OUT C_OUT

LOAD_FWD LOAD_REV MDA_IN

Fig. 2-1-1 Basic block diagram

2.2 CCD (ICX220AK/ICX221BK)

Fig. 2-2-1 CCD block diagram

Interline type CCD image sensor

Table 2-2-1 CCD functions

Table 2-2-2 CCD pin function

PAL: effective 740,000 (Im a g e 4 0 0,000) pixels

711(H) 962(H) 13.5MHz 18MHz 3.80 m

702(H) 962(H) 13.5MHz 18MHz 3.85 m

510H-type/760H-type 1/4" CCD for VHS-C

PAL (760H-type): effective 440,000 pixels

VHS-C PAL 9.45833MHz 908fH 2/3 PAL (760H) 14.1875MHz 908fH

Horizontal drive frequency

Pixel number and pixel size of various CCD

On-chip microlens Ineffective Light

On-chip microlens Ineffective Light

Effective Photo shielding AI Transfer section Transfer section

Effective Photo shielding AI Transfer Sensor Transfer section section

Fig. 2-2-3 Structural drawing of CCD image sensor

On-chip microlens Color filter

Poly Si Sensor V. Register Sensor

Fig. 2-2-4 Structural drawing of internal lens

2.2.3 Numbers of pixel for main models

1/3 Progressive scan 1/4

approx. 380,000 758H 504V

approx. 420,000 724H 582V

approx. 360,000 724H 494V